FullO3CPU< Impl > Member List

This is the complete list of members for FullO3CPU< Impl >, including all inherited members.

_cacheLineSize	BaseCPU	protected
_cpuId	BaseCPU	protected
_dataMasterId	BaseCPU	protected
_instMasterId	BaseCPU	protected
_params	SimObject	protected
_pid	BaseCPU	protected
_socketId	BaseCPU	protected
_status	FullO3CPU< Impl >
_switchedOut	BaseCPU	protected
_taskId	BaseCPU	protected
activateContext(ThreadID tid) override	FullO3CPU< Impl >	virtual
activateStage(const StageIdx idx)	FullO3CPU< Impl >	inline
activateThread(ThreadID tid)	FullO3CPU< Impl >
activeThreads	FullO3CPU< Impl >	protected
activityRec	FullO3CPU< Impl >	private
activityThisCycle()	FullO3CPU< Impl >	inline
addInst(const DynInstPtr &inst)	FullO3CPU< Impl >
addStat(Stats::Info *info)	Stats::Group
addStatGroup(const char *name, Group *block)	Stats::Group
addThreadToExitingList(ThreadID tid)	FullO3CPU< Impl >
armMonitor(ThreadID tid, Addr address)	BaseCPU
BaseCPU(Params *params, bool is_checker=false)	BaseCPU
BaseO3CPU(BaseCPUParams *params)	BaseO3CPU
Blocked enum value	FullO3CPU< Impl >
cacheLineSize() const	BaseCPU	inline
ccRegfileReads	FullO3CPU< Impl >
ccRegfileWrites	FullO3CPU< Impl >
checker	FullO3CPU< Impl >
checkInterrupts(ThreadContext *tc) const	BaseCPU	inline
cleanUpRemovedInsts()	FullO3CPU< Impl >
clearInterrupt(ThreadID tid, int int_num, int index)	BaseCPU	inline
clearInterrupts(ThreadID tid)	BaseCPU	inline
Clocked(ClockDomain &clk_domain)	Clocked	inlineprotected
Clocked(Clocked &)=delete	Clocked	protected
clockEdge(Cycles cycles=Cycles(0)) const	Clocked	inline
ClockedObject(const ClockedObjectParams *p)	ClockedObject
clockPeriod() const	Clocked	inline
clockPeriodUpdated()	Clocked	inlineprotectedvirtual
commit	FullO3CPU< Impl >	protected
commitDrained(ThreadID tid)	FullO3CPU< Impl >
CommitIdx enum value	FullO3CPU< Impl >
commitRenameMap	FullO3CPU< Impl >	protected
committedInsts	FullO3CPU< Impl >
committedOps	FullO3CPU< Impl >
contextToThread(ContextID cid)	BaseCPU	inline
cpi	FullO3CPU< Impl >
CPU_STATE_ON enum value	BaseCPU	protected
CPU_STATE_SLEEP enum value	BaseCPU	protected
CPU_STATE_WAKEUP enum value	BaseCPU	protected
cpuId() const	BaseCPU	inline
CPUPolicy typedef	FullO3CPU< Impl >
CPUState enum name	BaseCPU	protected
cpuWaitList	FullO3CPU< Impl >
curCycle() const	Clocked	inline
currentSection()	Serializable	static
cyclesToTicks(Cycles c) const	Clocked	inline
dataMasterId() const	BaseCPU	inline
deactivateStage(const StageIdx idx)	FullO3CPU< Impl >	inline
deactivateThread(ThreadID tid)	FullO3CPU< Impl >
decode	FullO3CPU< Impl >	protected
DecodeIdx enum value	FullO3CPU< Impl >
decodeQueue	FullO3CPU< Impl >
DecodeStruct typedef	FullO3CPU< Impl >
demapDataPage(Addr vaddr, uint64_t asn)	FullO3CPU< Impl >	inline
demapInstPage(Addr vaddr, uint64_t asn)	FullO3CPU< Impl >	inline
demapPage(Addr vaddr, uint64_t asn)	FullO3CPU< Impl >	inline
deschedule(Event &event)	EventManager	inline
deschedule(Event *event)	EventManager	inline
deschedulePowerGatingEvent()	BaseCPU
drain() override	FullO3CPU< Impl >	virtual
Drainable()	Drainable	protected
drainResume() override	FullO3CPU< Impl >	virtual
drainSanityCheck() const	FullO3CPU< Impl >	private
drainState() const	Drainable	inline
dtb	FullO3CPU< Impl >
dumpInsts()	FullO3CPU< Impl >
DynInstPtr typedef	FullO3CPU< Impl >
enterPwrGating()	BaseCPU	protected
enterPwrGatingEvent	BaseCPU	protected
EventManager(EventManager &em)	EventManager	inline
EventManager(EventManager *em)	EventManager	inline
EventManager(EventQueue *eq)	EventManager	inline
eventq	EventManager	protected
eventQueue() const	EventManager	inline
exitingThreads	FullO3CPU< Impl >	protected
exitThreads()	FullO3CPU< Impl >
fetch	FullO3CPU< Impl >	protected
FetchIdx enum value	FullO3CPU< Impl >
fetchQueue	FullO3CPU< Impl >
FetchStruct typedef	FullO3CPU< Impl >
find(const char *name)	SimObject	static
findContext(ThreadContext *tc)	BaseCPU
flushTLBs()	BaseCPU
fpRegfileReads	FullO3CPU< Impl >
fpRegfileWrites	FullO3CPU< Impl >
freeList	FullO3CPU< Impl >	protected
frequency() const	Clocked	inline
FullO3CPU(DerivO3CPUParams *params)	FullO3CPU< Impl >
getAndIncrementInstSeq()	FullO3CPU< Impl >	inline
getContext(int tn)	BaseCPU	inlinevirtual
getCpuAddrMonitor(ThreadID tid)	BaseCPU	inline
getCurrentInstCount(ThreadID tid)	BaseCPU
getDataPort() override	FullO3CPU< Impl >	inlinevirtual
getFreeTid()	FullO3CPU< Impl >
getInstPort() override	FullO3CPU< Impl >	inlinevirtual
getInterruptController(ThreadID tid)	BaseCPU	inline
getInterrupts()	FullO3CPU< Impl >
getPid() const	BaseCPU	inline
getPort(const std::string &if_name, PortID idx=InvalidPortID) override	BaseCPU	virtual
getProbeManager()	SimObject
getSendFunctional()	BaseCPU	inlinevirtual
getStatGroups() const	Stats::Group
getStats() const	Stats::Group
getTracer()	BaseCPU	inline
getWritableArchVecPredReg(int reg_idx, ThreadID tid)	FullO3CPU< Impl >
getWritableArchVecReg(int reg_idx, ThreadID tid)	FullO3CPU< Impl >
getWritableVecPredReg(PhysRegIdPtr reg_idx)	FullO3CPU< Impl >
getWritableVecReg(PhysRegIdPtr reg_idx)	FullO3CPU< Impl >
globalSeqNum	FullO3CPU< Impl >
Group()=delete	Stats::Group
Group(const Group &)=delete	Stats::Group
Group(Group *parent, const char *name=nullptr)	Stats::Group
halt()	FullO3CPU< Impl >	inline
haltContext(ThreadID tid) override	FullO3CPU< Impl >	virtual
Halted enum value	FullO3CPU< Impl >
Idle enum value	FullO3CPU< Impl >
idleCycles	FullO3CPU< Impl >
iew	FullO3CPU< Impl >	protected
IEWIdx enum value	FullO3CPU< Impl >
iewQueue	FullO3CPU< Impl >
IEWStruct typedef	FullO3CPU< Impl >
ImplState typedef	FullO3CPU< Impl >
init() override	FullO3CPU< Impl >	virtual
initState()	SimObject	virtual
insertThread(ThreadID tid)	FullO3CPU< Impl >
instAddr(ThreadID tid)	FullO3CPU< Impl >
instCnt	BaseCPU	protected
instCount()	BaseCPU	inline
instcount	FullO3CPU< Impl >
instDone(ThreadID tid, const DynInstPtr &inst)	FullO3CPU< Impl >
instList	FullO3CPU< Impl >
instMasterId() const	BaseCPU	inline
interrupts	BaseCPU	protected
intRegfileReads	FullO3CPU< Impl >
intRegfileWrites	FullO3CPU< Impl >
invldPid	BaseCPU	static
ipc	FullO3CPU< Impl >
isa	FullO3CPU< Impl >	protected
isCpuDrained() const	FullO3CPU< Impl >	private
isDraining() const	FullO3CPU< Impl >	inline
isThreadExiting(ThreadID tid) const	FullO3CPU< Impl >
itb	FullO3CPU< Impl >
lastActivatedCycle	FullO3CPU< Impl >
lastRunningCycle	FullO3CPU< Impl >
ListIt typedef	FullO3CPU< Impl >
loadState(CheckpointIn &cp)	SimObject	virtual
LSQRequest typedef	FullO3CPU< Impl >
memInvalidate()	SimObject	inlinevirtual
memWriteback()	SimObject	inlinevirtual
microcodeRom	BaseCPU
microPC(ThreadID tid)	FullO3CPU< Impl >
miscRegfileReads	FullO3CPU< Impl >
miscRegfileWrites	FullO3CPU< Impl >
mwait(ThreadID tid, PacketPtr pkt)	BaseCPU
mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb)	BaseCPU
name() const	SimObject	inlinevirtual
nextCycle() const	Clocked	inline
nextInstAddr(ThreadID tid)	FullO3CPU< Impl >
notifyFork()	Drainable	inlinevirtual
numActiveThreads()	FullO3CPU< Impl >	inline
numContexts()	BaseCPU	inline
numCycles	BaseCPU
numSimulatedCPUs()	BaseCPU	inlinestatic
numSimulatedInsts()	BaseCPU	inlinestatic
numSimulatedInsts()	BaseCPU	inlinestatic
numSimulatedOps()	BaseCPU	inlinestatic
numSimulatedOps()	BaseCPU	inlinestatic
NumStages enum value	FullO3CPU< Impl >
numThreads	BaseCPU
numWorkItemsCompleted	BaseCPU
numWorkItemsStarted	BaseCPU
O3CPU typedef	FullO3CPU< Impl >
O3ThreadContext< Impl > class	FullO3CPU< Impl >	friend
SimObject::operator=(const Group &)=delete	Stats::Group
Clocked::operator=(Clocked &)=delete	Clocked	protected
params() const	BaseCPU	inline
Params typedef	BaseCPU
PCMask	BaseCPU	static
pcState(const TheISA::PCState &newPCState, ThreadID tid)	FullO3CPU< Impl >
pcState(ThreadID tid)	FullO3CPU< Impl >
pmuProbePoint(const char *name)	BaseCPU	protected
postInterrupt(ThreadID tid, int int_num, int index)	BaseCPU	inline
powerGatingOnIdle	BaseCPU	protected
powerState	ClockedObject
ppActiveCycles	BaseCPU	protected
ppAllCycles	BaseCPU	protected
ppDataAccessComplete	FullO3CPU< Impl >
ppInstAccessComplete	FullO3CPU< Impl >
ppRetiredBranches	BaseCPU	protected
ppRetiredInsts	BaseCPU	protected
ppRetiredInstsPC	BaseCPU	protected
ppRetiredLoads	BaseCPU	protected
ppRetiredStores	BaseCPU	protected
ppSleeping	BaseCPU	protected
preDumpStats()	Stats::Group	virtual
previousCycle	BaseCPU	protected
previousState	BaseCPU	protected
probeInstCommit(const StaticInstPtr &inst, Addr pc)	BaseCPU	virtual
processInterrupts(const Fault &interrupt)	FullO3CPU< Impl >
processProfileEvent()	BaseCPU
profileEvent	BaseCPU
pushRequest(const DynInstPtr &inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op=nullptr, const std::vector< bool > &byte_enable=std::vector< bool >())	FullO3CPU< Impl >	inline
pwrGatingLatency	BaseCPU	protected
quiesceCycles	FullO3CPU< Impl >
read(LSQRequest *req, int load_idx)	FullO3CPU< Impl >	inline
readArchCCReg(int reg_idx, ThreadID tid)	FullO3CPU< Impl >
readArchFloatReg(int reg_idx, ThreadID tid)	FullO3CPU< Impl >
readArchIntReg(int reg_idx, ThreadID tid)	FullO3CPU< Impl >
readArchVecElem(const RegIndex &reg_idx, const ElemIndex &ldx, ThreadID tid) const	FullO3CPU< Impl >
readArchVecLane(int reg_idx, int lId, ThreadID tid) const	FullO3CPU< Impl >	inline
readArchVecPredReg(int reg_idx, ThreadID tid) const	FullO3CPU< Impl >
readArchVecReg(int reg_idx, ThreadID tid) const	FullO3CPU< Impl >
readCCReg(PhysRegIdPtr phys_reg)	FullO3CPU< Impl >
readFloatReg(PhysRegIdPtr phys_reg)	FullO3CPU< Impl >
readIntReg(PhysRegIdPtr phys_reg)	FullO3CPU< Impl >
readMiscReg(int misc_reg, ThreadID tid)	FullO3CPU< Impl >
readMiscRegNoEffect(int misc_reg, ThreadID tid) const	FullO3CPU< Impl >
readVecElem(PhysRegIdPtr reg_idx) const	FullO3CPU< Impl >
readVecLane(PhysRegIdPtr phys_reg) const	FullO3CPU< Impl >	inline
readVecLane(PhysRegIdPtr phys_reg) const	FullO3CPU< Impl >	inline
readVecPredReg(PhysRegIdPtr reg_idx) const	FullO3CPU< Impl >
readVecReg(PhysRegIdPtr reg_idx) const	FullO3CPU< Impl >
regFile	FullO3CPU< Impl >	protected
registerThreadContexts()	BaseCPU
regProbeListeners()	SimObject	virtual
regProbePoints() override	FullO3CPU< Impl >	virtual
regStats() override	FullO3CPU< Impl >	virtual
removeFrontInst(const DynInstPtr &inst)	FullO3CPU< Impl >
removeInstsNotInROB(ThreadID tid)	FullO3CPU< Impl >
removeInstsThisCycle	FullO3CPU< Impl >
removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)	FullO3CPU< Impl >
removeList	FullO3CPU< Impl >
removeThread(ThreadID tid)	FullO3CPU< Impl >
rename	FullO3CPU< Impl >	protected
RenameIdx enum value	FullO3CPU< Impl >
renameMap	FullO3CPU< Impl >	protected
renameQueue	FullO3CPU< Impl >
RenameStruct typedef	FullO3CPU< Impl >
reschedule(Event &event, Tick when, bool always=false)	EventManager	inline
reschedule(Event *event, Tick when, bool always=false)	EventManager	inline
resetClock() const	Clocked	inlineprotected
resetStats()	Stats::Group	virtual
resolveStat(std::string name) const	Stats::Group
rob	FullO3CPU< Impl >	protected
Running enum value	FullO3CPU< Impl >
schedule(Event &event, Tick when)	EventManager	inline
schedule(Event *event, Tick when)	EventManager	inline
scheduleInstStop(ThreadID tid, Counter insts, const char *cause)	BaseCPU
schedulePowerGatingEvent()	BaseCPU
scheduleThreadExitEvent(ThreadID tid)	FullO3CPU< Impl >
scheduleTickEvent(Cycles delay)	FullO3CPU< Impl >	inlineprivate
scoreboard	FullO3CPU< Impl >	protected
Serializable()	Serializable
serialize(CheckpointOut &cp) const override	BaseCPU	virtual
serializeAll(CheckpointOut &cp)	SimObject	static
Serializable::serializeAll(const std::string &cpt_dir)	Serializable	static
serializeSection(CheckpointOut &cp, const char *name) const	Serializable
serializeSection(CheckpointOut &cp, const std::string &name) const	Serializable	inline
serializeThread(CheckpointOut &cp, ThreadID tid) const override	FullO3CPU< Impl >	virtual
setArchCCReg(int reg_idx, RegVal val, ThreadID tid)	FullO3CPU< Impl >
setArchFloatReg(int reg_idx, RegVal val, ThreadID tid)	FullO3CPU< Impl >
setArchIntReg(int reg_idx, RegVal val, ThreadID tid)	FullO3CPU< Impl >
setArchVecElem(const RegIndex &reg_idx, const ElemIndex &ldx, const VecElem &val, ThreadID tid)	FullO3CPU< Impl >
setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD &val)	FullO3CPU< Impl >	inline
setArchVecPredReg(int reg_idx, const VecPredRegContainer &val, ThreadID tid)	FullO3CPU< Impl >
setArchVecReg(int reg_idx, const VecRegContainer &val, ThreadID tid)	FullO3CPU< Impl >
setCCReg(PhysRegIdPtr phys_reg, RegVal val)	FullO3CPU< Impl >
setCurTick(Tick newVal)	EventManager	inline
setFloatReg(PhysRegIdPtr phys_reg, RegVal val)	FullO3CPU< Impl >
setIntReg(PhysRegIdPtr phys_reg, RegVal val)	FullO3CPU< Impl >
setMiscReg(int misc_reg, RegVal val, ThreadID tid)	FullO3CPU< Impl >
setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)	FullO3CPU< Impl >
setPid(uint32_t pid)	BaseCPU	inline
setVecElem(PhysRegIdPtr reg_idx, const VecElem &val)	FullO3CPU< Impl >
setVecLane(PhysRegIdPtr phys_reg, const LD &val)	FullO3CPU< Impl >	inline
setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer &val)	FullO3CPU< Impl >
setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer &val)	FullO3CPU< Impl >
setVectorsAsReady(ThreadID tid)	FullO3CPU< Impl >
signalDrainDone() const	Drainable	inlineprotected
SimObject(const Params *_params)	SimObject
socketId() const	BaseCPU	inline
squashFromTC(ThreadID tid)	FullO3CPU< Impl >
squashInstIt(const ListIt &instIt, ThreadID tid)	FullO3CPU< Impl >	inline
StageIdx enum name	FullO3CPU< Impl >
startup() override	FullO3CPU< Impl >	virtual
Status enum name	FullO3CPU< Impl >
suspendContext(ThreadID tid) override	FullO3CPU< Impl >	virtual
SwitchedOut enum value	FullO3CPU< Impl >
switchedOut() const	BaseCPU	inline
switchOut() override	FullO3CPU< Impl >	virtual
switchRenameMode(ThreadID tid, UnifiedFreeList *freelist)	FullO3CPU< Impl >
syscall(ThreadID tid, Fault *fault)	FullO3CPU< Impl >
syscallRetryLatency	BaseCPU
system	FullO3CPU< Impl >
takeOverFrom(BaseCPU *oldCPU) override	FullO3CPU< Impl >	virtual
taskId() const	BaseCPU	inline
taskId(uint32_t id)	BaseCPU	inline
tcBase(ThreadID tid)	FullO3CPU< Impl >	inline
Thread typedef	FullO3CPU< Impl >
thread	FullO3CPU< Impl >
threadContexts	BaseCPU	protected
threadExitEvent	FullO3CPU< Impl >	private
threadMap	FullO3CPU< Impl >
tick()	FullO3CPU< Impl >
tickEvent	FullO3CPU< Impl >	private
ticksToCycles(Tick t) const	Clocked	inline
tids	FullO3CPU< Impl >
timeBuffer	FullO3CPU< Impl >
timesIdled	FullO3CPU< Impl >
TimeStruct typedef	FullO3CPU< Impl >
totalCpi	FullO3CPU< Impl >
totalInsts() const override	FullO3CPU< Impl >	virtual
totalIpc	FullO3CPU< Impl >
totalOps() const override	FullO3CPU< Impl >	virtual
traceFunctions(Addr pc)	BaseCPU	inline
tracer	BaseCPU	protected
trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst)	FullO3CPU< Impl >
tryDrain()	FullO3CPU< Impl >	private
unscheduleTickEvent()	FullO3CPU< Impl >	inlineprivate
unserialize(CheckpointIn &cp) override	BaseCPU	virtual
unserializeGlobals(CheckpointIn &cp)	Serializable	static
unserializeSection(CheckpointIn &cp, const char *name)	Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)	Serializable	inline
unserializeThread(CheckpointIn &cp, ThreadID tid) override	FullO3CPU< Impl >	virtual
updateClockPeriod()	Clocked	inline
updateCycleCounters(CPUState state)	BaseCPU	inlineprotected
updateThreadPriority()	FullO3CPU< Impl >
VecElem typedef	FullO3CPU< Impl >
vecMode	FullO3CPU< Impl >	protected
VecPredRegContainer typedef	FullO3CPU< Impl >
vecPredRegfileReads	FullO3CPU< Impl >	mutable
vecPredRegfileWrites	FullO3CPU< Impl >
VecRegContainer typedef	FullO3CPU< Impl >
vecRegfileReads	FullO3CPU< Impl >	mutable
vecRegfileWrites	FullO3CPU< Impl >
vecRenameMode() const	FullO3CPU< Impl >	inline
vecRenameMode(Enums::VecRegRenameMode vec_mode)	FullO3CPU< Impl >	inline
verifyMemoryMode() const override	FullO3CPU< Impl >	virtual
voltage() const	Clocked	inline
waitForRemoteGDB() const	BaseCPU
wakeCPU()	FullO3CPU< Impl >
wakeup(ThreadID tid) override	FullO3CPU< Impl >	virtual
wakeupEventQueue(Tick when=(Tick) -1)	EventManager	inline
workItemBegin()	BaseCPU	inline
workItemEnd()	BaseCPU	inline
write(LSQRequest *req, uint8_t *data, int store_idx)	FullO3CPU< Impl >	inline
~BaseCPU()	BaseCPU	virtual
~Clocked()	Clocked	inlineprotectedvirtual
~Drainable()	Drainable	protectedvirtual
~FullO3CPU()	FullO3CPU< Impl >
~Group()	Stats::Group	virtual
~Serializable()	Serializable	virtual
~SimObject()	SimObject	virtual