gem5  v20.0.0.3
RiscvISA::ISA Member List

This is the complete list of members for RiscvISA::ISA, including all inherited members.

_paramsSimObjectprotected
addStat(Stats::Info *info)Stats::Group
addStatGroup(const char *name, Group *block)Stats::Group
clear(ThreadContext *tc)RiscvISA::ISAinline
clear()RiscvISA::ISAprotected
currentSection()Serializablestatic
deschedule(Event &event)EventManagerinline
deschedule(Event *event)EventManagerinline
drain() overrideSimObjectinlinevirtual
Drainable()Drainableprotected
drainResume()Drainableinlineprotectedvirtual
drainState() constDrainableinline
EventManager(EventManager &em)EventManagerinline
EventManager(EventManager *em)EventManagerinline
EventManager(EventQueue *eq)EventManagerinline
eventqEventManagerprotected
eventQueue() constEventManagerinline
find(const char *name)SimObjectstatic
flattenCCIndex(int reg) constRiscvISA::ISAinline
flattenFloatIndex(int reg) constRiscvISA::ISAinline
flattenIntIndex(int reg) constRiscvISA::ISAinline
flattenMiscIndex(int reg) constRiscvISA::ISAinline
flattenRegId(const RegId &regId) constRiscvISA::ISAinline
flattenVecElemIndex(int reg) constRiscvISA::ISAinline
flattenVecIndex(int reg) constRiscvISA::ISAinline
flattenVecPredIndex(int reg) constRiscvISA::ISAinline
getPort(const std::string &if_name, PortID idx=InvalidPortID)SimObjectvirtual
getProbeManager()SimObject
getStatGroups() constStats::Group
getStats() constStats::Group
Group()=deleteStats::Group
Group(const Group &)=deleteStats::Group
Group(Group *parent, const char *name=nullptr)Stats::Group
hpmCounterEnabled(int counter) constRiscvISA::ISAprotected
init()SimObjectvirtual
initState()SimObjectvirtual
ISA(Params *p)RiscvISA::ISA
loadState(CheckpointIn &cp)SimObjectvirtual
memInvalidate()SimObjectinlinevirtual
memWriteback()SimObjectinlinevirtual
miscRegFileRiscvISA::ISAprotected
name() constSimObjectinlinevirtual
notifyFork()Drainableinlinevirtual
operator=(const Group &)=deleteStats::Group
Params typedefRiscvISA::ISA
params() constRiscvISA::ISA
preDumpStats()Stats::Groupvirtual
readMiscReg(int misc_reg, ThreadContext *tc)RiscvISA::ISA
readMiscRegNoEffect(int misc_reg) constRiscvISA::ISA
regProbeListeners()SimObjectvirtual
regProbePoints()SimObjectvirtual
regStats()Stats::Groupvirtual
reschedule(Event &event, Tick when, bool always=false)EventManagerinline
reschedule(Event *event, Tick when, bool always=false)EventManagerinline
resetStats()Stats::Groupvirtual
resolveStat(std::string name) constStats::Group
schedule(Event &event, Tick when)EventManagerinline
schedule(Event *event, Tick when)EventManagerinline
Serializable()Serializable
serialize(CheckpointOut &cp) constRiscvISA::ISAvirtual
serializeAll(CheckpointOut &cp)SimObjectstatic
Serializable::serializeAll(const std::string &cpt_dir)Serializablestatic
serializeSection(CheckpointOut &cp, const char *name) constSerializable
serializeSection(CheckpointOut &cp, const std::string &name) constSerializableinline
setCurTick(Tick newVal)EventManagerinline
setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)RiscvISA::ISA
setMiscRegNoEffect(int misc_reg, RegVal val)RiscvISA::ISA
signalDrainDone() constDrainableinlineprotected
SimObject(const Params *_params)SimObject
startup(ThreadContext *tc)RiscvISA::ISAinline
BaseISA::startup()SimObjectvirtual
takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)BaseISAinlinevirtual
unserialize(CheckpointIn &cp)RiscvISA::ISAvirtual
unserializeGlobals(CheckpointIn &cp)Serializablestatic
unserializeSection(CheckpointIn &cp, const char *name)Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)Serializableinline
wakeupEventQueue(Tick when=(Tick) -1)EventManagerinline
~Drainable()Drainableprotectedvirtual
~Group()Stats::Groupvirtual
~Serializable()Serializablevirtual
~SimObject()SimObjectvirtual

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