gpu_isa.hh

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/*
 * Copyright (c) 2016-2018 Advanced Micro Devices, Inc.
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 * For use for simulation and test purposes only
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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 * Authors: Anthony Gutierrez
 */

#ifndef __ARCH_GCN3_GPU_ISA_HH__
#define __ARCH_GCN3_GPU_ISA_HH__

#include <array>

#include "arch/gcn3/registers.hh"
#include "gpu-compute/dispatcher.hh"
#include "gpu-compute/hsa_queue_entry.hh"
#include "gpu-compute/misc.hh"

class Wavefront;

namespace Gcn3ISA
{
    class GPUISA
    {
      public:
        GPUISA(Wavefront &wf);

        ScalarRegU32 readMiscReg(int opIdx) const;
        void writeMiscReg(int opIdx, ScalarRegU32 operandVal);
        bool hasScalarUnit() const { return true; }
        void advancePC(GPUDynInstPtr gpuDynInst);

      private:
        ScalarRegU32 readPosConstReg(int opIdx) const
        {
            return posConstRegs[opIdx - REG_INT_CONST_POS_MIN];
        }

        ScalarRegU32 readNegConstReg(int opIdx) const
        {
            return *((ScalarRegU32*)
                &negConstRegs[opIdx - REG_INT_CONST_NEG_MIN]);
        }

        static const std::array<const ScalarRegU32, NumPosConstRegs>
            posConstRegs;
        static const std::array<const ScalarRegI32, NumNegConstRegs>
            negConstRegs;

        // parent wavefront
        Wavefront &wavefront;

        // shader status bits
        StatusReg statusReg;
        // memory descriptor reg
        ScalarRegU32 m0;
    };
} // namespace Gcn3ISA

#endif // __ARCH_GCN3_GPU_ISA_HH__