cprintf.hh File Reference

#include <ios>
#include <iostream>
#include <list>
#include <string>
#include "base/cprintf_formats.hh"

Go to the source code of this file.

Classes
struct	cp::Print

Namespaces
	cp

Functions
void	ccprintf (cp::Print &print)
template<typename T , typename ... Args>
void	ccprintf (cp::Print &print, const T &value, const Args &...args)
template<typename ... Args>
void	ccprintf (std::ostream &stream, const char *format, const Args &...args)
template<typename ... Args>
void	cprintf (const char *format, const Args &...args)
template<typename ... Args>
std::string	csprintf (const char *format, const Args &...args)
template<typename ... Args>
void	ccprintf (std::ostream &stream, const std::string &format, const Args &...args)
template<typename ... Args>
void	cprintf (const std::string &format, const Args &...args)
template<typename ... Args>
std::string	csprintf (const std::string &format, const Args &...args)

Function Documentation

ccprintf() [1/4]

void ccprintf ( cp::Print &  print )

inline

Definition at line 127 of file cprintf.hh.

References cp::Print::end_args().

Referenced by abortHandler(), Terminal::accept(), Stats::Text::begin(), ccprintf(), MemTest::completeRequest(), cprintf(), csprintf(), sc_core::sc_report_handler::default_handler(), X86ISA::X86FaultBase::describe(), X86ISA::PageFault::describe(), Trace::Logger::dprintf_flag(), Trace::IntelTraceRecord::dump(), Trace::Logger::dump(), Trie< Key, Value >::Node::dump(), ProfileNode::dump(), FunctionProfile::dump(), Trie< Addr, TlbEntry >::dump(), dumpDmesgEntry(), Stats::Text::end(), AbstractMemory::functionalAccess(), PowerISA::MiscOp::generateDisassembly(), SparcISA::Mem::generateDisassembly(), ImmOp64::generateDisassembly(), SparcISA::Trap::generateDisassembly(), PowerISA::CondLogicOp::generateDisassembly(), PowerISA::PowerStaticInst::generateDisassembly(), ArmISA::SysDC64::generateDisassembly(), SparcISA::BranchDisp::generateDisassembly(), SparcISA::MemImm::generateDisassembly(), SparcISA::BlockMemMicro::generateDisassembly(), SparcISA::RdPriv::generateDisassembly(), ArmISA::SveIndexIIOp::generateDisassembly(), ArmISA::SveMemVecFillSpill::generateDisassembly(), SparcISA::IntOpImm::generateDisassembly(), RegRegImmImmOp64::generateDisassembly(), PowerISA::MemDispOp::generateDisassembly(), ArmISA::DataXImmOnlyOp::generateDisassembly(), SparcISA::WrPriv::generateDisassembly(), ArmISAInst::TmeImmOp64::generateDisassembly(), PowerISA::CondMoveOp::generateDisassembly(), MsrImmOp::generateDisassembly(), SparcISA::BlockMemImmMicro::generateDisassembly(), ArmISA::SveIndexIROp::generateDisassembly(), PowerISA::IntOp::generateDisassembly(), PowerISA::BranchPCRel::generateDisassembly(), RegRegRegImmOp64::generateDisassembly(), ArmISA::SveMemPredFillSpill::generateDisassembly(), ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), ArmISA::BranchRegReg64::generateDisassembly(), ArmISA::SveIndexRIOp::generateDisassembly(), SparcISA::WrPrivImm::generateDisassembly(), SparcISA::BranchImm13::generateDisassembly(), X86ISA::X86MicroopBase::generateDisassembly(), PowerISA::IntImmOp::generateDisassembly(), ArmISA::SveIndexRROp::generateDisassembly(), X86ISA::RegOpImm::generateDisassembly(), ArmISA::BranchRegReg::generateDisassembly(), ArmISA::SveContigMemSS::generateDisassembly(), PowerISA::BranchNonPCRel::generateDisassembly(), SparcISA::SetHi::generateDisassembly(), ArmISA::DataX1RegOp::generateDisassembly(), X86ISA::MediaOpImm::generateDisassembly(), ArmISA::SvePredCountOp::generateDisassembly(), PowerISA::IntShiftOp::generateDisassembly(), ArmISA::DataX1RegImmOp::generateDisassembly(), ArmISA::MemoryImm64::generateDisassembly(), PowerISA::FloatOp::generateDisassembly(), ImmOp::generateDisassembly(), ArmISA::SveContigMemSI::generateDisassembly(), ArmISA::SvePredCountPredOp::generateDisassembly(), ArmISA::DataX1Reg2ImmOp::generateDisassembly(), ArmISA::MemoryDImm64::generateDisassembly(), RegImmOp::generateDisassembly(), ArmISA::SveWhileOp::generateDisassembly(), ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), MiscRegImmOp64::generateDisassembly(), PowerISA::IntRotateOp::generateDisassembly(), ArmISA::DataX2RegOp::generateDisassembly(), ArmISA::MemoryDImmEx64::generateDisassembly(), ArmISA::SveCompTermOp::generateDisassembly(), ArmISA::BranchImmReg64::generateDisassembly(), ArmISA::MemoryPreIndex64::generateDisassembly(), ArmISA::DataX2RegImmOp::generateDisassembly(), ArmISA::SveUnaryPredOp::generateDisassembly(), PowerISA::BranchPCRelCond::generateDisassembly(), ArmISA::MemoryPostIndex64::generateDisassembly(), ArmISA::DataX3RegOp::generateDisassembly(), RegImmRegOp::generateDisassembly(), ArmISA::SveUnaryUnpredOp::generateDisassembly(), ArmISA::BranchImmImmReg64::generateDisassembly(), ArmISA::MemoryReg64::generateDisassembly(), ArmISA::DataXCondCompImmOp::generateDisassembly(), ArmISA::SveUnaryWideImmUnpredOp::generateDisassembly(), RegRegRegImmOp::generateDisassembly(), PowerISA::BranchNonPCRelCond::generateDisassembly(), ArmISA::MemoryRaw64::generateDisassembly(), ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), ArmISA::DataXCondCompRegOp::generateDisassembly(), ArmISA::MemoryEx64::generateDisassembly(), ArmISA::SveUnaryWideImmPredOp::generateDisassembly(), PowerISA::BranchRegCond::generateDisassembly(), ArmISA::MemoryLiteral64::generateDisassembly(), ArmISA::DataXCondSelOp::generateDisassembly(), ArmISA::SveBinImmUnpredConstrOp::generateDisassembly(), ArmISA::SveBinImmPredOp::generateDisassembly(), RegRegImmOp::generateDisassembly(), ArmISA::SveBinWideImmUnpredOp::generateDisassembly(), ArmISA::MicroIntImmOp::generateDisassembly(), ArmISA::SveBinDestrPredOp::generateDisassembly(), ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), ArmISA::MicroIntImmXOp::generateDisassembly(), ArmISA::SveBinConstrPredOp::generateDisassembly(), RegImmImmOp::generateDisassembly(), ArmISA::SveBinUnpredOp::generateDisassembly(), RegRegImmImmOp::generateDisassembly(), ArmISA::MicroIntRegXOp::generateDisassembly(), ArmISA::SveBinIdxUnpredOp::generateDisassembly(), ArmISA::PredMacroOp::generateDisassembly(), RegImmRegShiftOp::generateDisassembly(), ArmISA::SvePredLogicalOp::generateDisassembly(), ArmISA::SvePredBinPermOp::generateDisassembly(), ArmISA::MicroMemOp::generateDisassembly(), ArmISA::SveCmpOp::generateDisassembly(), ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::generateDisassembly(), ArmISA::MicroMemPairOp::generateDisassembly(), ArmISA::SveCmpImmOp::generateDisassembly(), ArmISA::SveTerPredOp::generateDisassembly(), ArmISA::SveTerImmUnpredOp::generateDisassembly(), ArmISA::SveReducOp::generateDisassembly(), ArmISA::SveOrdReducOp::generateDisassembly(), ArmISA::SvePtrueOp::generateDisassembly(), ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::generateDisassembly(), ArmISA::SveIntCmpOp::generateDisassembly(), ArmISA::SveIntCmpImmOp::generateDisassembly(), ArmISA::SveAdrOp::generateDisassembly(), ArmISA::SveElemCountOp::generateDisassembly(), ArmISA::SvePartBrkOp::generateDisassembly(), ArmISA::SvePartBrkPropOp::generateDisassembly(), ArmISA::SveSelectOp::generateDisassembly(), ArmISA::SveUnaryPredPredOp::generateDisassembly(), ArmISA::SveTblOp::generateDisassembly(), ArmISA::SveUnpackOp::generateDisassembly(), ArmISA::SvePredTestOp::generateDisassembly(), ArmISA::SvePredUnaryWImplicitSrcPredOp::generateDisassembly(), ArmISA::SveBinImmUnpredDestrOp::generateDisassembly(), ArmISA::SveBinImmIdxUnpredOp::generateDisassembly(), ArmISA::SveUnarySca2VecUnpredOp::generateDisassembly(), ArmISA::SveDotProdIdxOp::generateDisassembly(), ArmISA::SveDotProdOp::generateDisassembly(), ArmISA::SveComplexOp::generateDisassembly(), ArmISA::FpCondCompRegOp::generateDisassembly(), ArmISA::SveComplexIdxOp::generateDisassembly(), ArmISA::FpCondSelOp::generateDisassembly(), ArmISA::FpRegImmOp::generateDisassembly(), ArmISA::FpRegRegImmOp::generateDisassembly(), ArmISA::FpRegRegRegImmOp::generateDisassembly(), Terminal::listen(), BaseRemoteGDB::listen(), VncServer::listen(), TapListener::listen(), Trace::OstreamLogger::logMessage(), main(), Trace::NativeTrace::NativeTrace(), Stats::ScalarPrint::operator()(), Stats::VectorPrint::operator()(), Stats::DistPrint::operator()(), Net::operator<<(), Loader::operator<<(), sc_core::operator<<(), GenericISA::operator<<(), X86ISA::operator<<(), operator<<(), sc_gem5::VcdTraceScope::output(), sc_gem5::VcdTraceValFloat< T >::output(), sc_gem5::VcdTraceValFxval< T >::output(), Trace::TarmacTracerRecordV8::TraceInstEntryV8::print(), Throttle::print(), WriteQueueEntry::TargetList::print(), Trace::TarmacTracerRecord::TraceInstEntry::print(), Trace::TarmacTracerRecordV8::TraceRegEntryV8::print(), Logger::print(), Trace::TarmacTracerRecord::TraceRegEntry::print(), Trace::TarmacTracerRecordV8::TraceMemEntryV8::print(), MessageBuffer::print(), WriteQueueEntry::print(), Trace::TarmacTracerRecord::TraceMemEntry::print(), MSHR::TargetList::print(), MSHR::print(), CacheBlkPrintWrapper::print(), Packet::print(), ArmISA::ArmStaticInst::printCCReg(), ArmISA::ArmStaticInst::printDataInst(), ArmISA::ArmStaticInst::printExtendOperand(), ArmISA::ArmStaticInst::printFloatReg(), ArmISA::ArmStaticInst::printIntReg(), Packet::PrintReqState::printLabels(), X86ISA::X86StaticInst::printMem(), ArmISA::ArmStaticInst::printMemSymbol(), ArmISA::ArmStaticInst::printMiscReg(), X86ISA::X86StaticInst::printMnemonic(), SparcISA::SparcStaticInst::printMnemonic(), ArmISA::MemoryImm::printOffset(), ArmISA::MemoryReg::printOffset(), ArmISA::ArmStaticInst::printPFflags(), SparcISA::IntOp::printPseudoOps(), SparcISA::IntOpImm::printPseudoOps(), PowerISA::PowerStaticInst::printReg(), SparcISA::SparcStaticInst::printReg(), X86ISA::X86StaticInst::printReg(), X86ISA::X86StaticInst::printSegment(), ArmISA::ArmStaticInst::printTarget(), ArmISA::ArmStaticInst::printVecPredReg(), ArmISA::ArmStaticInst::printVecReg(), ArmISA::DumpStats::process(), Shader::regStats(), BaseCPU::regStats(), System::regStats(), sc_core::sc_report_compose_message(), ArmISA::ArmStaticInst::shift_carry_imm(), ArmISA::ArmStaticInst::shift_carry_rs(), ArmISA::ArmStaticInst::shift_rm_imm(), ArmISA::ArmStaticInst::shift_rm_rs(), ArmISA::ArmStaticInst::shiftReg64(), sc_core::sc_vector_base::size(), ArmISA::Memory64::startDisassembly(), TEST(), sc_gem5::VcdTraceFile::trace(), BaseCPU::traceFunctionsInternal(), Trace::ExeTracerRecord::traceInst(), and sc_gem5::VcdTraceFile::~VcdTraceFile().

ccprintf() [2/4]

template<typename T , typename ... Args>

void ccprintf	(	cp::Print &	print,
		const T &	value,
		const Args &...	args
	)

Definition at line 134 of file cprintf.hh.

References cp::Print::add_arg(), and ccprintf().

ccprintf() [3/4]

template<typename ... Args>

void ccprintf	(	std::ostream &	stream,
		const char *	format,
		const Args &...	args
	)

Definition at line 143 of file cprintf.hh.

References ccprintf(), and ArmISA::format.

ccprintf() [4/4]

template<typename ... Args>

void ccprintf	(	std::ostream &	stream,
		const std::string &	format,
		const Args &...	args
	)

Definition at line 171 of file cprintf.hh.

References ccprintf(), and ArmISA::format.

cprintf() [1/2]

template<typename ... Args>

void cprintf	(	const char *	format,
		const Args &...	args
	)

Definition at line 152 of file cprintf.hh.

References ccprintf(), and ArmISA::format.

Referenced by Stats::Info::baseCheck(), Debug::breakpoint(), UnitTest::checkVal(), EventQueue::debugVerify(), sc_core::sc_report_handler::default_handler(), ActivityRecorder::dump(), StoreSet::dump(), DependencyGraph< DynInstPtr >::dump(), PCEventQueue::dump(), BPredUnit::dump(), Event::dump(), BaseDynInst< Impl >::dump(), EventQueue::dump(), Checker< O3CPUImpl >::dumpAndExit(), dumpDebugFlags(), DefaultRename< Impl >::dumpHistory(), LSQUnit< Impl >::dumpInsts(), InstructionQueue< Impl >::dumpInsts(), FullO3CPU< O3CPUImpl >::dumpInsts(), Checker< O3CPUImpl >::dumpInsts(), MemDepUnit< MemDepPred, Impl >::dumpLists(), InstructionQueue< Impl >::dumpLists(), fixClockFrequency(), EmbeddedPyBind::init(), StatTest::init(), main(), UnitTest::printResults(), CPUProgressEvent::process(), and InstructionQueue< Impl >::~InstructionQueue().

cprintf() [2/2]

template<typename ... Args>

void cprintf	(	const std::string &	format,
		const Args &...	args
	)

Definition at line 177 of file cprintf.hh.

References ccprintf(), and ArmISA::format.

csprintf() [1/2]

template<typename ... Args>

std::string csprintf	(	const char *	format,
		const Args &...	args
	)

Definition at line 158 of file cprintf.hh.

References ccprintf(), and ArmISA::format.

Referenced by SMMUv3DeviceInterface::atsRecvAtomic(), SMMUv3DeviceInterface::atsRecvTimingReq(), Stats::Text::beginGroup(), CxxConfigManager::bindObjectPorts(), CxxConfigManager::bindPort(), CxxConfigManager::bindRequestPort(), BaseRemoteGDB::cmd_signal(), CoherentXBar::CoherentXBar(), MemChecker::completeRead(), GenericTimer::CoreTimers::CoreTimers(), Linux::cpuOnline(), csprintf(), ArmISA::PMU::CounterState::debugCounter(), Pl111::dmaDone(), sc_core::sc_in_resolved::end_of_elaboration(), sc_core::sc_inout_resolved::end_of_elaboration(), sc_gem5::Module::endOfElaboration(), Linux::etcPasswd(), EtherSwitch::EtherSwitch(), CxxConfigManager::findObject(), CxxConfigManager::findObjectParams(), CxxConfigManager::findObjectType(), Trace::TarmacTracerRecordV8::TraceRegEntryV8::formatReg(), RiscvISA::MemFenceMicro::generateDisassembly(), PowerISA::MemOp::generateDisassembly(), DecoderFaultInst::generateDisassembly(), RiscvISA::Unknown::generateDisassembly(), SparcISA::FailUnimplemented::generateDisassembly(), FailUnimplemented::generateDisassembly(), UnknownOp64::generateDisassembly(), SparcISA::WarnUnimplemented::generateDisassembly(), WarnUnimplemented::generateDisassembly(), MiscRegImplDefined64::generateDisassembly(), UnknownOp::generateDisassembly(), McrMrcMiscInst::generateDisassembly(), McrMrcImplDefined::generateDisassembly(), getEventQueue(), CxxConfigManager::getObject(), FastModel::GIC::getPort(), X86ISA::I8042::I8042(), X86ISA::I82094AA::I82094AA(), X86ISA::I8254::I8254(), X86ISA::I8259::I8259(), MemDepUnit< MemDepPred, Impl >::init(), LSQUnit< Impl >::init(), sc_gem5::VcdTraceFile::initialize(), Event::instanceString(), ArmISA::ArmFault::invoke(), ArmISA::ArmFault::invoke64(), SMMUTranslationProcess::issuePrefetch(), MachineIDToString(), Throttle::name(), PerfectSwitch::name(), CopyEngine::CopyEngineChannel::name(), PciHost::DeviceInterface::name(), System::Threads::Thread::name(), SimpleThread::name(), Event::name(), DRAMInterface::Rank::name(), NoncoherentXBar::NoncoherentXBar(), operator<<(), sc_gem5::VcdTraceScope::output(), Trace::TarmacTracerRecordV8::TraceInstEntryV8::print(), Trace::TarmacTracerRecord::TraceInstEntry::print(), FALRUBlk::print(), ReplaceableEntry::print(), CompressionBlk::print(), SectorSubBlk::print(), VecPredRegT< VecElem, NumElems, Packed, Const >::print(), BaseTags::print(), VecRegT< VecElem, NumElems, Const >::print(), ArmISA::TlbEntry::print(), VecPredRegContainer< TheISA::VecPredRegSizeBits, TheISA::VecPredRegHasPackedRepr >::print(), CacheBlk::print(), VecRegContainer< TheISA::VecRegSizeBytes >::print(), Compressor::DictionaryCompressor< T >::Pattern::print(), Linux::procMeminfo(), Serializable::ScopedCheckpointSection::pushName(), HDLcd::pxlFrameDone(), SMMUv3DeviceInterface::recvAtomic(), SMMUv3DeviceInterface::recvTimingReq(), Profiler::regStats(), Throttle::regStats(), ScoreboardCheckStage::regStats(), GarnetNetwork::regStats(), ScheduleStage::regStats(), SMMUv3::regStats(), WalkCache::regStats(), ComputeUnit::regStats(), TrafficGen::resolveFile(), RubyPort::RubyPort(), FastModel::ScxEvsCortexA76< Types >::ScxEvsCortexA76(), ArmSemihosting::semiExit(), FlashDevice::serialize(), MipsISA::TLB::serialize(), RiscvISA::TLB::serialize(), ArmISA::PMU::serialize(), EtherLink::Link::serialize(), Gicv3::serialize(), Iob::serialize(), X86ISA::TLB::serialize(), EmulationPageTable::serialize(), PowerISA::TLB::serialize(), EtherSwitch::Interface::PortFifo::serialize(), CopyEngine::serialize(), Loader::SymbolTable::serialize(), MemState::serialize(), SparcISA::TLB::serialize(), CpuLocalTimer::serialize(), VGic::serialize(), PacketFifo::serialize(), PciDevice::serialize(), ArmSemihosting::serialize(), PhysicalMemory::serialize(), GenericTimer::serialize(), IGbE::DescCache< iGbReg::RxDesc >::serialize(), Sinic::Device::serialize(), BaseCPU::serialize(), DistIface::RecvScheduler::serialize(), GicV2::serialize(), VirtIODeviceBase::serialize(), System::serialize(), CheckpointIn::setDir(), CxxConfigManager::setParam(), CxxConfigManager::setParamVector(), SimpleCache::SimpleCache(), Stats::Text::statName(), Stats::ScalarProxy< Stat >::str(), Stats::ConstVectorNode< T >::str(), Stats::BinaryNode< Op >::str(), Stats::SumNode< Op >::str(), AddrRange::to_string(), BaseCPU::traceFunctionsInternal(), BaseRemoteGDB::trap(), FlashDevice::unserialize(), MipsISA::TLB::unserialize(), RiscvISA::TLB::unserialize(), ArmISA::PMU::unserialize(), EtherLink::Link::unserialize(), Gicv3::unserialize(), Iob::unserialize(), X86ISA::TLB::unserialize(), EmulationPageTable::unserialize(), PowerISA::TLB::unserialize(), EtherSwitch::Interface::PortFifo::unserialize(), CopyEngine::unserialize(), Loader::SymbolTable::unserialize(), SparcISA::TLB::unserialize(), CpuLocalTimer::unserialize(), VGic::unserialize(), MemState::unserialize(), PacketFifo::unserialize(), PciDevice::unserialize(), ArmSemihosting::unserialize(), PhysicalMemory::unserialize(), GenericTimer::unserialize(), IGbE::DescCache< iGbReg::RxDesc >::unserialize(), Sinic::Device::unserialize(), BaseCPU::unserialize(), DistIface::RecvScheduler::unserialize(), GicV2::unserialize(), VirtIODeviceBase::unserialize(), System::unserialize(), sc_core::wait(), and X86ISA::Cmos::X86RTC::X86RTC().

csprintf() [2/2]

template<typename ... Args>

std::string csprintf	(	const std::string &	format,
		const Args &...	args
	)

Definition at line 183 of file cprintf.hh.

References csprintf(), and ArmISA::format.