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32 #ifndef __SIMPLE_LT_INITIATOR1_H__
33 #define __SIMPLE_LT_INITIATOR1_H__
56 unsigned int nrOfTransactions = 0x5,
57 unsigned int baseAddress = 0x0) :
87 trans.set_data_ptr(
reinterpret_cast<unsigned char*
>(&
mData));
88 trans.set_data_length(4);
89 trans.set_streaming_width(4);
90 trans.set_dmi_allowed(
false);
100 std::cout <<
name() <<
": Send write request: A = 0x"
101 << std::hex << (
unsigned int)trans.get_address()
102 <<
", D = 0x" <<
mData << std::dec
106 std::cout <<
name() <<
": Send read request: A = 0x"
107 << std::hex << (
unsigned int)trans.get_address() << std::dec
115 std::cout <<
name() <<
": Received error response @ "
119 std::cout <<
name() <<
": Received ok response";
121 std::cout <<
": D = 0x" << std::hex <<
mData << std::dec;
@ TLM_INCOMPLETE_RESPONSE
unsigned int mTransactionCount
bool initTransaction(transaction_type &trans)
const sc_time SC_ZERO_TIME
tlm::tlm_sync_enum sync_enum_type
initiator_socket_type socket
void logStartTransation(transaction_type &trans)
unsigned int mNrOfTransactions
tlm::tlm_initiator_socket< 32 > initiator_socket_type
tlm::tlm_fw_transport_if fw_interface_type
tlm::tlm_bw_transport_if bw_interface_type
SC_HAS_PROCESS(SimpleLTInitiator1)
tlm::tlm_sync_enum nb_transport_bw(transaction_type &, phase_type &, sc_core::sc_time &)
sc_core::sc_event mEndEvent
SimpleLTInitiator1(sc_core::sc_module_name name, unsigned int nrOfTransactions=0x5, unsigned int baseAddress=0x0)
void invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range)
const char * name() const
tlm::tlm_generic_payload transaction_type
tlm::tlm_phase phase_type
void logEndTransaction(transaction_type &trans)
const sc_time & sc_time_stamp()
unsigned int mBaseAddress
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