gem5  v20.1.0.0
SimpleLTTarget2.h
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19 
20 #ifndef __SIMPLE_LT_TARGET2_H__
21 #define __SIMPLE_LT_TARGET2_H__
22 
23 #include "tlm.h"
24 #include "tlm_utils/passthrough_target_socket.h"
25 #include <cassert>
26 #include <vector>
27 
29 {
30 public:
32  typedef tlm::tlm_phase phase_type;
35 
36 
37 public:
39 
40 public:
43  socket("socket")
44  {
45  // register nb_transport method
49 
50  // TODO: we don't register the transport_dbg callback here, so we
51  // can test if something bad happens
52  // REGISTER_DEBUGTRANSPORT(socket, transport_dbg, 0);
53  }
54 
57  {
58  sc_dt::uint64 address = trans.get_address();
59  assert(address < 400);
60 
61  unsigned int& data = *reinterpret_cast<unsigned int*>(trans.get_data_ptr());
62  if (trans.get_command() == tlm::TLM_WRITE_COMMAND) {
63  std::cout << name() << ": Received write request: A = 0x"
64  << std::hex << (unsigned int)address
65  << ", D = 0x" << data << std::dec
66  << " @ " << sc_core::sc_time_stamp() << std::endl;
67 
68  *reinterpret_cast<unsigned int*>(&mMem[address]) = data;
70 
71  } else {
72  std::cout << name() << ": Received read request: A = 0x"
73  << std::hex << (unsigned int)address << std::dec
74  << " @ " << sc_core::sc_time_stamp() << std::endl;
75 
76  data = *reinterpret_cast<unsigned int*>(&mMem[address]);
78  }
79 
81 
82  trans.set_dmi_allowed(true);
83  }
84 
86  phase_type& phase,
88  {
89  assert(phase == tlm::BEGIN_REQ);
90 
91  // Never blocks, so call b_transport implementation
92  myBTransport(trans, t);
93  // LT target
94  // - always return TLM_COMPLETED
95  // - not necessary to update phase (if TLM_COMPLETED is returned)
96  return tlm::TLM_COMPLETED;
97  }
98 
99  unsigned int transport_dbg(transaction_type& r)
100  {
101  if (r.get_address() >= 400) return 0;
102 
103  unsigned int tmp = (int)r.get_address();
104  unsigned int num_bytes;
105  if (tmp + r.get_data_length() >= 400) {
106  num_bytes = 400 - tmp;
107 
108  } else {
109  num_bytes = r.get_data_length();
110  }
111  if (r.is_read()) {
112  for (unsigned int i = 0; i < num_bytes; ++i) {
113  r.get_data_ptr()[i] = mMem[i + tmp];
114  }
115 
116  } else {
117  for (unsigned int i = 0; i < num_bytes; ++i) {
118  mMem[i + tmp] = r.get_data_ptr()[i];
119  }
120  }
121  return num_bytes;
122  }
123 
124  bool myGetDMIPtr(transaction_type& trans,
125  tlm::tlm_dmi& dmi_data)
126  {
127  sc_dt::uint64 address = trans.get_address();
128  if (address < 400) {
129  dmi_data.allow_read_write();
130  dmi_data.set_start_address(0x0);
131  dmi_data.set_end_address(399);
132  dmi_data.set_dmi_ptr(mMem);
135  return true;
136 
137  } else {
138  // should not happen
139  dmi_data.set_start_address(address);
140  dmi_data.set_end_address(address);
141  return false;
142 
143  }
144  }
145 private:
146  unsigned char mMem[400];
147 };
148 
149 #endif
SimpleLTTarget2::mMem
unsigned char mMem[400]
Definition: SimpleLTTarget2.h:163
data
const char data[]
Definition: circlebuf.test.cc:42
sc_core::sc_module
Definition: sc_module.hh:97
tlm::tlm_phase
Definition: phase.hh:47
tlm::tlm_dmi::allow_read_write
void allow_read_write()
Definition: dmi.hh:124
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
tlm::TLM_COMPLETED
@ TLM_COMPLETED
Definition: fw_bw_ifs.hh:65
tlm::tlm_dmi
Definition: dmi.hh:46
tlm::TLM_WRITE_COMMAND
@ TLM_WRITE_COMMAND
Definition: gp.hh:102
SimpleLTTarget2::myBTransport
void myBTransport(transaction_type &trans, sc_core::sc_time &t)
Definition: SimpleLTTarget2.h:72
tlm::TLM_OK_RESPONSE
@ TLM_OK_RESPONSE
Definition: gp.hh:108
tlm_utils::passthrough_target_socket< SimpleLTTarget2 >
tlm::tlm_generic_payload::set_dmi_allowed
void set_dmi_allowed(bool dmi_allowed)
Definition: gp.hh:256
SimpleLTTarget2::socket
target_socket_type socket
Definition: SimpleLTTarget2.h:55
sc_core::SC_NS
@ SC_NS
Definition: sc_time.hh:43
tlm::tlm_dmi::set_end_address
void set_end_address(sc_dt::uint64 addr)
Definition: dmi.hh:117
tlm::tlm_generic_payload::get_command
tlm_command get_command() const
Definition: gp.hh:197
SimpleLTTarget2::myGetDMIPtr
bool myGetDMIPtr(transaction_type &trans, tlm::tlm_dmi &dmi_data)
Definition: SimpleLTTarget2.h:141
SimpleLTTarget2::myNBTransport
sync_enum_type myNBTransport(transaction_type &trans, phase_type &phase, sc_core::sc_time &t)
Definition: SimpleLTTarget2.h:102
SimpleLTTarget2::transaction_type
tlm::tlm_generic_payload transaction_type
Definition: SimpleLTTarget2.h:48
SimpleLTTarget2
Definition: SimpleLTTarget2.h:28
sc_dt::uint64
uint64_t uint64
Definition: sc_nbdefs.hh:206
tlm::tlm_dmi::set_read_latency
void set_read_latency(sc_core::sc_time t)
Definition: dmi.hh:118
MipsISA::r
r
Definition: pra_constants.hh:95
sc_core::sc_time
Definition: sc_time.hh:49
tlm_utils::passthrough_target_socket_b::register_b_transport
void register_b_transport(MODULE *mod, void(MODULE::*cb)(transaction_type &, sc_core::sc_time &))
Definition: passthrough_target_socket.h:105
SimpleLTTarget2::transport_dbg
unsigned int transport_dbg(transaction_type &r)
Definition: SimpleLTTarget2.h:116
SimpleLTTarget2::sync_enum_type
tlm::tlm_sync_enum sync_enum_type
Definition: SimpleLTTarget2.h:50
sc_core::sc_module_name
Definition: sc_module_name.hh:41
tlm_utils::passthrough_target_socket_b::register_get_direct_mem_ptr
void register_get_direct_mem_ptr(MODULE *mod, bool(MODULE::*cb)(transaction_type &, tlm::tlm_dmi &))
Definition: passthrough_target_socket.h:119
tlm::BEGIN_REQ
@ BEGIN_REQ
Definition: phase.hh:41
tlm::tlm_dmi::set_write_latency
void set_write_latency(sc_core::sc_time t)
Definition: dmi.hh:119
tlm::tlm_generic_payload
Definition: gp.hh:133
ArmISA::t
Bitfield< 5 > t
Definition: miscregs_types.hh:67
SimpleLTTarget2::target_socket_type
tlm_utils::passthrough_target_socket< SimpleLTTarget2 > target_socket_type
Definition: SimpleLTTarget2.h:51
sc_core::sc_object::name
const char * name() const
Definition: sc_object.cc:44
SimpleLTTarget2::SimpleLTTarget2
SimpleLTTarget2(sc_core::sc_module_name name)
Definition: SimpleLTTarget2.h:58
tlm::tlm_sync_enum
tlm_sync_enum
Definition: fw_bw_ifs.hh:48
tlm::tlm_dmi::set_dmi_ptr
void set_dmi_ptr(unsigned char *p)
Definition: dmi.hh:115
SimpleLTTarget2::phase_type
tlm::tlm_phase phase_type
Definition: SimpleLTTarget2.h:49
tlm::tlm_dmi::set_start_address
void set_start_address(sc_dt::uint64 addr)
Definition: dmi.hh:116
tlm_utils::passthrough_target_socket_b::register_nb_transport_fw
void register_nb_transport_fw(MODULE *mod, sync_enum_type(MODULE::*cb)(transaction_type &, phase_type &, sc_core::sc_time &))
Definition: passthrough_target_socket.h:97
tlm::tlm_generic_payload::get_address
sc_dt::uint64 get_address() const
Definition: gp.hh:201
sc_core::sc_time_stamp
const sc_time & sc_time_stamp()
Definition: sc_main.cc:128
tlm::tlm_generic_payload::get_data_ptr
unsigned char * get_data_ptr() const
Definition: gp.hh:205
tlm::tlm_generic_payload::set_response_status
void set_response_status(const tlm_response_status response_status)
Definition: gp.hh:221

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