gem5
v20.1.0.0
systemc
tests
systemc
misc
semantic
2.3
T_2_3_2_1
T_2_3_1.h
Go to the documentation of this file.
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/*****************************************************************************
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing
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permissions and limitations under the License.
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*****************************************************************************/
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/*****************************************************************************
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T_2_3_1.h --
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Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
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*****************************************************************************/
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/*****************************************************************************
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MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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changes you are making here.
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Name, Affiliation, Date:
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Description of Modification:
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*****************************************************************************/
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SC_MODULE
( MYNAME )
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{
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SC_HAS_PROCESS
( MYNAME );
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sc_in_clk
clk;
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const
signal_vector&
x
;
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const
signal_vector& y;
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signal_vector&
z
;
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MYNAME( sc_module_name NAME,
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sc_clock& CLK,
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const
signal_vector&
X
,
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const
signal_vector& Y,
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signal_vector& Z )
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:
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x
(
X
), y(Y),
z
(Z)
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{
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clk(CLK);
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SC_CTHREAD
( entry, clk.pos() );
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}
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void
entry();
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};
SC_MODULE
SC_MODULE(MYNAME)
Definition:
T_2_3_1.h:38
X86ISA::X
Bitfield< 15, 0 > X
Definition:
int.hh:53
ArmISA::z
Bitfield< 11 > z
Definition:
miscregs_types.hh:370
RiscvISA::x
Bitfield< 3 > x
Definition:
pagetable.hh:69
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition:
sc_clock.hh:116
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition:
sc_module.hh:297
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition:
sc_module.hh:319
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