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38 #ifndef __ARCH_X86_INTREGS_HH__
39 #define __ARCH_X86_INTREGS_HH__
50 SignedBitfield<63,0>
SR;
52 SignedBitfield<31,0>
SE;
54 SignedBitfield<15,0>
SX;
56 SignedBitfield<15,8>
SH;
58 SignedBitfield<7, 0>
SL;
64 INTREG_EAX = INTREG_RAX,
65 INTREG_AX = INTREG_RAX,
66 INTREG_AL = INTREG_RAX,
69 INTREG_ECX = INTREG_RCX,
70 INTREG_CX = INTREG_RCX,
71 INTREG_CL = INTREG_RCX,
74 INTREG_EDX = INTREG_RDX,
75 INTREG_DX = INTREG_RDX,
76 INTREG_DL = INTREG_RDX,
79 INTREG_EBX = INTREG_RBX,
80 INTREG_BX = INTREG_RBX,
81 INTREG_BL = INTREG_RBX,
84 INTREG_ESP = INTREG_RSP,
86 INTREG_SPL = INTREG_RSP,
87 INTREG_AH = INTREG_RSP,
90 INTREG_EBP = INTREG_RBP,
91 INTREG_BP = INTREG_RBP,
92 INTREG_BPL = INTREG_RBP,
93 INTREG_CH = INTREG_RBP,
96 INTREG_ESI = INTREG_RSI,
97 INTREG_SI = INTREG_RSI,
98 INTREG_SIL = INTREG_RSI,
99 INTREG_DH = INTREG_RSI,
102 INTREG_EDI = INTREG_RDI,
103 INTREG_DI = INTREG_RDI,
104 INTREG_DIL = INTREG_RDI,
105 INTREG_BH = INTREG_RDI,
168 if ((
index & 0x1C) == 4 && foldBit)
174 #endif // __ARCH_X86_INTREGS_HH__
static const IntRegIndex IntFoldBit
static IntRegIndex INTREG_IMPLICIT(int index)
BitUnion64(VAddr) Bitfield< 20
SignedBitfield< 31, 0 > SE
SignedBitfield< 15, 8 > SH
static IntRegIndex INTREG_MICRO(int index)
static IntRegIndex INTREG_FOLDED(int index, int foldBit)
This is exposed globally, independent of the ISA.
SignedBitfield< 7, 0 > SL
EndBitUnion(TriggerIntMessage) namespace DeliveryMode
SignedBitfield< 15, 0 > SX
const int NumMicroIntRegs
SignedBitfield< 63, 0 > SR
Generated on Wed Sep 30 2020 14:02:07 for gem5 by doxygen 1.8.17