gem5  v20.1.0.0
int.hh
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37 
38 #ifndef __ARCH_X86_INTREGS_HH__
39 #define __ARCH_X86_INTREGS_HH__
40 
41 #include "arch/x86/x86_traits.hh"
42 #include "base/bitunion.hh"
43 #include "base/logging.hh"
44 #include "sim/core.hh"
45 
46 namespace X86ISA
47 {
48  BitUnion64(X86IntReg)
49  Bitfield<63,0> R;
50  SignedBitfield<63,0> SR;
51  Bitfield<31,0> E;
52  SignedBitfield<31,0> SE;
53  Bitfield<15,0> X;
54  SignedBitfield<15,0> SX;
55  Bitfield<15,8> H;
56  SignedBitfield<15,8> SH;
57  Bitfield<7, 0> L;
58  SignedBitfield<7, 0> SL;
59  EndBitUnion(X86IntReg)
60 
61  enum IntRegIndex
62  {
63  INTREG_RAX,
64  INTREG_EAX = INTREG_RAX,
65  INTREG_AX = INTREG_RAX,
66  INTREG_AL = INTREG_RAX,
67 
68  INTREG_RCX,
69  INTREG_ECX = INTREG_RCX,
70  INTREG_CX = INTREG_RCX,
71  INTREG_CL = INTREG_RCX,
72 
73  INTREG_RDX,
74  INTREG_EDX = INTREG_RDX,
75  INTREG_DX = INTREG_RDX,
76  INTREG_DL = INTREG_RDX,
77 
78  INTREG_RBX,
79  INTREG_EBX = INTREG_RBX,
80  INTREG_BX = INTREG_RBX,
81  INTREG_BL = INTREG_RBX,
82 
83  INTREG_RSP,
84  INTREG_ESP = INTREG_RSP,
85  INTREG_SP = INTREG_RSP,
86  INTREG_SPL = INTREG_RSP,
87  INTREG_AH = INTREG_RSP,
88 
89  INTREG_RBP,
90  INTREG_EBP = INTREG_RBP,
91  INTREG_BP = INTREG_RBP,
92  INTREG_BPL = INTREG_RBP,
93  INTREG_CH = INTREG_RBP,
94 
95  INTREG_RSI,
96  INTREG_ESI = INTREG_RSI,
97  INTREG_SI = INTREG_RSI,
98  INTREG_SIL = INTREG_RSI,
99  INTREG_DH = INTREG_RSI,
100 
101  INTREG_RDI,
102  INTREG_EDI = INTREG_RDI,
103  INTREG_DI = INTREG_RDI,
104  INTREG_DIL = INTREG_RDI,
105  INTREG_BH = INTREG_RDI,
106 
107  INTREG_R8,
108  INTREG_R8D = INTREG_R8,
109  INTREG_R8W = INTREG_R8,
110  INTREG_R8B = INTREG_R8,
111 
112  INTREG_R9,
113  INTREG_R9D = INTREG_R9,
114  INTREG_R9W = INTREG_R9,
115  INTREG_R9B = INTREG_R9,
116 
117  INTREG_R10,
118  INTREG_R10D = INTREG_R10,
119  INTREG_R10W = INTREG_R10,
120  INTREG_R10B = INTREG_R10,
121 
122  INTREG_R11,
123  INTREG_R11D = INTREG_R11,
124  INTREG_R11W = INTREG_R11,
125  INTREG_R11B = INTREG_R11,
126 
127  INTREG_R12,
128  INTREG_R12D = INTREG_R12,
129  INTREG_R12W = INTREG_R12,
130  INTREG_R12B = INTREG_R12,
131 
132  INTREG_R13,
133  INTREG_R13D = INTREG_R13,
134  INTREG_R13W = INTREG_R13,
135  INTREG_R13B = INTREG_R13,
136 
137  INTREG_R14,
138  INTREG_R14D = INTREG_R14,
139  INTREG_R14W = INTREG_R14,
140  INTREG_R14B = INTREG_R14,
141 
142  INTREG_R15,
143  INTREG_R15D = INTREG_R15,
144  INTREG_R15W = INTREG_R15,
145  INTREG_R15B = INTREG_R15,
146 
148  };
149 
150  // This needs to be large enough to miss all the other bits of an index.
151  static const IntRegIndex IntFoldBit = (IntRegIndex)(1 << 6);
152 
153  inline static IntRegIndex
155  {
156  return (IntRegIndex)(NUM_INTREGS + index);
157  }
158 
159  inline static IntRegIndex
161  {
163  }
164 
165  inline static IntRegIndex
166  INTREG_FOLDED(int index, int foldBit)
167  {
168  if ((index & 0x1C) == 4 && foldBit)
169  index = (index - 4) | foldBit;
170  return (IntRegIndex)index;
171  }
172 }
173 
174 #endif // __ARCH_X86_INTREGS_HH__
X86ISA::IntFoldBit
static const IntRegIndex IntFoldBit
Definition: int.hh:151
x86_traits.hh
X86ISA::L
Bitfield< 7, 0 > L
Definition: int.hh:57
ArmISA::INTREG_R8
@ INTREG_R8
Definition: intregs.hh:62
ArmISA::INTREG_R9
@ INTREG_R9
Definition: intregs.hh:63
X86ISA::INTREG_IMPLICIT
static IntRegIndex INTREG_IMPLICIT(int index)
Definition: int.hh:160
X86ISA::BitUnion64
BitUnion64(VAddr) Bitfield< 20
ArmISA::IntRegIndex
IntRegIndex
Definition: intregs.hh:51
X86ISA::E
Bitfield< 31, 0 > E
Definition: int.hh:51
X86ISA::X
Bitfield< 15, 0 > X
Definition: int.hh:53
ArmISA::INTREG_R13
@ INTREG_R13
Definition: intregs.hh:67
ArmISA::INTREG_SP
@ INTREG_SP
Definition: intregs.hh:68
ArmISA::INTREG_R10
@ INTREG_R10
Definition: intregs.hh:64
X86ISA::SE
SignedBitfield< 31, 0 > SE
Definition: int.hh:52
X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:93
X86ISA::SH
SignedBitfield< 15, 8 > SH
Definition: int.hh:56
ArmISA::INTREG_R12
@ INTREG_R12
Definition: intregs.hh:66
bitunion.hh
ArmISA::INTREG_R14
@ INTREG_R14
Definition: intregs.hh:69
X86ISA::INTREG_MICRO
static IntRegIndex INTREG_MICRO(int index)
Definition: int.hh:154
ArmISA::INTREG_R15
@ INTREG_R15
Definition: intregs.hh:71
X86ISA::INTREG_FOLDED
static IntRegIndex INTREG_FOLDED(int index, int foldBit)
Definition: int.hh:166
core.hh
X86ISA
This is exposed globally, independent of the ISA.
Definition: acpi.hh:55
X86ISA::R
R
Definition: int.hh:49
X86ISA::SL
SignedBitfield< 7, 0 > SL
Definition: int.hh:58
ArmISA::NUM_INTREGS
@ NUM_INTREGS
Definition: intregs.hh:123
X86ISA::EndBitUnion
EndBitUnion(TriggerIntMessage) namespace DeliveryMode
Definition: intmessage.hh:49
logging.hh
X86ISA::SX
SignedBitfield< 15, 0 > SX
Definition: int.hh:54
X86ISA::H
Bitfield< 15, 8 > H
Definition: int.hh:55
ArmISA::INTREG_R11
@ INTREG_R11
Definition: intregs.hh:65
X86ISA::NumMicroIntRegs
const int NumMicroIntRegs
Definition: x86_traits.hh:47
X86ISA::SR
SignedBitfield< 63, 0 > SR
Definition: int.hh:50

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