gem5  v20.1.0.0
gpu_static_inst.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * For use for simulation and test purposes only
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright notice,
11  * this list of conditions and the following disclaimer.
12  *
13  * 2. Redistributions in binary form must reproduce the above copyright notice,
14  * this list of conditions and the following disclaimer in the documentation
15  * and/or other materials provided with the distribution.
16  *
17  * 3. Neither the name of the copyright holder nor the names of its
18  * contributors may be used to endorse or promote products derived from this
19  * software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  * POSSIBILITY OF SUCH DAMAGE.
32  *
33  * Authors: Anthony Gutierrez
34  */
35 
36 #ifndef __ARCH_GCN3_INSTS_GPU_STATIC_INST_HH__
37 #define __ARCH_GCN3_INSTS_GPU_STATIC_INST_HH__
38 
39 #include "arch/gcn3/operand.hh"
40 #include "arch/gcn3/registers.hh"
44 #include "gpu-compute/wavefront.hh"
45 
46 namespace Gcn3ISA
47 {
49  {
50  public:
51  GCN3GPUStaticInst(const std::string &opcode);
53 
54  void generateDisassembly() override { disassembly = _opcode; }
55 
56  bool
57  isFlatScratchRegister(int opIdx) override
58  {
59  return isFlatScratchReg(opIdx);
60  }
61 
62  bool
63  isExecMaskRegister(int opIdx) override
64  {
65  return isExecMask(opIdx);
66  }
67 
68  bool isScalarRegister(int opIdx) override { return false; }
69  bool isVectorRegister(int opIdx) override { return false; }
70  bool isSrcOperand(int opIdx) override { return false; }
71  bool isDstOperand(int opIdx) override { return false; }
72  int getOperandSize(int opIdx) override { return 0; }
73 
74  int
75  getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override
76  {
77  return 0;
78  }
79 
87  int coalescerTokenCount() const override { return 1; }
88  ScalarRegU32 srcLiteral() const override { return _srcLiteral; }
89 
90  protected:
91  void panicUnimplemented() const;
92 
99  }; // class GCN3GPUStaticInst
100 
101 } // namespace Gcn3ISA
102 #endif //__ARCH_GCN3_INSTS_GPU_STATIC_INST_HH__
Gcn3ISA::GCN3GPUStaticInst::panicUnimplemented
void panicUnimplemented() const
Definition: gpu_static_inst.cc:55
Gcn3ISA::isFlatScratchReg
bool isFlatScratchReg(int opIdx)
Definition: registers.cc:211
Gcn3ISA::GCN3GPUStaticInst::isDstOperand
bool isDstOperand(int opIdx) override
Definition: gpu_static_inst.hh:71
gpu_static_inst.hh
Gcn3ISA::GCN3GPUStaticInst::getRegisterIndex
int getRegisterIndex(int opIdx, GPUDynInstPtr gpuDynInst) override
Definition: gpu_static_inst.hh:75
Gcn3ISA::GCN3GPUStaticInst::isVectorRegister
bool isVectorRegister(int opIdx) override
Definition: gpu_static_inst.hh:69
registers.hh
Gcn3ISA::isExecMask
bool isExecMask(int opIdx)
Definition: registers.cc:199
Gcn3ISA::GCN3GPUStaticInst::isSrcOperand
bool isSrcOperand(int opIdx) override
Definition: gpu_static_inst.hh:70
wavefront.hh
GPUStaticInst::_opcode
const std::string _opcode
Definition: gpu_static_inst.hh:260
GPUStaticInst::disassembly
std::string disassembly
Definition: gpu_static_inst.hh:261
GPUStaticInst::opcode
const std::string & opcode() const
Definition: gpu_static_inst.hh:257
vector_register_file.hh
Gcn3ISA::GCN3GPUStaticInst::isFlatScratchRegister
bool isFlatScratchRegister(int opIdx) override
Definition: gpu_static_inst.hh:57
Gcn3ISA
classes that represnt vector/scalar operands in GCN3 ISA.
Definition: decoder.cc:44
Gcn3ISA::GCN3GPUStaticInst::isExecMaskRegister
bool isExecMaskRegister(int opIdx) override
Definition: gpu_static_inst.hh:63
Gcn3ISA::GCN3GPUStaticInst::GCN3GPUStaticInst
GCN3GPUStaticInst(const std::string &opcode)
Definition: gpu_static_inst.cc:45
scalar_register_file.hh
Gcn3ISA::GCN3GPUStaticInst::~GCN3GPUStaticInst
~GCN3GPUStaticInst()
Definition: gpu_static_inst.cc:50
GPUStaticInst
Definition: gpu_static_inst.hh:58
Gcn3ISA::GCN3GPUStaticInst::getOperandSize
int getOperandSize(int opIdx) override
Definition: gpu_static_inst.hh:72
Gcn3ISA::GCN3GPUStaticInst::srcLiteral
ScalarRegU32 srcLiteral() const override
Definition: gpu_static_inst.hh:88
Gcn3ISA::GCN3GPUStaticInst::coalescerTokenCount
int coalescerTokenCount() const override
Return the number of tokens needed by the coalescer.
Definition: gpu_static_inst.hh:87
Gcn3ISA::GCN3GPUStaticInst::isScalarRegister
bool isScalarRegister(int opIdx) override
Definition: gpu_static_inst.hh:68
Gcn3ISA::GCN3GPUStaticInst::generateDisassembly
void generateDisassembly() override
Definition: gpu_static_inst.hh:54
operand.hh
Gcn3ISA::GCN3GPUStaticInst::_srcLiteral
ScalarRegU32 _srcLiteral
if the instruction has a src literal - an immediate value that is part of the instruction stream - we...
Definition: gpu_static_inst.hh:98
GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:48
Gcn3ISA::ScalarRegU32
uint32_t ScalarRegU32
Definition: registers.hh:154
Gcn3ISA::GCN3GPUStaticInst
Definition: gpu_static_inst.hh:48

Generated on Wed Sep 30 2020 14:02:01 for gem5 by doxygen 1.8.17