gem5  v20.1.0.0
isa.cc
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27 
29 
30 #include "arch/arm/miscregs.hh"
31 #include "cpu/thread_context.hh"
32 #include "params/IrisISA.hh"
33 #include "sim/serialize.hh"
34 
35 void
37 {
39  for (int i = 0; i < ArmISA::NUM_PHYS_MISCREGS; i++)
40  miscRegs[i] = tc->readMiscRegNoEffect(i);
42 }
43 
44 Iris::ISA *
45 IrisISAParams::create()
46 {
47  return new Iris::ISA(this);
48 }
ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
isa.hh
serialize.hh
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
cp
Definition: cprintf.cc:40
BaseISA::tc
ThreadContext * tc
Definition: isa.hh:52
Iris::ISA
Definition: isa.hh:36
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:832
miscregs.hh
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:63
Iris::ISA::serialize
void serialize(CheckpointOut &cp) const
Serialize an object.
Definition: isa.cc:36
ArmISA::NUM_PHYS_MISCREGS
@ NUM_PHYS_MISCREGS
Definition: miscregs.hh:1057
thread_context.hh
RegVal
uint64_t RegVal
Definition: types.hh:168

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