gem5  v20.1.0.0
base_gic.hh
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37 
42 #ifndef __DEV_ARM_BASE_GIC_H__
43 #define __DEV_ARM_BASE_GIC_H__
44 
45 #include <unordered_map>
46 
47 #include "arch/arm/system.hh"
48 #include "dev/io_device.hh"
49 
50 class Platform;
51 class RealView;
52 class ThreadContext;
53 class ArmInterruptPin;
54 class ArmSPI;
55 class ArmPPI;
56 
57 struct ArmInterruptPinParams;
58 struct ArmPPIParams;
59 struct ArmSPIParams;
60 struct BaseGicParams;
61 
62 class BaseGic : public PioDevice
63 {
64  public:
65  typedef BaseGicParams Params;
66  enum class GicVersion { GIC_V2, GIC_V3, GIC_V4 };
67 
68  BaseGic(const Params *p);
69  virtual ~BaseGic();
70  void init() override;
71 
72  const Params * params() const;
73 
82  virtual void sendInt(uint32_t num) = 0;
83 
90  virtual void sendPPInt(uint32_t num, uint32_t cpu) = 0;
91  virtual void clearPPInt(uint32_t num, uint32_t cpu) = 0;
92 
101  virtual void clearInt(uint32_t num) = 0;
102 
103  ArmSystem *
104  getSystem() const
105  {
106  return (ArmSystem *) sys;
107  }
108 
110  virtual bool supportsVersion(GicVersion version) = 0;
111 
112  protected:
115 };
116 
118 {
119  public:
120  virtual uint32_t readDistributor(ContextID ctx, Addr daddr) = 0;
121  virtual uint32_t readCpu(ContextID ctx, Addr daddr) = 0;
122 
123  virtual void writeDistributor(ContextID ctx, Addr daddr,
124  uint32_t data) = 0;
125  virtual void writeCpu(ContextID ctx, Addr daddr, uint32_t data) = 0;
126 };
127 
136 {
137  public:
138  ArmInterruptPinGen(const ArmInterruptPinParams *p);
139 
140  virtual ArmInterruptPin* get(ThreadContext *tc = nullptr) = 0;
141 };
142 
149 {
150  public:
151  ArmSPIGen(const ArmSPIParams *p);
152 
153  ArmInterruptPin* get(ThreadContext *tc = nullptr) override;
154  protected:
156 };
157 
164 {
165  public:
166  ArmPPIGen(const ArmPPIParams *p);
167 
168  ArmInterruptPin* get(ThreadContext* tc = nullptr) override;
169  protected:
170  std::unordered_map<ContextID, ArmPPI*> pins;
171 };
172 
177 {
178  friend class ArmInterruptPinGen;
179  protected:
181  uint32_t int_num);
182 
183  public: /* Public interface */
192 
194  uint32_t num() const { return intNum; }
195 
197  bool active() const { return _active; }
198 
200  virtual void raise() = 0;
202  virtual void clear() = 0;
203 
204  public: /* Serializable interface */
205  void serialize(CheckpointOut &cp) const override;
206  void unserialize(CheckpointIn &cp) override;
207 
208  protected:
215  ContextID targetContext() const;
216 
222 
225 
227  const uint32_t intNum;
228 
230  bool _active;
231 };
232 
233 class ArmSPI : public ArmInterruptPin
234 {
235  friend class ArmSPIGen;
236  private:
237  ArmSPI(Platform *platform, uint32_t int_num);
238 
239  public:
240  void raise() override;
241  void clear() override;
242 };
243 
244 class ArmPPI : public ArmInterruptPin
245 {
246  friend class ArmPPIGen;
247  private:
248  ArmPPI(Platform *platform, ThreadContext *tc, uint32_t int_num);
249 
250  public:
251  void raise() override;
252  void clear() override;
253 };
254 
255 #endif
io_device.hh
BaseGic::Params
BaseGicParams Params
Definition: base_gic.hh:65
ArmSPI::ArmSPI
ArmSPI(Platform *platform, uint32_t int_num)
Definition: base_gic.cc:158
ArmPPIGen
Private Peripheral Interrupt Generator Since PPIs are banked in the GIC, this class is capable of gen...
Definition: base_gic.hh:163
ArmSPI::clear
void clear() override
Clear a signalled interrupt.
Definition: base_gic.cc:172
ArmSPIGen::ArmSPIGen
ArmSPIGen(const ArmSPIParams *p)
Definition: base_gic.cc:83
RealView
Definition: realview.hh:57
ArmInterruptPinGen::get
virtual ArmInterruptPin * get(ThreadContext *tc=nullptr)=0
data
const char data[]
Definition: circlebuf.test.cc:42
ArmPPIGen::pins
std::unordered_map< ContextID, ArmPPI * > pins
Definition: base_gic.hh:170
ArmInterruptPin::clear
virtual void clear()=0
Clear a signalled interrupt.
Serializable
Basic support for object serialization.
Definition: serialize.hh:172
ArmInterruptPin::setThreadContext
void setThreadContext(ThreadContext *tc)
Set the thread context owning this interrupt.
Definition: base_gic.cc:130
ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:231
ArmPPIGen::get
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
Definition: base_gic.cc:100
ArmInterruptPin::_active
bool _active
True if interrupt pin is active, false otherwise.
Definition: base_gic.hh:230
system.hh
BaseGic::supportsVersion
virtual bool supportsVersion(GicVersion version)=0
Check if version supported.
ArmInterruptPin::num
uint32_t num() const
Get interrupt number.
Definition: base_gic.hh:194
PioDevice::sys
System * sys
Definition: io_device.hh:102
ArmInterruptPin::intNum
const uint32_t intNum
Interrupt number to generate.
Definition: base_gic.hh:227
BaseGic::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base_gic.cc:66
ArmSPIGen::get
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
Definition: base_gic.cc:89
ArmSPIGen
Shared Peripheral Interrupt Generator It is capable of generating one interrupt only: it maintains a ...
Definition: base_gic.hh:148
cp
Definition: cprintf.cc:40
PioDevice
This device is the base class which all devices senstive to an address range inherit from.
Definition: io_device.hh:99
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
BaseGicRegisters
Definition: base_gic.hh:117
ArmInterruptPin::targetContext
ContextID targetContext() const
Get the target context ID of this interrupt.
Definition: base_gic.cc:139
ArmInterruptPin::ArmInterruptPin
ArmInterruptPin(Platform *platform, ThreadContext *tc, uint32_t int_num)
Definition: base_gic.cc:121
ArmInterruptPinGen
This SimObject is instantiated in the python world and serves as an ArmInterruptPin generator.
Definition: base_gic.hh:135
ArmPPI::clear
void clear() override
Clear a signalled interrupt.
Definition: base_gic.cc:192
BaseGic::platform
Platform * platform
Platform this GIC belongs to.
Definition: base_gic.hh:114
BaseGicRegisters::writeCpu
virtual void writeCpu(ContextID ctx, Addr daddr, uint32_t data)=0
BaseGicRegisters::writeDistributor
virtual void writeDistributor(ContextID ctx, Addr daddr, uint32_t data)=0
ArmInterruptPinGen::ArmInterruptPinGen
ArmInterruptPinGen(const ArmInterruptPinParams *p)
Definition: base_gic.cc:78
Platform
Definition: platform.hh:49
ArmInterruptPin::threadContext
const ThreadContext * threadContext
Pointer to the thread context that owns this interrupt in case it is a thread-/CPU-private interrupt.
Definition: base_gic.hh:221
BaseGic::clearPPInt
virtual void clearPPInt(uint32_t num, uint32_t cpu)=0
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
ArmInterruptPin::platform
RealView *const platform
Arm platform to use for interrupt generation.
Definition: base_gic.hh:224
ArmInterruptPin::active
bool active() const
True if interrupt pin is active, false otherwise.
Definition: base_gic.hh:197
BaseGic::sendInt
virtual void sendInt(uint32_t num)=0
Post an interrupt from a device that is connected to the GIC.
BaseGic::~BaseGic
virtual ~BaseGic()
Definition: base_gic.cc:61
BaseGic::clearInt
virtual void clearInt(uint32_t num)=0
Clear an interrupt from a device that is connected to the GIC.
ArmSystem
Definition: system.hh:59
BaseGic::BaseGic
BaseGic(const Params *p)
Definition: base_gic.cc:47
BaseGicRegisters::readDistributor
virtual uint32_t readDistributor(ContextID ctx, Addr daddr)=0
BaseGic
Definition: base_gic.hh:62
ArmSPIGen::pin
ArmSPI * pin
Definition: base_gic.hh:155
BaseGic::GicVersion::GIC_V3
@ GIC_V3
ArmInterruptPin
Generic representation of an Arm interrupt pin.
Definition: base_gic.hh:176
BaseGic::GicVersion::GIC_V2
@ GIC_V2
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:63
BaseGic::getSystem
ArmSystem * getSystem() const
Definition: base_gic.hh:104
BaseGic::params
const Params * params() const
Definition: base_gic.cc:73
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
BaseGic::sendPPInt
virtual void sendPPInt(uint32_t num, uint32_t cpu)=0
Interface call for private peripheral interrupts.
ArmPPIGen::ArmPPIGen
ArmPPIGen(const ArmPPIParams *p)
Definition: base_gic.cc:94
CheckpointIn
Definition: serialize.hh:67
ArmInterruptPin::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: base_gic.cc:147
ArmSPI
Definition: base_gic.hh:233
BaseGic::GicVersion
GicVersion
Definition: base_gic.hh:66
ArmPPI
Definition: base_gic.hh:244
ArmInterruptPin::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: base_gic.cc:153
ArmPPI::ArmPPI
ArmPPI(Platform *platform, ThreadContext *tc, uint32_t int_num)
Definition: base_gic.cc:178
BaseGic::GicVersion::GIC_V4
@ GIC_V4
BaseGicRegisters::readCpu
virtual uint32_t readCpu(ContextID ctx, Addr daddr)=0
SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:92

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