gem5  v20.1.0.0
branch64.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2011-2013 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
39 
40 namespace ArmISA
41 {
42 
45 {
46  ArmISA::PCState pcs = branchPC;
47  pcs.instNPC(pcs.pc() + imm);
48  pcs.advance();
49  return pcs;
50 }
51 
54 {
55  ArmISA::PCState pcs = branchPC;
56  pcs.instNPC(pcs.pc() + imm);
57  pcs.advance();
58  return pcs;
59 }
60 
63 {
64  ArmISA::PCState pcs = branchPC;
65  pcs.instNPC(pcs.pc() + imm2);
66  pcs.advance();
67  return pcs;
68 }
69 
70 std::string
72  Addr pc, const Loader::SymbolTable *symtab) const
73 {
74  std::stringstream ss;
75  printMnemonic(ss, "", false, true, condCode);
76  printTarget(ss, pc + imm, symtab);
77  return ss.str();
78 }
79 
80 std::string
82  Addr pc, const Loader::SymbolTable *symtab) const
83 {
84  std::stringstream ss;
85  printMnemonic(ss, "", false);
86  printTarget(ss, pc + imm, symtab);
87  return ss.str();
88 }
89 
90 std::string
92  Addr pc, const Loader::SymbolTable *symtab) const
93 {
94  std::stringstream ss;
95  printMnemonic(ss, "", false);
96  printIntReg(ss, op1);
97  return ss.str();
98 }
99 
100 std::string
102  Addr pc, const Loader::SymbolTable *symtab) const
103 {
104  std::stringstream ss;
105  printMnemonic(ss, "", false);
106  printIntReg(ss, op1);
107  ccprintf(ss, ", ");
108  printIntReg(ss, op2);
109  return ss.str();
110 }
111 
112 std::string
114  Addr pc, const Loader::SymbolTable *symtab) const
115 {
116  std::stringstream ss;
117  printMnemonic(ss, "", false);
118  if (op1 != INTREG_X30)
119  printIntReg(ss, op1);
120  return ss.str();
121 }
122 
123 std::string
125  Addr pc, const Loader::SymbolTable *symtab) const
126 {
127  std::stringstream ss;
128  printMnemonic(ss, "", false);
129  if (op1 != INTREG_X30)
130  printIntReg(ss, op1);
131  return ss.str();
132 }
133 
134 std::string
136  Addr pc, const Loader::SymbolTable *symtab) const
137 {
138  std::stringstream ss;
139  printMnemonic(ss, "", false);
140  return ss.str();
141 }
142 
143 std::string
145  Addr pc, const Loader::SymbolTable *symtab) const
146 {
147  std::stringstream ss;
148  printMnemonic(ss, "", false);
149  return ss.str();
150 }
151 
152 std::string
154  Addr pc, const Loader::SymbolTable *symtab) const
155 {
156  std::stringstream ss;
157  printMnemonic(ss, "", false);
158  printIntReg(ss, op1);
159  ccprintf(ss, ", ");
160  printTarget(ss, pc + imm, symtab);
161  return ss.str();
162 }
163 
164 std::string
166  Addr pc, const Loader::SymbolTable *symtab) const
167 {
168  std::stringstream ss;
169  printMnemonic(ss, "", false);
170  printIntReg(ss, op1);
171  ccprintf(ss, ", #%#x, ", imm1);
172  printTarget(ss, pc + imm2, symtab);
173  return ss.str();
174 }
175 
176 } // namespace ArmISA
ArmISA::BranchImmImmReg64::op1
IntRegIndex op1
Definition: branch64.hh:197
ArmISA::BranchRegReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:101
ArmISA::BranchImm64::branchTarget
ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const override
Definition: branch64.cc:44
ArmISA::BranchReg64::op1
IntRegIndex op1
Definition: branch64.hh:104
ArmISA::BranchImmImmReg64::imm1
int64_t imm1
Definition: branch64.hh:195
Loader::SymbolTable
Definition: symtab.hh:59
branch64.hh
ArmISA::ArmStaticInst::printIntReg
void printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:296
ArmISA::BranchRet64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:113
ArmISA
Definition: ccregs.hh:41
ArmISA::BranchEret64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:135
ArmISA::BranchImmReg64::imm
int64_t imm
Definition: branch64.hh:172
ArmISA::BranchImm64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:81
ArmISA::BranchRegReg64::op1
IntRegIndex op1
Definition: branch64.hh:87
ArmISA::BranchRetA64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:124
ArmISA::BranchImmReg64::branchTarget
ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const override
Definition: branch64.cc:53
ArmISA::ss
Bitfield< 21 > ss
Definition: miscregs_types.hh:56
ArmISA::BranchImmImmReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:165
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
ArmISA::BranchImmImmReg64::imm2
int64_t imm2
Definition: branch64.hh:196
ArmISA::BranchRegReg64::op2
IntRegIndex op2
Definition: branch64.hh:88
ArmISA::BranchImmCond64::condCode
ConditionCode condCode
Definition: branch64.hh:71
ArmISA::BranchImmImmReg64::branchTarget
ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const override
Definition: branch64.cc:62
ArmISA::BranchImmCond64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:71
ArmISA::BranchImm64::imm
int64_t imm
Definition: branch64.hh:49
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
ArmISA::BranchReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:91
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
ArmISA::BranchImmReg64::op1
IntRegIndex op1
Definition: branch64.hh:173
ArmISA::ArmStaticInst::printMnemonic
void printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const
Definition: static_inst.cc:374
ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:127
ArmISA::INTREG_X30
@ INTREG_X30
Definition: intregs.hh:157
ArmISA::BranchEretA64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:144
ArmISA::ArmStaticInst::printTarget
void printTarget(std::ostream &os, Addr target, const Loader::SymbolTable *symtab) const
Definition: static_inst.cc:395
ArmISA::BranchImmReg64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch64.cc:153

Generated on Wed Sep 30 2020 14:02:00 for gem5 by doxygen 1.8.17