ArmISA::Stage2MMU::Stage2Translation Class Reference

This translation class is used to trigger the data fetch once a timing translation returns the translated physical address. More...

#include <stage2_mmu.hh>

Inheritance diagram for ArmISA::Stage2MMU::Stage2Translation:

Public Member Functions
	Stage2Translation (Stage2MMU &_parent, uint8_t *_data, Event *_event, Addr _oVAddr)
void	markDelayed ()
	Signal that the translation has been delayed due to a hw page table walk. More...
void	finish (const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode)
void	setVirt (Addr vaddr, int size, Request::Flags flags, int requestorId)
void	translateTiming (ThreadContext *tc)
Public Member Functions inherited from BaseTLB::Translation
virtual	~Translation ()
virtual bool	squashed () const
	This function is used by the page table walker to determine if it should translate the a pending request or if the underlying request has been squashed. More...

Public Attributes
Fault	fault

Private Attributes
uint8_t *	data
int	numBytes
RequestPtr	req
Event *	event
Stage2MMU &	parent
Addr	oVAddr

Detailed Description

This translation class is used to trigger the data fetch once a timing translation returns the translated physical address.

Definition at line 68 of file stage2_mmu.hh.

Constructor & Destructor Documentation

Stage2Translation()

Stage2MMU::Stage2Translation::Stage2Translation	(	Stage2MMU &	_parent,
		uint8_t *	_data,
		Event *	_event,
		Addr	_oVAddr
	)

Definition at line 110 of file stage2_mmu.cc.

References req.

Member Function Documentation

finish()

void Stage2MMU::Stage2Translation::finish ( const Fault &  fault, const RequestPtr &  req, ThreadContext *  tc, BaseTLB::Mode  mode  )

virtual

Implements BaseTLB::Translation.

Definition at line 119 of file stage2_mmu.cc.

References ArmISA::ArmFault::annotate(), data, MipsISA::event, ThreadContext::getCpuPtr(), Request::NO_ACCESS, NoFault, ArmISA::ArmFault::OVA, MemCmd::ReadReq, and ArmISA::ArmFault::S1PTW.

markDelayed()

void ArmISA::Stage2MMU::Stage2Translation::markDelayed ( )

inlinevirtual

Signal that the translation has been delayed due to a hw page table walk.

Implements BaseTLB::Translation.

Definition at line 85 of file stage2_mmu.hh.

setVirt()

void ArmISA::Stage2MMU::Stage2Translation::setVirt ( Addr  vaddr, int  size, Request::Flags  flags, int  requestorId  )

inline

Definition at line 91 of file stage2_mmu.hh.

References numBytes, req, ArmISA::Stage2MMU::requestorId, and MipsISA::vaddr.

Referenced by ArmISA::Stage2MMU::readDataTimed().

translateTiming()

void ArmISA::Stage2MMU::Stage2Translation::translateTiming ( ThreadContext *  tc )

inline

Definition at line 98 of file stage2_mmu.hh.

References parent, BaseTLB::Read, req, ArmISA::Stage2MMU::stage2Tlb(), and ArmISA::TLB::translateTiming().

Referenced by ArmISA::Stage2MMU::readDataTimed().

Member Data Documentation

data

uint8_t* ArmISA::Stage2MMU::Stage2Translation::data

private

Definition at line 71 of file stage2_mmu.hh.

event

Event* ArmISA::Stage2MMU::Stage2Translation::event

private

Definition at line 74 of file stage2_mmu.hh.

fault

Fault ArmISA::Stage2MMU::Stage2Translation::fault

Definition at line 79 of file stage2_mmu.hh.

Referenced by ArmISA::TableWalker::fetchDescriptor().

numBytes

int ArmISA::Stage2MMU::Stage2Translation::numBytes

private

Definition at line 72 of file stage2_mmu.hh.

Referenced by setVirt().

oVAddr

Addr ArmISA::Stage2MMU::Stage2Translation::oVAddr

private

Definition at line 76 of file stage2_mmu.hh.

parent

Stage2MMU& ArmISA::Stage2MMU::Stage2Translation::parent

private

Definition at line 75 of file stage2_mmu.hh.

Referenced by translateTiming().

req

RequestPtr ArmISA::Stage2MMU::Stage2Translation::req

private

Definition at line 73 of file stage2_mmu.hh.

Referenced by setVirt(), Stage2Translation(), and translateTiming().

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The documentation for this class was generated from the following files:

• arch/arm/stage2_mmu.hh
• arch/arm/stage2_mmu.cc