gem5
v20.1.0.0
arch
x86
cpuid.hh
Go to the documentation of this file.
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/*
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* Copyright (c) 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_X86_CPUID_HH__
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#define __ARCH_X86_CPUID_HH__
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#include "
base/types.hh
"
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class
ThreadContext
;
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namespace
X86ISA
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{
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struct
CpuidResult
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{
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uint64_t
rax
;
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uint64_t
rbx
;
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uint64_t
rcx
;
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uint64_t
rdx
;
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// These are not in alphebetical order on purpose. The order reflects
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// how the CPUID orders the registers when it returns results.
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CpuidResult
(uint64_t _rax, uint64_t _rbx,
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uint64_t _rdx, uint64_t _rcx) :
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rax
(_rax),
rbx
(_rbx),
rcx
(_rcx),
rdx
(_rdx)
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{}
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CpuidResult
()
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{}
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};
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uint64_t
stringToRegister
(
const
char
*str);
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bool
doCpuid
(
ThreadContext
* tc, uint32_t
function
,
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uint32_t
index
, CpuidResult &result);
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}
// namespace X86ISA
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#endif
X86ISA::CpuidResult::CpuidResult
CpuidResult(uint64_t _rax, uint64_t _rbx, uint64_t _rdx, uint64_t _rcx)
Definition:
cpuid.hh:47
X86ISA::CpuidResult::CpuidResult
CpuidResult()
Definition:
cpuid.hh:52
X86ISA::CpuidResult::rax
uint64_t rax
Definition:
cpuid.hh:40
X86ISA::stringToRegister
uint64_t stringToRegister(const char *str)
Definition:
cpuid.cc:76
X86ISA::index
Bitfield< 5, 3 > index
Definition:
types.hh:93
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition:
thread_context.hh:88
X86ISA::CpuidResult::rbx
uint64_t rbx
Definition:
cpuid.hh:41
X86ISA
This is exposed globally, independent of the ISA.
Definition:
acpi.hh:55
types.hh
X86ISA::doCpuid
bool doCpuid(ThreadContext *tc, uint32_t function, uint32_t index, CpuidResult &result)
Definition:
cpuid.cc:87
X86ISA::CpuidResult::rcx
uint64_t rcx
Definition:
cpuid.hh:42
X86ISA::CpuidResult
Definition:
cpuid.hh:38
X86ISA::CpuidResult::rdx
uint64_t rdx
Definition:
cpuid.hh:43
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