gem5  v20.1.0.0
cpuid.hh
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28 
29 #ifndef __ARCH_X86_CPUID_HH__
30 #define __ARCH_X86_CPUID_HH__
31 
32 #include "base/types.hh"
33 
34 class ThreadContext;
35 
36 namespace X86ISA
37 {
38  struct CpuidResult
39  {
40  uint64_t rax;
41  uint64_t rbx;
42  uint64_t rcx;
43  uint64_t rdx;
44 
45  // These are not in alphebetical order on purpose. The order reflects
46  // how the CPUID orders the registers when it returns results.
47  CpuidResult(uint64_t _rax, uint64_t _rbx,
48  uint64_t _rdx, uint64_t _rcx) :
49  rax(_rax), rbx(_rbx), rcx(_rcx), rdx(_rdx)
50  {}
51 
53  {}
54  };
55 
56  uint64_t stringToRegister(const char *str);
57 
58  bool doCpuid(ThreadContext * tc, uint32_t function,
59  uint32_t index, CpuidResult &result);
60 } // namespace X86ISA
61 
62 #endif
X86ISA::CpuidResult::CpuidResult
CpuidResult(uint64_t _rax, uint64_t _rbx, uint64_t _rdx, uint64_t _rcx)
Definition: cpuid.hh:47
X86ISA::CpuidResult::CpuidResult
CpuidResult()
Definition: cpuid.hh:52
X86ISA::CpuidResult::rax
uint64_t rax
Definition: cpuid.hh:40
X86ISA::stringToRegister
uint64_t stringToRegister(const char *str)
Definition: cpuid.cc:76
X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:93
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
X86ISA::CpuidResult::rbx
uint64_t rbx
Definition: cpuid.hh:41
X86ISA
This is exposed globally, independent of the ISA.
Definition: acpi.hh:55
types.hh
X86ISA::doCpuid
bool doCpuid(ThreadContext *tc, uint32_t function, uint32_t index, CpuidResult &result)
Definition: cpuid.cc:87
X86ISA::CpuidResult::rcx
uint64_t rcx
Definition: cpuid.hh:42
X86ISA::CpuidResult
Definition: cpuid.hh:38
X86ISA::CpuidResult::rdx
uint64_t rdx
Definition: cpuid.hh:43

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