gem5
v20.1.0.0
arch
x86
cpuid.cc
Go to the documentation of this file.
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/*
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* Copyright (c) 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
arch/x86/cpuid.hh
"
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#include "
base/bitfield.hh
"
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#include "
cpu/thread_context.hh
"
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namespace
X86ISA
{
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enum
StandardCpuidFunction
{
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VendorAndLargestStdFunc
,
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FamilyModelStepping
,
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CacheAndTLB
,
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SerialNumber
,
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CacheParams
,
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MonitorMwait
,
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ThermalPowerMgmt
,
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ExtendedFeatures
,
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NumStandardCpuidFuncs
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};
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enum
ExtendedCpuidFunctions
{
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VendorAndLargestExtFunc
,
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FamilyModelSteppingBrandFeatures
,
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NameString1
,
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NameString2
,
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NameString3
,
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L1CacheAndTLB
,
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L2L3CacheAndL2TLB
,
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APMInfo
,
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LongModeAddressSize
,
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/*
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* The following are defined by the spec but not yet implemented
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*/
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/* // Function 9 is reserved
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SVMInfo = 10,
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// Functions 11-24 are reserved
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TLB1GBPageInfo = 25,
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PerformanceInfo,*/
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NumExtendedCpuidFuncs
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};
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static
const
int
vendorStringSize
= 13;
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static
const
char
vendorString
[
vendorStringSize
] =
"M5 Simulator"
;
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static
const
int
nameStringSize
= 48;
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static
const
char
nameString
[
nameStringSize
] =
"Fake M5 x86_64 CPU"
;
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uint64_t
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stringToRegister
(
const
char
*str)
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{
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uint64_t
reg
= 0;
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for
(
int
pos = 3; pos >=0; pos--) {
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reg
<<= 8;
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reg
|= str[pos];
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}
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return
reg
;
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}
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bool
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doCpuid
(
ThreadContext
* tc, uint32_t
function
,
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uint32_t
index
,
CpuidResult
&result)
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{
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uint16_t family =
bits
(
function
, 31, 16);
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uint16_t funcNum =
bits
(
function
, 15, 0);
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if
(family == 0x8000) {
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// The extended functions
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switch
(funcNum) {
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case
VendorAndLargestExtFunc
:
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assert(
vendorStringSize
>= 12);
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result =
CpuidResult
(
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0x80000000 +
NumExtendedCpuidFuncs
- 1,
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stringToRegister
(
vendorString
),
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stringToRegister
(
vendorString
+ 4),
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stringToRegister
(
vendorString
+ 8));
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break
;
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case
FamilyModelSteppingBrandFeatures
:
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result =
CpuidResult
(0x00020f51, 0x00000405,
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0xe3d3fbff, 0x00000001);
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break
;
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case
NameString1
:
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case
NameString2
:
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case
NameString3
:
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{
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// Zero fill anything beyond the end of the string. This
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// should go away once the string is a vetted parameter.
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char
cleanName[
nameStringSize
];
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memset(cleanName,
'\0'
,
nameStringSize
);
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strncpy(cleanName,
nameString
,
nameStringSize
);
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int
offset
= (funcNum -
NameString1
) * 16;
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assert(
nameStringSize
>=
offset
+ 16);
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result =
CpuidResult
(
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stringToRegister
(cleanName +
offset
+ 0),
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stringToRegister
(cleanName +
offset
+ 4),
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stringToRegister
(cleanName +
offset
+ 12),
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stringToRegister
(cleanName +
offset
+ 8));
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}
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break
;
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case
L1CacheAndTLB
:
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result =
CpuidResult
(0xff08ff08, 0xff20ff20,
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0x40020140, 0x40020140);
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break
;
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case
L2L3CacheAndL2TLB
:
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result =
CpuidResult
(0x00000000, 0x42004200,
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0x00000000, 0x04008140);
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break
;
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case
APMInfo
:
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result =
CpuidResult
(0x80000018, 0x68747541,
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0x69746e65, 0x444d4163);
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break
;
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case
LongModeAddressSize
:
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result =
CpuidResult
(0x00003030, 0x00000000,
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0x00000000, 0x00000000);
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break
;
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/* case SVMInfo:
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case TLB1GBPageInfo:
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case PerformanceInfo:*/
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default
:
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warn
(
"x86 cpuid family 0x8000: unimplemented function %u"
,
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funcNum);
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return
false
;
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}
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}
else
if
(family == 0x0000) {
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// The standard functions
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switch
(funcNum) {
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case
VendorAndLargestStdFunc
:
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assert(
vendorStringSize
>= 12);
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result =
CpuidResult
(
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NumStandardCpuidFuncs
- 1,
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stringToRegister
(
vendorString
),
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stringToRegister
(
vendorString
+ 4),
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stringToRegister
(
vendorString
+ 8));
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break
;
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case
FamilyModelStepping
:
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result =
CpuidResult
(0x00020f51, 0x00000805,
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0xe7dbfbff, 0x00000209);
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break
;
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case
ExtendedFeatures
:
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result =
CpuidResult
(0x00000000, 0x01800000,
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0x00000000, 0x00000000);
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break
;
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default
:
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warn
(
"x86 cpuid family 0x0000: unimplemented function %u"
,
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funcNum);
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return
false
;
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}
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}
else
{
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warn
(
"x86 cpuid: unknown family %#x"
, family);
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return
false
;
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}
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return
true
;
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}
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}
// namespace X86ISA
X86ISA::nameStringSize
static const int nameStringSize
Definition:
cpuid.cc:72
warn
#define warn(...)
Definition:
logging.hh:239
X86ISA::vendorStringSize
static const int vendorStringSize
Definition:
cpuid.cc:70
X86ISA::CacheParams
@ CacheParams
Definition:
cpuid.cc:40
X86ISA::NameString1
@ NameString1
Definition:
cpuid.cc:50
X86ISA::VendorAndLargestStdFunc
@ VendorAndLargestStdFunc
Definition:
cpuid.cc:36
X86ISA::LongModeAddressSize
@ LongModeAddressSize
Definition:
cpuid.cc:56
X86ISA::VendorAndLargestExtFunc
@ VendorAndLargestExtFunc
Definition:
cpuid.cc:48
X86ISA::StandardCpuidFunction
StandardCpuidFunction
Definition:
cpuid.cc:35
X86ISA::APMInfo
@ APMInfo
Definition:
cpuid.cc:55
X86ISA::stringToRegister
uint64_t stringToRegister(const char *str)
Definition:
cpuid.cc:76
X86ISA::reg
Bitfield< 5, 3 > reg
Definition:
types.hh:87
X86ISA::vendorString
static const char vendorString[vendorStringSize]
Definition:
cpuid.cc:71
X86ISA::ExtendedCpuidFunctions
ExtendedCpuidFunctions
Definition:
cpuid.cc:47
X86ISA::index
Bitfield< 5, 3 > index
Definition:
types.hh:93
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition:
thread_context.hh:88
bitfield.hh
X86ISA::L2L3CacheAndL2TLB
@ L2L3CacheAndL2TLB
Definition:
cpuid.cc:54
X86ISA::ExtendedFeatures
@ ExtendedFeatures
Definition:
cpuid.cc:43
X86ISA::NumStandardCpuidFuncs
@ NumStandardCpuidFuncs
Definition:
cpuid.cc:44
X86ISA::FamilyModelStepping
@ FamilyModelStepping
Definition:
cpuid.cc:37
X86ISA::NumExtendedCpuidFuncs
@ NumExtendedCpuidFuncs
Definition:
cpuid.cc:67
X86ISA
This is exposed globally, independent of the ISA.
Definition:
acpi.hh:55
X86ISA::offset
offset
Definition:
misc.hh:1024
X86ISA::nameString
static const char nameString[nameStringSize]
Definition:
cpuid.cc:73
X86ISA::MonitorMwait
@ MonitorMwait
Definition:
cpuid.cc:41
X86ISA::NameString2
@ NameString2
Definition:
cpuid.cc:51
X86ISA::FamilyModelSteppingBrandFeatures
@ FamilyModelSteppingBrandFeatures
Definition:
cpuid.cc:49
X86ISA::doCpuid
bool doCpuid(ThreadContext *tc, uint32_t function, uint32_t index, CpuidResult &result)
Definition:
cpuid.cc:87
cpuid.hh
X86ISA::L1CacheAndTLB
@ L1CacheAndTLB
Definition:
cpuid.cc:53
X86ISA::NameString3
@ NameString3
Definition:
cpuid.cc:52
X86ISA::CacheAndTLB
@ CacheAndTLB
Definition:
cpuid.cc:38
X86ISA::ThermalPowerMgmt
@ ThermalPowerMgmt
Definition:
cpuid.cc:42
thread_context.hh
X86ISA::SerialNumber
@ SerialNumber
Definition:
cpuid.cc:39
X86ISA::CpuidResult
Definition:
cpuid.hh:38
bits
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition:
bitfield.hh:75
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