Go to the documentation of this file.
46 #ifndef __CPU_TRAFFIC_GEN_HYBRID_GEN_HH__
47 #define __CPU_TRAFFIC_GEN_HYBRID_GEN_HH__
52 #include "enums/AddrMap.hh"
100 Addr start_addr_dram,
Addr end_addr_dram,
102 Addr start_addr_nvm,
Addr end_addr_nvm,
106 uint8_t read_percent,
Addr data_limit,
107 unsigned int num_seq_pkts_dram,
unsigned int page_size_dram,
108 unsigned int nbr_of_banks_dram,
unsigned int nbr_of_banks_util_dram,
109 unsigned int num_seq_pkts_nvm,
unsigned int buffer_size_nvm,
110 unsigned int nbr_of_banks_nvm,
unsigned int nbr_of_banks_util_nvm,
111 Enums::AddrMap addr_mapping,
112 unsigned int nbr_of_ranks_dram,
113 unsigned int nbr_of_ranks_nvm,
114 uint8_t nvm_percent);
126 void genStartAddr(
unsigned int new_bank ,
unsigned int new_rank);
Addr addr
Address of request.
Base class for all generators, with the shared functionality and virtual functions for entering,...
Addr endAddr
End of address range.
const unsigned int blockBitsDram
Number of block bits in DRAM address.
Enums::AddrMap addrMapping
Address mapping to be used.
const Addr cacheLineSize
Cache line size in the simulated system.
const Addr startAddrNvm
Start of DRAM address range.
const unsigned int bufferSizeNvm
Buffer size of NVM.
Addr dataManipulated
Counter to determine the amount of data manipulated.
uint64_t Tick
Tick count type.
const uint8_t readPercent
Percent of generated transactions that should be reads.
const unsigned int pageBitsNvm
Number of buffer bits in NVM address.
unsigned int countNumSeqPkts
Track number of sequential packets generated for a request
bool isNvm
Remember the interface to be generated in series.
unsigned int blockBits
Number of block bits in DRAM address.
const Addr blocksizeNvm
Blocksize and address increment for DRAM.
Hybrid NVM + DRAM specific generator is for issuing request with variable buffer hit length and bank ...
const unsigned int numSeqPktsNvm
const unsigned int pageBitsDram
Number of page bits in DRAM address.
const unsigned int bankBitsDram
Number of bank bits in DRAM address.
const Addr dataLimit
Maximum amount of data to manipulate.
PacketPtr getNextPacket()
Get the next generated packet.
Addr startAddr
Start of address range.
const Addr endAddrNvm
End of DRAM address range.
const unsigned int pageSizeDram
Page size of DRAM.
unsigned int nbrOfRanks
Number of ranks to be utilized for a given configuration.
const unsigned int numSeqPktsDram
Number of sequential packets to be generated per cpu request.
const unsigned int nbrOfRanksDram
Number of ranks to be utilized for a given configuration.
const uint8_t nvmPercent
Percent of generated transactions that should go to NVM.
const unsigned int nbrOfBanksUtilNvm
Number of banks to be utilized for a given configuration.
unsigned int rankBits
Number of rank bits in DRAM address.
const Addr startAddrDram
Start of DRAM address range.
unsigned int pageBits
Number of page bits in DRAM address.
const unsigned int nbrOfRanksNvm
Number of ranks to be utilized for a given configuration.
const unsigned int rankBitsDram
Number of rank bits in DRAM address.
unsigned int bankBits
Number of bank bits in DRAM address.
const unsigned int nbrOfBanksUtilDram
Number of banks to be utilized for a given configuration.
void enter()
Enter this generator state.
const unsigned int rankBitsNvm
Number of rank bits in DRAM address.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Tick nextPacketTick(bool elastic, Tick delay) const
Determine the tick when the next packet is available.
unsigned int pageSize
Page size of DRAM.
const unsigned int blockBitsNvm
Number of block bits in NVM address.
Addr blocksize
Blocksize and address increment.
void genStartAddr(unsigned int new_bank, unsigned int new_rank)
Insert bank, rank, and column bits into packed address to create address for 1st command in a series.
HybridGen(SimObject &obj, RequestorID requestor_id, Tick _duration, Addr start_addr_dram, Addr end_addr_dram, Addr blocksize_dram, Addr start_addr_nvm, Addr end_addr_nvm, Addr blocksize_nvm, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts_dram, unsigned int page_size_dram, unsigned int nbr_of_banks_dram, unsigned int nbr_of_banks_util_dram, unsigned int num_seq_pkts_nvm, unsigned int buffer_size_nvm, unsigned int nbr_of_banks_nvm, unsigned int nbr_of_banks_util_nvm, Enums::AddrMap addr_mapping, unsigned int nbr_of_ranks_dram, unsigned int nbr_of_ranks_nvm, uint8_t nvm_percent)
Create a hybrid DRAM + NVM address sequence generator.
unsigned int numSeqPkts
Number of sequential DRAM packets to be generated per cpu request.
unsigned int nbrOfBanksUtil
Number of banks to be utilized for a given configuration.
const unsigned int nbrOfBanksNvm
Number of banks in NVM.
unsigned int nbrOfBanks
Number of banks in DRAM.
const Tick minPeriod
Request generation period.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
const Addr endAddrDram
End of DRAM address range.
bool isRead
Remember type of requests to be generated in series.
const Addr blocksizeDram
Blocksize and address increment for DRAM.
const unsigned int bankBitsNvm
Number of bank bits in NVM address.
const unsigned int nbrOfBanksDram
Number of banks in DRAM.
Abstract superclass for simulation objects.
Generated on Wed Sep 30 2020 14:02:09 for gem5 by doxygen 1.8.17