gem5  v20.1.0.0
kmi.hh
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40 
41 
46 #ifndef __DEV_ARM_PL050_HH__
47 #define __DEV_ARM_PL050_HH__
48 
49 #include <list>
50 
51 #include "base/vnc/vncinput.hh"
52 #include "dev/arm/amba_device.hh"
53 #include "params/Pl050.hh"
54 
55 class PS2Device;
56 
57 class Pl050 : public AmbaIntDevice
58 {
59  protected:
60  static const int kmiCr = 0x000;
61  static const int kmiStat = 0x004;
62  static const int kmiData = 0x008;
63  static const int kmiClkDiv = 0x00C;
64  static const int kmiISR = 0x010;
65 
66  BitUnion8(ControlReg)
67  Bitfield<0> force_clock_low;
68  Bitfield<1> force_data_low;
69  Bitfield<2> enable;
70  Bitfield<3> txint_enable;
71  Bitfield<4> rxint_enable;
72  Bitfield<5> type;
73  EndBitUnion(ControlReg)
74 
75 
77  ControlReg control;
78 
80  BitUnion8(StatusReg)
81  Bitfield<0> data_in;
82  Bitfield<1> clk_in;
83  Bitfield<2> rxparity;
84  Bitfield<3> rxbusy;
85  Bitfield<4> rxfull;
86  Bitfield<5> txbusy;
87  Bitfield<6> txempty;
88  EndBitUnion(StatusReg)
89 
90  StatusReg status;
91 
97  uint8_t clkdiv;
98 
99  BitUnion8(InterruptReg)
100  Bitfield<0> rx;
101  Bitfield<1> tx;
102  EndBitUnion(InterruptReg)
103 
104 
105  InterruptReg rawInterrupts;
106 
108  void setTxInt(bool value);
109 
111  void updateRxInt();
112 
117  void updateIntCtrl(InterruptReg ints, ControlReg ctrl);
118 
119  void setInterrupts(InterruptReg ints) { updateIntCtrl(ints, control); }
120  void setControl(ControlReg ctrl) { updateIntCtrl(rawInterrupts, ctrl); }
121 
123  InterruptReg getInterrupt() const;
124 
127 
128  public:
129  Pl050(const Pl050Params *p);
130 
131  Tick read(PacketPtr pkt) override;
132  Tick write(PacketPtr pkt) override;
133 
134  void serialize(CheckpointOut &cp) const override;
135  void unserialize(CheckpointIn &cp) override;
136 };
137 
138 #endif // __DEV_ARM_PL050_HH__
ArmISA::status
Bitfield< 5, 0 > status
Definition: miscregs_types.hh:417
Pl050::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: kmi.cc:206
amba_device.hh
Pl050::kmiClkDiv
static const int kmiClkDiv
Definition: kmi.hh:63
vncinput.hh
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:63
Pl050::updateIntCtrl
void updateIntCtrl(InterruptReg ints, ControlReg ctrl)
Update the status of the interrupt and control registers and deliver an interrupt if required.
Definition: kmi.cc:176
Pl050::setInterrupts
void setInterrupts(InterruptReg ints)
Definition: kmi.hh:119
PS2Device
Definition: device.hh:51
Pl050::rxparity
Bitfield< 2 > rxparity
Definition: kmi.hh:83
Pl050::setTxInt
void setTxInt(bool value)
Set or clear the TX interrupt.
Definition: kmi.cc:156
Pl050::kmiISR
static const int kmiISR
Definition: kmi.hh:64
Pl050::type
Bitfield< 5 > type
Definition: kmi.hh:72
Pl050::txbusy
Bitfield< 5 > txbusy
Definition: kmi.hh:86
cp
Definition: cprintf.cc:40
Pl050::tx
Bitfield< 1 > tx
Definition: kmi.hh:101
Pl050::kmiData
static const int kmiData
Definition: kmi.hh:62
Pl050::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: kmi.cc:60
Pl050::ps2
PS2Device * ps2
PS2 device connected to this KMI interface.
Definition: kmi.hh:126
Pl050::rxbusy
Bitfield< 3 > rxbusy
Definition: kmi.hh:84
Pl050::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: kmi.cc:215
Pl050::enable
Bitfield< 2 > enable
Definition: kmi.hh:69
Pl050::setControl
void setControl(ControlReg ctrl)
Definition: kmi.hh:120
AmbaIntDevice
Definition: amba_device.hh:86
Pl050::clk_in
Bitfield< 1 > clk_in
Definition: kmi.hh:82
Pl050::Pl050
Pl050(const Pl050Params *p)
Definition: kmi.cc:51
Pl050::rxint_enable
Bitfield< 4 > rxint_enable
Definition: kmi.hh:71
Pl050::EndBitUnion
EndBitUnion(ControlReg) ControlReg control
control register
Pl050::kmiStat
static const int kmiStat
Definition: kmi.hh:61
Pl050::force_data_low
Bitfield< 1 > force_data_low
Definition: kmi.hh:68
Pl050::BitUnion8
BitUnion8(ControlReg) Bitfield< 0 > force_clock_low
Pl050::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: kmi.cc:112
Pl050
Definition: kmi.hh:57
Pl050::rxfull
Bitfield< 4 > rxfull
Definition: kmi.hh:85
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
Pl050::txempty
Bitfield< 6 > txempty
Definition: kmi.hh:87
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:63
Pl050::clkdiv
uint8_t clkdiv
clock divisor register This register is just kept around to satisfy reads after driver does writes.
Definition: kmi.hh:97
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
CheckpointIn
Definition: serialize.hh:67
Pl050::getInterrupt
InterruptReg getInterrupt() const
Get current interrupt value.
Definition: kmi.cc:195
Pl050::txint_enable
Bitfield< 3 > txint_enable
Definition: kmi.hh:70
Pl050::kmiCr
static const int kmiCr
Definition: kmi.hh:60
Pl050::updateRxInt
void updateRxInt()
Update the RX interrupt using PS/2 device state.
Definition: kmi.cc:166

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