gem5  v20.1.0.0
msr.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2011 Google
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include "arch/x86/regs/msr.hh"
30 
31 namespace X86ISA
32 {
33 
34 typedef MsrMap::value_type MsrVal;
35 
36 const MsrMap::value_type msrMapData[] = {
37  MsrVal(0x10, MISCREG_TSC),
39  MsrVal(0xFE, MISCREG_MTRRCAP),
43  MsrVal(0x179, MISCREG_MCG_CAP),
44  MsrVal(0x17A, MISCREG_MCG_STATUS),
45  MsrVal(0x17B, MISCREG_MCG_CTL),
78  MsrVal(0x277, MISCREG_PAT),
79  MsrVal(0x2FF, MISCREG_DEF_TYPE),
80  MsrVal(0x400, MISCREG_MC0_CTL),
81  MsrVal(0x404, MISCREG_MC1_CTL),
82  MsrVal(0x408, MISCREG_MC2_CTL),
83  MsrVal(0x40C, MISCREG_MC3_CTL),
84  MsrVal(0x410, MISCREG_MC4_CTL),
85  MsrVal(0x414, MISCREG_MC5_CTL),
86  MsrVal(0x418, MISCREG_MC6_CTL),
87  MsrVal(0x41C, MISCREG_MC7_CTL),
88  MsrVal(0x401, MISCREG_MC0_STATUS),
89  MsrVal(0x405, MISCREG_MC1_STATUS),
90  MsrVal(0x409, MISCREG_MC2_STATUS),
91  MsrVal(0x40D, MISCREG_MC3_STATUS),
92  MsrVal(0x411, MISCREG_MC4_STATUS),
93  MsrVal(0x415, MISCREG_MC5_STATUS),
94  MsrVal(0x419, MISCREG_MC6_STATUS),
95  MsrVal(0x41D, MISCREG_MC7_STATUS),
96  MsrVal(0x402, MISCREG_MC0_ADDR),
97  MsrVal(0x406, MISCREG_MC1_ADDR),
98  MsrVal(0x40A, MISCREG_MC2_ADDR),
99  MsrVal(0x40E, MISCREG_MC3_ADDR),
100  MsrVal(0x412, MISCREG_MC4_ADDR),
101  MsrVal(0x416, MISCREG_MC5_ADDR),
102  MsrVal(0x41A, MISCREG_MC6_ADDR),
103  MsrVal(0x41E, MISCREG_MC7_ADDR),
104  MsrVal(0x403, MISCREG_MC0_MISC),
105  MsrVal(0x407, MISCREG_MC1_MISC),
106  MsrVal(0x40B, MISCREG_MC2_MISC),
107  MsrVal(0x40F, MISCREG_MC3_MISC),
108  MsrVal(0x413, MISCREG_MC4_MISC),
109  MsrVal(0x417, MISCREG_MC5_MISC),
110  MsrVal(0x41B, MISCREG_MC6_MISC),
111  MsrVal(0x41F, MISCREG_MC7_MISC),
112  MsrVal(0xC0000080, MISCREG_EFER),
113  MsrVal(0xC0000081, MISCREG_STAR),
114  MsrVal(0xC0000082, MISCREG_LSTAR),
115  MsrVal(0xC0000083, MISCREG_CSTAR),
116  MsrVal(0xC0000084, MISCREG_SF_MASK),
117  MsrVal(0xC0000100, MISCREG_FS_BASE),
118  MsrVal(0xC0000101, MISCREG_GS_BASE),
119  MsrVal(0xC0000102, MISCREG_KERNEL_GS_BASE),
120  MsrVal(0xC0000103, MISCREG_TSC_AUX),
121  MsrVal(0xC0010000, MISCREG_PERF_EVT_SEL0),
122  MsrVal(0xC0010001, MISCREG_PERF_EVT_SEL1),
123  MsrVal(0xC0010002, MISCREG_PERF_EVT_SEL2),
124  MsrVal(0xC0010003, MISCREG_PERF_EVT_SEL3),
125  MsrVal(0xC0010004, MISCREG_PERF_EVT_CTR0),
126  MsrVal(0xC0010005, MISCREG_PERF_EVT_CTR1),
127  MsrVal(0xC0010006, MISCREG_PERF_EVT_CTR2),
128  MsrVal(0xC0010007, MISCREG_PERF_EVT_CTR3),
129  MsrVal(0xC0010010, MISCREG_SYSCFG),
130  MsrVal(0xC0010016, MISCREG_IORR_BASE0),
131  MsrVal(0xC0010017, MISCREG_IORR_BASE1),
132  MsrVal(0xC0010018, MISCREG_IORR_MASK0),
133  MsrVal(0xC0010019, MISCREG_IORR_MASK1),
134  MsrVal(0xC001001A, MISCREG_TOP_MEM),
135  MsrVal(0xC001001D, MISCREG_TOP_MEM2),
136  MsrVal(0xC0010114, MISCREG_VM_CR),
137  MsrVal(0xC0010115, MISCREG_IGNNE),
138  MsrVal(0xC0010116, MISCREG_SMM_CTL),
139  MsrVal(0xC0010117, MISCREG_VM_HSAVE_PA)
140 };
141 
142 static const unsigned msrMapSize = sizeof(msrMapData) / sizeof(msrMapData[0]);
143 
145 
146 bool
148 {
149  MsrMap::const_iterator it(msrMap.find(addr));
150  if (it == msrMap.end()) {
151  return false;
152  } else {
153  regNum = it->second;
154  return true;
155  }
156 }
157 
158 } // namespace X86ISA
X86ISA::MISCREG_MTRR_PHYS_BASE_6
@ MISCREG_MTRR_PHYS_BASE_6
Definition: misc.hh:169
X86ISA::MISCREG_SMM_CTL
@ MISCREG_SMM_CTL
Definition: misc.hh:288
X86ISA::MISCREG_MTRR_FIX_4K_D8000
@ MISCREG_MTRR_FIX_4K_D8000
Definition: misc.hh:190
X86ISA::MISCREG_IORR_BASE0
@ MISCREG_IORR_BASE0
Definition: misc.hh:274
X86ISA::MISCREG_MCG_CAP
@ MISCREG_MCG_CAP
Definition: misc.hh:151
X86ISA::MISCREG_PERF_EVT_CTR2
@ MISCREG_PERF_EVT_CTR2
Definition: misc.hh:267
X86ISA::MISCREG_MC7_ADDR
@ MISCREG_MC7_ADDR
Definition: misc.hh:230
X86ISA::MISCREG_APIC_BASE
@ MISCREG_APIC_BASE
Definition: misc.hh:393
X86ISA::MISCREG_GS_BASE
@ MISCREG_GS_BASE
Definition: misc.hh:317
X86ISA::MISCREG_MTRRCAP
@ MISCREG_MTRRCAP
Definition: misc.hh:145
X86ISA::MISCREG_MC2_MISC
@ MISCREG_MC2_MISC
Definition: misc.hh:236
X86ISA::MISCREG_MTRR_PHYS_MASK_4
@ MISCREG_MTRR_PHYS_MASK_4
Definition: misc.hh:178
X86ISA::MISCREG_MC4_MISC
@ MISCREG_MC4_MISC
Definition: misc.hh:238
X86ISA::MISCREG_LAST_EXCEPTION_FROM_IP
@ MISCREG_LAST_EXCEPTION_FROM_IP
Definition: misc.hh:159
X86ISA::MISCREG_TOP_MEM2
@ MISCREG_TOP_MEM2
Definition: misc.hh:284
X86ISA::MISCREG_MCG_CTL
@ MISCREG_MCG_CTL
Definition: misc.hh:153
X86ISA::MISCREG_MC7_STATUS
@ MISCREG_MC7_STATUS
Definition: misc.hh:219
X86ISA::MISCREG_MTRR_PHYS_MASK_3
@ MISCREG_MTRR_PHYS_MASK_3
Definition: misc.hh:177
X86ISA::MISCREG_MTRR_FIX_16K_A0000
@ MISCREG_MTRR_FIX_16K_A0000
Definition: misc.hh:186
X86ISA::MISCREG_PERF_EVT_SEL3
@ MISCREG_PERF_EVT_SEL3
Definition: misc.hh:261
X86ISA::MISCREG_PERF_EVT_SEL2
@ MISCREG_PERF_EVT_SEL2
Definition: misc.hh:260
X86ISA::MISCREG_SYSENTER_CS
@ MISCREG_SYSENTER_CS
Definition: misc.hh:147
X86ISA::MISCREG_IGNNE
@ MISCREG_IGNNE
Definition: misc.hh:287
X86ISA::MISCREG_VM_HSAVE_PA
@ MISCREG_VM_HSAVE_PA
Definition: misc.hh:289
X86ISA::MISCREG_MTRR_PHYS_BASE_3
@ MISCREG_MTRR_PHYS_BASE_3
Definition: misc.hh:166
X86ISA::MISCREG_MTRR_PHYS_BASE_0
@ MISCREG_MTRR_PHYS_BASE_0
Definition: misc.hh:163
X86ISA::MISCREG_DEF_TYPE
@ MISCREG_DEF_TYPE
Definition: misc.hh:198
X86ISA::MISCREG_CSTAR
@ MISCREG_CSTAR
Definition: misc.hh:249
X86ISA::MISCREG_EFER
@ MISCREG_EFER
Definition: misc.hh:245
X86ISA::MISCREG_PERF_EVT_CTR3
@ MISCREG_PERF_EVT_CTR3
Definition: misc.hh:268
X86ISA::MISCREG_MTRR_PHYS_MASK_7
@ MISCREG_MTRR_PHYS_MASK_7
Definition: misc.hh:181
X86ISA::MISCREG_MTRR_PHYS_MASK_2
@ MISCREG_MTRR_PHYS_MASK_2
Definition: misc.hh:176
X86ISA::MISCREG_PERF_EVT_SEL1
@ MISCREG_PERF_EVT_SEL1
Definition: misc.hh:259
X86ISA::msrAddrToIndex
bool msrAddrToIndex(MiscRegIndex &regNum, Addr addr)
Find and return the misc reg corresponding to an MSR address.
Definition: msr.cc:147
X86ISA::MISCREG_LAST_BRANCH_FROM_IP
@ MISCREG_LAST_BRANCH_FROM_IP
Definition: misc.hh:157
X86ISA::MISCREG_MC5_STATUS
@ MISCREG_MC5_STATUS
Definition: misc.hh:217
X86ISA::MISCREG_MTRR_FIX_4K_D0000
@ MISCREG_MTRR_FIX_4K_D0000
Definition: misc.hh:189
X86ISA::MISCREG_MC3_CTL
@ MISCREG_MC3_CTL
Definition: misc.hh:204
X86ISA::MISCREG_MTRR_FIX_16K_80000
@ MISCREG_MTRR_FIX_16K_80000
Definition: misc.hh:185
X86ISA::MISCREG_STAR
@ MISCREG_STAR
Definition: misc.hh:247
X86ISA::MISCREG_MTRR_PHYS_BASE_5
@ MISCREG_MTRR_PHYS_BASE_5
Definition: misc.hh:168
X86ISA::MISCREG_MC5_MISC
@ MISCREG_MC5_MISC
Definition: misc.hh:239
X86ISA::MISCREG_MCG_STATUS
@ MISCREG_MCG_STATUS
Definition: misc.hh:152
X86ISA::MISCREG_MTRR_PHYS_BASE_7
@ MISCREG_MTRR_PHYS_BASE_7
Definition: misc.hh:170
X86ISA::MISCREG_SYSENTER_EIP
@ MISCREG_SYSENTER_EIP
Definition: misc.hh:149
X86ISA::MISCREG_TSC_AUX
@ MISCREG_TSC_AUX
Definition: misc.hh:255
X86ISA::MISCREG_MC3_STATUS
@ MISCREG_MC3_STATUS
Definition: misc.hh:215
X86ISA::MISCREG_SYSENTER_ESP
@ MISCREG_SYSENTER_ESP
Definition: misc.hh:148
X86ISA::MISCREG_MC0_STATUS
@ MISCREG_MC0_STATUS
Definition: misc.hh:212
X86ISA::MISCREG_TOP_MEM
@ MISCREG_TOP_MEM
Definition: misc.hh:283
X86ISA::MISCREG_MC2_CTL
@ MISCREG_MC2_CTL
Definition: misc.hh:203
X86ISA::MISCREG_VM_CR
@ MISCREG_VM_CR
Definition: misc.hh:286
X86ISA::MISCREG_MTRR_FIX_4K_E8000
@ MISCREG_MTRR_FIX_4K_E8000
Definition: misc.hh:192
msr.hh
X86ISA::MISCREG_MTRR_FIX_64K_00000
@ MISCREG_MTRR_FIX_64K_00000
Definition: misc.hh:184
X86ISA::MISCREG_MC2_STATUS
@ MISCREG_MC2_STATUS
Definition: misc.hh:214
X86ISA::MISCREG_DEBUG_CTL_MSR
@ MISCREG_DEBUG_CTL_MSR
Definition: misc.hh:155
X86ISA::MISCREG_MTRR_PHYS_MASK_6
@ MISCREG_MTRR_PHYS_MASK_6
Definition: misc.hh:180
X86ISA::MISCREG_IORR_MASK1
@ MISCREG_IORR_MASK1
Definition: misc.hh:280
X86ISA::MISCREG_MC1_STATUS
@ MISCREG_MC1_STATUS
Definition: misc.hh:213
X86ISA::MISCREG_MC0_MISC
@ MISCREG_MC0_MISC
Definition: misc.hh:234
X86ISA::MISCREG_LAST_EXCEPTION_TO_IP
@ MISCREG_LAST_EXCEPTION_TO_IP
Definition: misc.hh:160
X86ISA::MISCREG_MTRR_FIX_4K_E0000
@ MISCREG_MTRR_FIX_4K_E0000
Definition: misc.hh:191
X86ISA::MISCREG_MC6_CTL
@ MISCREG_MC6_CTL
Definition: misc.hh:207
X86ISA::MISCREG_MC5_ADDR
@ MISCREG_MC5_ADDR
Definition: misc.hh:228
X86ISA::MISCREG_PERF_EVT_CTR1
@ MISCREG_PERF_EVT_CTR1
Definition: misc.hh:266
X86ISA::MISCREG_MC7_CTL
@ MISCREG_MC7_CTL
Definition: misc.hh:208
X86ISA::MsrVal
MsrMap::value_type MsrVal
Definition: msr.cc:34
X86ISA::MISCREG_MTRR_FIX_4K_F8000
@ MISCREG_MTRR_FIX_4K_F8000
Definition: misc.hh:194
X86ISA
This is exposed globally, independent of the ISA.
Definition: acpi.hh:55
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
X86ISA::MISCREG_SF_MASK
@ MISCREG_SF_MASK
Definition: misc.hh:251
X86ISA::MISCREG_MTRR_FIX_4K_C0000
@ MISCREG_MTRR_FIX_4K_C0000
Definition: misc.hh:187
X86ISA::msrMapSize
static const unsigned msrMapSize
Definition: msr.cc:142
X86ISA::MISCREG_LSTAR
@ MISCREG_LSTAR
Definition: misc.hh:248
X86ISA::MISCREG_MC6_MISC
@ MISCREG_MC6_MISC
Definition: misc.hh:240
X86ISA::MISCREG_MTRR_FIX_4K_F0000
@ MISCREG_MTRR_FIX_4K_F0000
Definition: misc.hh:193
X86ISA::MISCREG_MC4_STATUS
@ MISCREG_MC4_STATUS
Definition: misc.hh:216
X86ISA::MISCREG_SYSCFG
@ MISCREG_SYSCFG
Definition: misc.hh:271
X86ISA::MISCREG_MC3_ADDR
@ MISCREG_MC3_ADDR
Definition: misc.hh:226
X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:79
X86ISA::MISCREG_MC5_CTL
@ MISCREG_MC5_CTL
Definition: misc.hh:206
X86ISA::MISCREG_MC4_ADDR
@ MISCREG_MC4_ADDR
Definition: misc.hh:227
X86ISA::MISCREG_MC6_ADDR
@ MISCREG_MC6_ADDR
Definition: misc.hh:229
X86ISA::MISCREG_MC0_ADDR
@ MISCREG_MC0_ADDR
Definition: misc.hh:223
X86ISA::MISCREG_MTRR_FIX_4K_C8000
@ MISCREG_MTRR_FIX_4K_C8000
Definition: misc.hh:188
X86ISA::MsrMap
std::unordered_map< Addr, MiscRegIndex > MsrMap
Definition: msr.hh:40
X86ISA::MISCREG_MC3_MISC
@ MISCREG_MC3_MISC
Definition: misc.hh:237
X86ISA::MISCREG_MC1_ADDR
@ MISCREG_MC1_ADDR
Definition: misc.hh:224
X86ISA::MISCREG_MC7_MISC
@ MISCREG_MC7_MISC
Definition: misc.hh:241
X86ISA::MISCREG_MC0_CTL
@ MISCREG_MC0_CTL
Definition: misc.hh:201
X86ISA::MISCREG_PERF_EVT_SEL0
@ MISCREG_PERF_EVT_SEL0
Definition: misc.hh:258
X86ISA::MISCREG_MTRR_PHYS_BASE_1
@ MISCREG_MTRR_PHYS_BASE_1
Definition: misc.hh:164
X86ISA::MISCREG_LAST_BRANCH_TO_IP
@ MISCREG_LAST_BRANCH_TO_IP
Definition: misc.hh:158
X86ISA::MISCREG_IORR_MASK0
@ MISCREG_IORR_MASK0
Definition: misc.hh:279
X86ISA::MISCREG_IORR_BASE1
@ MISCREG_IORR_BASE1
Definition: misc.hh:275
X86ISA::MISCREG_PERF_EVT_CTR0
@ MISCREG_PERF_EVT_CTR0
Definition: misc.hh:265
X86ISA::MISCREG_MC1_MISC
@ MISCREG_MC1_MISC
Definition: misc.hh:235
X86ISA::MISCREG_PAT
@ MISCREG_PAT
Definition: misc.hh:196
X86ISA::MISCREG_MTRR_PHYS_BASE_4
@ MISCREG_MTRR_PHYS_BASE_4
Definition: misc.hh:167
X86ISA::MISCREG_MC1_CTL
@ MISCREG_MC1_CTL
Definition: misc.hh:202
X86ISA::MISCREG_MTRR_PHYS_MASK_1
@ MISCREG_MTRR_PHYS_MASK_1
Definition: misc.hh:175
X86ISA::MISCREG_KERNEL_GS_BASE
@ MISCREG_KERNEL_GS_BASE
Definition: misc.hh:253
X86ISA::MISCREG_MTRR_PHYS_MASK_0
@ MISCREG_MTRR_PHYS_MASK_0
Definition: misc.hh:174
X86ISA::MISCREG_MC6_STATUS
@ MISCREG_MC6_STATUS
Definition: misc.hh:218
X86ISA::msrMap
const MsrMap msrMap
Map between MSR addresses and their corresponding misc registers.
X86ISA::msrMapData
const MsrMap::value_type msrMapData[]
Definition: msr.cc:36
X86ISA::MISCREG_FS_BASE
@ MISCREG_FS_BASE
Definition: misc.hh:316
X86ISA::MISCREG_MTRR_PHYS_BASE_2
@ MISCREG_MTRR_PHYS_BASE_2
Definition: misc.hh:165
X86ISA::MISCREG_TSC
@ MISCREG_TSC
Definition: misc.hh:143
X86ISA::MISCREG_MC2_ADDR
@ MISCREG_MC2_ADDR
Definition: misc.hh:225
X86ISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:100
X86ISA::MISCREG_MC4_CTL
@ MISCREG_MC4_CTL
Definition: misc.hh:205
X86ISA::MISCREG_MTRR_PHYS_MASK_5
@ MISCREG_MTRR_PHYS_MASK_5
Definition: misc.hh:179

Generated on Wed Sep 30 2020 14:02:07 for gem5 by doxygen 1.8.17