gem5
v20.1.0.0
arch
riscv
bare_metal
fs_workload.hh
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/*
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* Copyright (c) 2018 TU Dresden
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* All rights reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_RISCV_BARE_METAL_SYSTEM_HH__
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#define __ARCH_RISCV_BARE_METAL_SYSTEM_HH__
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#include "
arch/riscv/fs_workload.hh
"
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#include "params/RiscvBareMetal.hh"
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namespace
RiscvISA
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{
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class
BareMetal
:
public
RiscvISA::FsWorkload
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{
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protected
:
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Loader::ObjectFile
*
bootloader
;
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Loader::SymbolTable
bootloaderSymtab
;
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public
:
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typedef
RiscvBareMetalParams
Params
;
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BareMetal
(
Params
*
p
);
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~BareMetal
();
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void
initState
()
override
;
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Loader::Arch
getArch
()
const override
{
return
bootloader
->
getArch
(); }
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const
Loader::SymbolTable
&
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symtab
(
ThreadContext
*tc)
override
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{
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return
bootloaderSymtab
;
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}
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bool
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insertSymbol
(
const
Loader::Symbol
&symbol)
override
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{
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return
bootloaderSymtab
.
insert
(symbol);
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}
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};
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}
// namespace RiscvISA
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#endif // __ARCH_RISCV_BARE_METAL_FS_WORKLOAD_HH__
RiscvISA::BareMetal::~BareMetal
~BareMetal()
Definition:
fs_workload.cc:47
RiscvISA::FsWorkload
Definition:
fs_workload.hh:40
Loader::SymbolTable
Definition:
symtab.hh:59
RiscvISA::p
Bitfield< 0 > p
Definition:
pra_constants.hh:323
RiscvISA::BareMetal::symtab
const Loader::SymbolTable & symtab(ThreadContext *tc) override
Definition:
fs_workload.hh:53
RiscvISA
Definition:
fs_workload.cc:36
Loader::ObjectFile
Definition:
object_file.hh:70
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition:
thread_context.hh:88
RiscvISA::BareMetal::getArch
Loader::Arch getArch() const override
Definition:
fs_workload.hh:51
RiscvISA::BareMetal::insertSymbol
bool insertSymbol(const Loader::Symbol &symbol) override
Definition:
fs_workload.hh:58
RiscvISA::BareMetal::bootloader
Loader::ObjectFile * bootloader
Definition:
fs_workload.hh:41
RiscvISA::BareMetal
Definition:
fs_workload.hh:38
fs_workload.hh
Loader::Arch
Arch
Definition:
object_file.hh:44
Loader::ObjectFile::getArch
Arch getArch() const
Definition:
object_file.hh:99
Loader::Symbol
Definition:
symtab.hh:46
RiscvISA::BareMetal::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition:
fs_workload.cc:53
RiscvISA::BareMetal::bootloaderSymtab
Loader::SymbolTable bootloaderSymtab
Definition:
fs_workload.hh:42
Loader::SymbolTable::insert
bool insert(const Symbol &symbol)
Definition:
symtab.cc:58
RiscvISA::BareMetal::Params
RiscvBareMetalParams Params
Definition:
fs_workload.hh:45
RiscvISA::BareMetal::BareMetal
BareMetal(Params *p)
Definition:
fs_workload.cc:39
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