decoder.hh

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/*
 * Copyright (c) 2012 Google
 * Copyright (c) 2017 The University of Virginia
 * All rights reserved.
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
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 * neither the name of the copyright holders nor the names of its
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 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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#ifndef __ARCH_RISCV_DECODER_HH__
#define __ARCH_RISCV_DECODER_HH__
 
#include "arch/generic/decode_cache.hh"
#include "arch/generic/decoder.hh"
#include "arch/riscv/isa_traits.hh"
#include "arch/riscv/types.hh"
#include "base/logging.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "debug/Decode.hh"
 
namespace RiscvISA
{
 
class ISA;
class Decoder : public InstDecoder
{
  private:
    DecodeCache::InstMap<ExtMachInst> instMap;
    bool aligned;
    bool mid;
    bool more;
 
  protected:
    //The extended machine instruction being generated
    ExtMachInst emi;
    bool instDone;
 
  public:
    Decoder(ISA* isa=nullptr) { reset(); }
 
    void process() {}
    void reset();
 
    inline bool compressed(ExtMachInst inst) { return (inst & 0x3) < 0x3; }
 
    //Use this to give data to the decoder. This should be used
    //when there is control flow.
    void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
 
    bool needMoreBytes() { return more; }
    bool instReady() { return instDone; }
    void takeOverFrom(Decoder *old) {}
 
    StaticInstPtr decodeInst(ExtMachInst mach_inst);
 
    StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
 
    StaticInstPtr decode(RiscvISA::PCState &nextPC);
};
 
} // namespace RiscvISA
 
#endif // __ARCH_RISCV_DECODER_HH__