gem5  v20.1.0.0
isa.hh
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1 /*
2  * Copyright (c) 2009 The Regents of The University of Michigan
3  * Copyright (c) 2009 The University of Edinburgh
4  * Copyright (c) 2014 Sven Karlsson
5  * Copyright (c) 2016 RISC-V Foundation
6  * Copyright (c) 2016 The University of Virginia
7  * Copyright (c) 2020 Barkhausen Institut
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33 
34 #ifndef __ARCH_RISCV_ISA_HH__
35 #define __ARCH_RISCV_ISA_HH__
36 
37 #include <map>
38 #include <string>
39 
40 #include "arch/generic/isa.hh"
41 #include "arch/riscv/registers.hh"
42 #include "arch/riscv/types.hh"
43 #include "base/bitfield.hh"
44 #include "base/logging.hh"
45 #include "cpu/reg_class.hh"
46 #include "sim/sim_object.hh"
47 
48 struct RiscvISAParams;
49 class ThreadContext;
50 class Checkpoint;
51 class EventManager;
52 
53 namespace RiscvISA
54 {
55 
57 {
58  PRV_U = 0,
59  PRV_S = 1,
60  PRV_M = 3
61 };
62 
64 {
65  OFF = 0,
66  INITIAL = 1,
67  CLEAN = 2,
68  DIRTY = 3,
69 };
70 
71 class ISA : public BaseISA
72 {
73  protected:
75 
76  bool hpmCounterEnabled(int counter) const;
77 
78  public:
79  typedef RiscvISAParams Params;
80 
81  void clear();
82 
83  public:
84  RegVal readMiscRegNoEffect(int misc_reg) const;
85  RegVal readMiscReg(int misc_reg);
86  void setMiscRegNoEffect(int misc_reg, RegVal val);
87  void setMiscReg(int misc_reg, RegVal val);
88 
89  RegId flattenRegId(const RegId &regId) const { return regId; }
90  int flattenIntIndex(int reg) const { return reg; }
91  int flattenFloatIndex(int reg) const { return reg; }
92  int flattenVecIndex(int reg) const { return reg; }
93  int flattenVecElemIndex(int reg) const { return reg; }
94  int flattenVecPredIndex(int reg) const { return reg; }
95  int flattenCCIndex(int reg) const { return reg; }
96  int flattenMiscIndex(int reg) const { return reg; }
97 
98  void serialize(CheckpointOut &cp) const;
100 
101  const Params *params() const;
102 
103  ISA(Params *p);
104 };
105 
106 } // namespace RiscvISA
107 
108 #endif // __ARCH_RISCV_ISA_HH__
RiscvISA::ISA::flattenVecElemIndex
int flattenVecElemIndex(int reg) const
Definition: isa.hh:93
RiscvISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg)
Definition: isa.cc:246
RiscvISA::PRV_S
@ PRV_S
Definition: isa.hh:59
RiscvISA::ISA::Params
RiscvISAParams Params
Definition: isa.hh:79
RiscvISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
RiscvISA::FPUStatus
FPUStatus
Definition: isa.hh:63
RiscvISA::ISA::clear
void clear()
Definition: isa.cc:191
RiscvISA::ISA::hpmCounterEnabled
bool hpmCounterEnabled(int counter) const
Definition: isa.cc:210
std::vector< RegVal >
RiscvISA::ISA::unserialize
void unserialize(CheckpointIn &cp)
Unserialize an object.
Definition: isa.cc:407
X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:87
RiscvISA::OFF
@ OFF
Definition: isa.hh:65
RiscvISA::ISA::ISA
ISA(Params *p)
Definition: isa.cc:179
RiscvISA::ISA::params
const Params * params() const
Definition: isa.cc:186
RiscvISA::ISA::serialize
void serialize(CheckpointOut &cp) const
Serialize an object.
Definition: isa.cc:400
RiscvISA
Definition: fs_workload.cc:36
RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:75
RiscvISA::ISA::flattenVecIndex
int flattenVecIndex(int reg) const
Definition: isa.hh:92
cp
Definition: cprintf.cc:40
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
bitfield.hh
sim_object.hh
RiscvISA::ISA::flattenVecPredIndex
int flattenVecPredIndex(int reg) const
Definition: isa.hh:94
types.hh
RiscvISA::ISA::flattenIntIndex
int flattenIntIndex(int reg) const
Definition: isa.hh:90
RiscvISA::PrivilegeMode
PrivilegeMode
Definition: isa.hh:56
RiscvISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val)
Definition: isa.cc:333
RiscvISA::PRV_U
@ PRV_U
Definition: isa.hh:58
RiscvISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val)
Definition: isa.cc:321
RiscvISA::CLEAN
@ CLEAN
Definition: isa.hh:67
X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
RiscvISA::ISA::flattenFloatIndex
int flattenFloatIndex(int reg) const
Definition: isa.hh:91
RiscvISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: isa.cc:233
registers.hh
isa.hh
RiscvISA::ISA::miscRegFile
std::vector< RegVal > miscRegFile
Definition: isa.hh:74
RiscvISA::ISA::flattenCCIndex
int flattenCCIndex(int reg) const
Definition: isa.hh:95
RiscvISA::ISA
Definition: isa.hh:71
RiscvISA::ISA::flattenMiscIndex
int flattenMiscIndex(int reg) const
Definition: isa.hh:96
reg_class.hh
logging.hh
RiscvISA::ISA::flattenRegId
RegId flattenRegId(const RegId &regId) const
Definition: isa.hh:89
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:63
EventManager
Definition: eventq.hh:973
RiscvISA::DIRTY
@ DIRTY
Definition: isa.hh:68
RiscvISA::INITIAL
@ INITIAL
Definition: isa.hh:66
CheckpointIn
Definition: serialize.hh:67
RiscvISA::PRV_M
@ PRV_M
Definition: isa.hh:60
BaseISA
Definition: isa.hh:47
RegVal
uint64_t RegVal
Definition: types.hh:168

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