gem5
v20.1.0.0
arch
riscv
insts
pseudo.hh
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/*
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* Copyright (c) 2020 Barkhausen Institut
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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*/
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#ifndef __ARCH_RISCV_INSTS_PSEUDO_HH__
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#define __ARCH_RISCV_INSTS_PSEUDO_HH__
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#include <string>
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#include "
arch/riscv/insts/static_inst.hh
"
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namespace
RiscvISA
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{
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class
PseudoOp
:
public
RiscvStaticInst
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{
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protected
:
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using
RiscvStaticInst::RiscvStaticInst;
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std::string
generateDisassembly
(
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Addr
pc
,
const
Loader::SymbolTable
*symtab)
const override
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{
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return
mnemonic
;
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}
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};
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}
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#endif // __ARCH_RISCV_INSTS_PSEUDO_HH__
RiscvISA::pc
Bitfield< 4 > pc
Definition:
pra_constants.hh:240
Loader::SymbolTable
Definition:
symtab.hh:59
RiscvISA
Definition:
fs_workload.cc:36
RiscvISA::PseudoOp
Definition:
pseudo.hh:39
StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition:
static_inst.hh:258
static_inst.hh
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition:
types.hh:142
RiscvISA::RiscvStaticInst
Base class for all RISC-V static instructions.
Definition:
static_inst.hh:46
RiscvISA::PseudoOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition:
pseudo.hh:44
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