gem5  v20.1.0.0
pseudo.hh
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28 
29 #ifndef __ARCH_RISCV_INSTS_PSEUDO_HH__
30 #define __ARCH_RISCV_INSTS_PSEUDO_HH__
31 
32 #include <string>
33 
35 
36 namespace RiscvISA
37 {
38 
39 class PseudoOp : public RiscvStaticInst
40 {
41  protected:
42  using RiscvStaticInst::RiscvStaticInst;
43 
44  std::string generateDisassembly(
45  Addr pc, const Loader::SymbolTable *symtab) const override
46  {
47  return mnemonic;
48  }
49 };
50 
51 }
52 
53 #endif // __ARCH_RISCV_INSTS_PSEUDO_HH__
RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
Loader::SymbolTable
Definition: symtab.hh:59
RiscvISA
Definition: fs_workload.cc:36
RiscvISA::PseudoOp
Definition: pseudo.hh:39
StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:258
static_inst.hh
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
RiscvISA::RiscvStaticInst
Base class for all RISC-V static instructions.
Definition: static_inst.hh:46
RiscvISA::PseudoOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pseudo.hh:44

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