gem5
v20.1.0.0
systemc
tests
systemc
misc
sim_tests
srlatch
testbench.h
Go to the documentation of this file.
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing
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permissions and limitations under the License.
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*****************************************************************************/
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/*****************************************************************************
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testbench.h --
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Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
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*****************************************************************************/
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/*****************************************************************************
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MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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changes you are making here.
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Name, Affiliation, Date:
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Description of Modification:
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*****************************************************************************/
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/* Filename testbench.h */
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/* This is the interface file for synchronous process 'testbench' */
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#include "systemc.h"
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SC_MODULE
(
testbench
)
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{
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SC_HAS_PROCESS
(
testbench
);
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sc_in_clk
clk;
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sc_in<bool>
q
;
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sc_in<bool> qp;
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sc_out<bool>
s
;
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sc_out<bool>
r
;
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// Constructor
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testbench
( sc_module_name NAME,
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sc_clock& CLK,
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sc_signal<bool>& Q,
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sc_signal<bool>& QP,
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sc_signal<bool>& S,
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sc_signal<bool>&
R
)
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{
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clk(CLK);
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q
(Q); qp(QP);
s
(S);
r
(
R
);
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SC_CTHREAD
( entry, clk.pos() );
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}
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// Process functionality in member function below
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void
entry();
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};
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ArmISA::q
Bitfield< 27 > q
Definition:
miscregs_types.hh:52
testbench
Definition:
tb.h:50
MipsISA::r
r
Definition:
pra_constants.hh:95
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition:
sc_clock.hh:116
X86ISA::R
R
Definition:
int.hh:49
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition:
sc_module.hh:297
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition:
sc_module.hh:319
SC_MODULE
SC_MODULE(testbench)
Definition:
testbench.h:43
ArmISA::s
Bitfield< 4 > s
Definition:
miscregs_types.hh:556
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