gem5  v20.1.0.0
testbench.h
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21 
22  testbench.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
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29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
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33  Name, Affiliation, Date:
34  Description of Modification:
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36  *****************************************************************************/
37 
38 /* Filename testbench.h */
39 /* This is the interface file for synchronous process 'testbench' */
40 
41 #include "systemc.h"
42 
44 {
46 
47  sc_in_clk clk;
48 
49  sc_in<bool> q;
50  sc_in<bool> qp;
51  sc_out<bool> s;
52  sc_out<bool> r;
53 
54  // Constructor
55  testbench( sc_module_name NAME,
56  sc_clock& CLK,
57  sc_signal<bool>& Q,
58  sc_signal<bool>& QP,
59  sc_signal<bool>& S,
60  sc_signal<bool>& R )
61  {
62  clk(CLK);
63  q(Q); qp(QP); s(S); r(R);
64  SC_CTHREAD( entry, clk.pos() );
65  }
66 
67  // Process functionality in member function below
68  void entry();
69 };
70 
ArmISA::q
Bitfield< 27 > q
Definition: miscregs_types.hh:52
testbench
Definition: tb.h:50
MipsISA::r
r
Definition: pra_constants.hh:95
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
X86ISA::R
R
Definition: int.hh:49
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:297
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:319
SC_MODULE
SC_MODULE(testbench)
Definition: testbench.h:43
ArmISA::s
Bitfield< 4 > s
Definition: miscregs_types.hh:556

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