gem5  v20.1.0.0
decoder.hh
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28 
29 #ifndef __ARCH_SPARC_DECODER_HH__
30 #define __ARCH_SPARC_DECODER_HH__
31 
33 #include "arch/generic/decoder.hh"
34 #include "arch/sparc/registers.hh"
35 #include "arch/types.hh"
36 #include "cpu/static_inst.hh"
37 
38 namespace SparcISA
39 {
40 
41 class ISA;
42 class Decoder : public InstDecoder
43 {
44  protected:
45  // The extended machine instruction being generated
47  bool instDone;
49 
50  public:
51  Decoder(ISA* isa = nullptr) : instDone(false), asi(0)
52  {}
53 
54  void process() {}
55 
56  void
58  {
59  instDone = false;
60  }
61 
62  // Use this to give data to the predecoder. This should be used
63  // when there is control flow.
64  void
65  moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
66  {
67  emi = betoh(inst);
68  // The I bit, bit 13, is used to figure out where the ASI
69  // should come from. Use that in the ExtMachInst. This is
70  // slightly redundant, but it removes the need to put a condition
71  // into all the execute functions
72  if (emi & (1 << 13)) {
73  emi |= (static_cast<ExtMachInst>(
74  asi << (sizeof(MachInst) * 8)));
75  } else {
76  emi |= (static_cast<ExtMachInst>(bits(emi, 12, 5))
77  << (sizeof(MachInst) * 8));
78  }
79  instDone = true;
80  }
81 
82  bool
84  {
85  return true;
86  }
87 
88  bool
90  {
91  return instDone;
92  }
93 
94  void
96  {
97  asi = _asi;
98  }
99 
100  void takeOverFrom(Decoder *old) {}
101 
102  protected:
105 
106  public:
108 
114  {
115  return defaultCache.decode(this, mach_inst, addr);
116  }
117 
120  {
121  if (!instDone)
122  return NULL;
123  instDone = false;
124  return decode(emi, nextPC.instAddr());
125  }
126 };
127 
128 } // namespace SparcISA
129 
130 #endif // __ARCH_SPARC_DECODER_HH__
SparcISA::MachInst
uint32_t MachInst
Definition: types.hh:38
SparcISA::Decoder::moreBytes
void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
Definition: decoder.hh:65
SparcISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:39
SparcISA::Decoder::reset
void reset()
Definition: decoder.hh:57
SparcISA::Decoder::takeOverFrom
void takeOverFrom(Decoder *old)
Definition: decoder.hh:100
SparcISA::Decoder::asi
RegVal asi
Definition: decoder.hh:48
GenericISA::BasicDecodeCache::decode
StaticInstPtr decode(TheISA::Decoder *const decoder, TheISA::ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decode_cache.cc:40
decode_cache.hh
SparcISA::Decoder::emi
ExtMachInst emi
Definition: decoder.hh:46
SparcISA::Decoder::needMoreBytes
bool needMoreBytes()
Definition: decoder.hh:83
GenericISA::DelaySlotUPCState
Definition: types.hh:391
SparcISA::Decoder::defaultCache
static GenericISA::BasicDecodeCache defaultCache
A cache of decoded instruction objects.
Definition: decoder.hh:104
GenericISA::BasicDecodeCache
Definition: decode_cache.hh:45
SparcISA::Decoder::Decoder
Decoder(ISA *isa=nullptr)
Definition: decoder.hh:51
SparcISA
Definition: asi.cc:31
decoder.hh
SparcISA::Decoder::decode
StaticInstPtr decode(SparcISA::PCState &nextPC)
Definition: decoder.hh:119
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
SparcISA::Decoder::instDone
bool instDone
Definition: decoder.hh:47
SparcISA::Decoder
Definition: decoder.hh:42
SparcISA::Decoder::process
void process()
Definition: decoder.hh:54
static_inst.hh
GenericISA::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address the bytes of this instruction came from.
Definition: types.hh:80
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
betoh
T betoh(T value)
Definition: byteswap.hh:143
SparcISA::Decoder::setContext
void setContext(RegVal _asi)
Definition: decoder.hh:95
addr
ip6_addr_t addr
Definition: inet.hh:423
InstDecoder
Definition: decoder.hh:34
registers.hh
RefCountingPtr< StaticInst >
SparcISA::ISA
Definition: isa.hh:48
SparcISA::Decoder::decode
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decoder.hh:113
SparcISA::Decoder::instReady
bool instReady()
Definition: decoder.hh:89
RegVal
uint64_t RegVal
Definition: types.hh:168
SparcISA::Decoder::decodeInst
StaticInstPtr decodeInst(ExtMachInst mach_inst)
bits
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:75

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