tlbi_op.cc

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/*
 * Copyright (c) 2018-2019 ARM Limited
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 * met: redistributions of source code must retain the above copyright
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#include "arch/arm/tlbi_op.hh"
 
#include "arch/arm/tlb.hh"
#include "cpu/checker/cpu.hh"
 
namespace ArmISA {
 
void
TLBIALL::operator()(ThreadContext* tc)
{
    HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
    bool in_host = (hcr.tge == 1 && hcr.e2h == 1);
    getITBPtr(tc)->flushAllSecurity(secureLookup, targetEL, in_host);
    getDTBPtr(tc)->flushAllSecurity(secureLookup, targetEL, in_host);
 
    // If CheckerCPU is connected, need to notify it of a flush
    CheckerCPU *checker = tc->getCheckerCpuPtr();
    if (checker) {
        getITBPtr(checker)->flushAllSecurity(secureLookup,
                                               targetEL, in_host);
        getDTBPtr(checker)->flushAllSecurity(secureLookup,
                                               targetEL, in_host);
    }
}
 
void
ITLBIALL::operator()(ThreadContext* tc)
{
    getITBPtr(tc)->flushAllSecurity(secureLookup, targetEL);
}
 
void
DTLBIALL::operator()(ThreadContext* tc)
{
    getDTBPtr(tc)->flushAllSecurity(secureLookup, targetEL);
}
 
void
TLBIASID::operator()(ThreadContext* tc)
{
    HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
    bool in_host = (hcr.tge == 1 && hcr.e2h == 1);
    getITBPtr(tc)->flushAsid(asid, secureLookup, targetEL, in_host);
    getDTBPtr(tc)->flushAsid(asid, secureLookup, targetEL, in_host);
    CheckerCPU *checker = tc->getCheckerCpuPtr();
    if (checker) {
        getITBPtr(checker)->flushAsid(asid, secureLookup, targetEL, in_host);
        getDTBPtr(checker)->flushAsid(asid, secureLookup, targetEL, in_host);
    }
}
 
void
ITLBIASID::operator()(ThreadContext* tc)
{
    getITBPtr(tc)->flushAsid(asid, secureLookup, targetEL);
}
 
void
DTLBIASID::operator()(ThreadContext* tc)
{
    getDTBPtr(tc)->flushAsid(asid, secureLookup, targetEL);
}
 
void
TLBIALLN::operator()(ThreadContext* tc)
{
    getITBPtr(tc)->flushAllNs(targetEL);
    getDTBPtr(tc)->flushAllNs(targetEL);
 
    CheckerCPU *checker = tc->getCheckerCpuPtr();
    if (checker) {
        getITBPtr(checker)->flushAllNs(targetEL);
        getDTBPtr(checker)->flushAllNs(targetEL);
    }
}
 
void
TLBIMVAA::operator()(ThreadContext* tc)
{
    HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
    bool in_host = (hcr.tge == 1 && hcr.e2h == 1);
    getITBPtr(tc)->flushMva(addr, secureLookup, targetEL, in_host);
    getDTBPtr(tc)->flushMva(addr, secureLookup, targetEL, in_host);
 
    CheckerCPU *checker = tc->getCheckerCpuPtr();
    if (checker) {
        getITBPtr(checker)->flushMva(addr, secureLookup, targetEL, in_host);
        getDTBPtr(checker)->flushMva(addr, secureLookup, targetEL, in_host);
    }
}
 
void
TLBIMVA::operator()(ThreadContext* tc)
{
    HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
    bool in_host = (hcr.tge == 1 && hcr.e2h == 1);
    getITBPtr(tc)->flushMvaAsid(addr, asid,
                                  secureLookup, targetEL, in_host);
    getDTBPtr(tc)->flushMvaAsid(addr, asid,
                                  secureLookup, targetEL, in_host);
 
    CheckerCPU *checker = tc->getCheckerCpuPtr();
    if (checker) {
        getITBPtr(checker)->flushMvaAsid(
            addr, asid, secureLookup, targetEL, in_host);
        getDTBPtr(checker)->flushMvaAsid(
            addr, asid, secureLookup, targetEL, in_host);
    }
}
 
void
ITLBIMVA::operator()(ThreadContext* tc)
{
    getITBPtr(tc)->flushMvaAsid(
        addr, asid, secureLookup, targetEL);
}
 
void
DTLBIMVA::operator()(ThreadContext* tc)
{
    getDTBPtr(tc)->flushMvaAsid(
        addr, asid, secureLookup, targetEL);
}
 
void
TLBIIPA::operator()(ThreadContext* tc)
{
    getITBPtr(tc)->flushIpaVmid(addr,
        secureLookup, targetEL);
    getDTBPtr(tc)->flushIpaVmid(addr,
        secureLookup, targetEL);
 
    CheckerCPU *checker = tc->getCheckerCpuPtr();
    if (checker) {
        getITBPtr(checker)->flushIpaVmid(addr,
            secureLookup, targetEL);
        getDTBPtr(checker)->flushIpaVmid(addr,
            secureLookup, targetEL);
    }
}
 
} // namespace ArmISA