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38 #ifndef __CPU_TRACE_TRACE_CPU_HH__
39 #define __CPU_TRACE_TRACE_CPU_HH__
45 #include <unordered_map>
47 #include "arch/registers.hh"
50 #include "debug/TraceCPUData.hh"
51 #include "debug/TraceCPUInst.hh"
52 #include "params/TraceCPU.hh"
53 #include "proto/inst_dep_record.pb.h"
54 #include "proto/packet.pb.h"
427 const std::string& trace_file)
536 const std::string& _name);
571 typedef ProtoMessage::InstDepRecord
Record;
593 typedef std::array<NodeSeqNum, TheISA::MaxInstSrcRegs>
RegDepArray;
826 const double time_multiplier);
856 const std::string& trace_file, TraceCPUParams *
params)
870 DPRINTF(TraceCPUData,
"Window size in the trace is %d.\n",
979 bool checkAndIssue(
const GraphNode* node_ptr,
bool first =
true);
1052 const std::string& _name);
1164 #endif // __CPU_TRACE_TRACE_CPU_HH__
void completeMemAccess(PacketPtr pkt)
When a load writeback is received, that is when the load completes, release the dependents on it.
const uint64_t progressMsgInterval
Interval of committed instructions specified by the user at which a progress info message is printed.
void schedIcacheNext()
This is the control flow that uses the functionality of the icacheGen to replay the trace.
The HardwareResource class models structures that hold the in-flight nodes.
void addDepsOnParent(GraphNode *new_node, T &dep_array, uint8_t &num_dep)
Iterate over the dependencies of a new node and add the new node to the list of dependents of the par...
void execute()
This is the main execute function which consumes nodes from the sorted readyList.
bool removeRobDep(NodeSeqNum rob_dep)
Remove completed instruction from order dependency array.
bool removeDepOnInst(NodeSeqNum done_seq_num)
Check for all dependencies on completed inst.
TraceStats(TraceCPU *trace)
void takeOverFrom(BaseCPU *oldCPU)
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
std::array< NodeSeqNum, maxRobDep > RobDepArray
Typedef for the array containing the ROB dependencies.
const uint16_t sizeROB
The size of the ROB used to throttle the max.
IcachePort icachePort
Port to connect to L1 instruction cache.
TraceCPU::TraceStats traceStats
Stats::Scalar numSendSucceeded
Stats::Scalar numSchedDcacheEvent
Stats::Scalar numSchedIcacheEvent
std::string typeToStr() const
Return string specifying the type of the node.
Tick init()
Called from TraceCPU init().
int16_t ThreadID
Thread index/ID type.
std::map< NodeSeqNum, NodeRobNum > inFlightNodes
A map from the sequence number to the ROB number of the in- flight nodes.
void addToSortedReadyList(NodeSeqNum seq_num, Tick exec_tick)
Add a ready node to the readyList.
Request::FlagsType flags
Potential request flags to use.
CountedExitEvent * execCompleteEvent
A CountedExitEvent which when serviced decrements the counter.
HardwareResource(uint16_t max_rob, uint16_t max_stores, uint16_t max_loads)
Constructor that initializes the sizes of the structures.
std::string genName
String to store the name of the FixedRetryGen.
void clearRobDep()
Initialize register dependency array to all zeroes.
uint64_t Tick
Tick count type.
bool oneTraceComplete
Set to true when one of the generators finishes replaying its trace.
TraceCPU & owner
Reference of the TraceCPU.
Port & getInstPort()
Used to get a reference to the icache port.
bool isSnooping() const
Required functionally.
Addr physAddr
The address for the request if any.
void schedDcacheNext()
This is the control flow that uses the functionality of the dcacheGen to replay the trace.
DcachePort(TraceCPU *_cpu)
Default constructor.
const RequestorID requestorId
RequestorID used for the requests being sent.
void checkAndSchedExitEvent()
This is called when either generator finishes executing from the trace.
bool awaitingResponse() const
Check if there are any outstanding requests, i.e.
IcachePort class that interfaces with L1 Instruction Cache.
InputStream trace
Input stream used for reading the input trace file.
NodeRobNum robNum
ROB occupancy number.
std::list< ReadyNode > readyList
List of nodes that are ready to execute.
Struct to store a ready-to-execute node and its execution tick.
DcachePort class that interfaces with L1 Data Cache.
FixedRetryGen(TraceCPU &_owner, const std::string &_name, RequestPort &_port, RequestorID requestor_id, const std::string &trace_file)
std::string genName
String to store the name of the FixedRetryGen.
Stats::Scalar numSendFailed
HardwareResource hwResource
Hardware resources required to contain in-flight nodes and to throttle issuing of new nodes when reso...
Stats::Scalar instLastTick
Last simulated tick by the FixedRetryGen.
FixedRetryGen icacheGen
Instance of FixedRetryGen to replay instruction read requests.
This struct stores a line in the trace file.
void adjustInitTraceOffset(Tick &offset)
Adjust traceOffset based on what TraceCPU init() determines on comparing the offsets in the fetch req...
bool traceComplete
Set to true when end of trace is reached.
NodeSeqNum seqNum
Instruction sequence number.
void recvTimingSnoopReq(PacketPtr pkt)
Required functionally but do nothing.
bool isStrictlyOrdered() const
Return true if node has a request which is strictly ordered.
RequestPort & port
Reference of the port to be used to issue memory requests.
Stats::Scalar numSendAttempted
Stats for instruction accesses replayed.
void exit()
Exit the FixedRetryGen.
This is a simple scalar statistic, like a counter.
const uint16_t sizeLoadBuffer
The size of load buffer.
bool isTraceComplete()
Returns the traceComplete variable which is set when end of the input trace file is reached.
uint16_t numInFlightStores
Number of ready stores for which request may or may not be sent.
int64_t Counter
Statistics counter type.
@ STRICT_ORDER
The request is required to be strictly ordered by CPU models and is non-speculative.
void wakeup(ThreadID tid=0)
uint64_t NodeRobNum
Node ROB number type.
FixedRetryGenStatGroup(Stats::Group *parent, const std::string &_name)
name is the extension to the name for these stats
void dcacheRetryRecvd()
When data cache port receives a retry, schedule event dcacheNextEvent.
RequestPort & port
Reference of the port to be used to issue memory requests.
Stats::Scalar numSendSucceeded
bool nextExecute()
Reads a line of the trace file.
Counter value() const
Return the current value of this stat as its base type.
TraceCPU & owner
Reference of the TraceCPU.
MemCmd cmd
Specifies if the request is to be a read or a write.
Stats::Scalar numRetrySucceeded
The elastic data memory request generator to read protobuf trace containing execution trace annotated...
void recvReqRetry()
Handle a retry signalled by the cache if data access failed in the first attempt.
bool recvTimingResp(PacketPtr pkt)
Receive the timing reponse and call dcacheRecvTimingResp() method of the dcacheGen to handle completi...
TraceCPU::ElasticDataGen::ElasticDataGenStatGroup elasticStats
TraceElement currElement
Store an element read from the trace to send as the next packet.
ProtoMessage::InstDepRecord::RecordType RecordType
bool recvTimingResp(PacketPtr pkt)
Receive the timing reponse and simply delete the packet since instruction fetch requests are issued a...
Request::Flags flags
Request flags if any.
bool execComplete
Set true when execution of trace is complete.
void clearRegDep()
Initialize register dependency array to all zeroes.
Tick tick
The time at which the request should be sent.
Ports are used to interface objects to each other.
bool removeRegDep(NodeSeqNum reg_dep)
Remove completed instruction from register dependency array.
Stats::Scalar numSOStores
void printReadyList()
Print readyList for debugging using debug flag TraceCPUData.
Generator to read protobuf trace containing memory requests at fixed timestamps, perform flow control...
std::vector< GraphNode * > dependents
A vector of nodes dependent (outgoing) on this node.
void recvFunctionalSnoop(PacketPtr pkt)
Required functionally but do nothing.
uint64_t compDelay
Computational delay.
TraceCPU(TraceCPUParams *params)
bool isAvailable(const GraphNode *new_node) const
Check if structures required to issue a node are free.
The struct GraphNode stores an instruction in the trace file.
Tick init()
Called from TraceCPU init().
uint64_t progressMsgThreshold
bool isStore() const
Is the node a store.
Stats::Scalar numSplitReqs
Counter totalInsts() const
This is a pure virtual function in BaseCPU.
bool readNextWindow()
Reads a line of the trace file.
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
const bool enableEarlyExit
Exit when any one Trace CPU completes its execution.
std::unordered_map< NodeSeqNum, GraphNode * > depGraph
Store the depGraph of GraphNodes.
EventFunctionWrapper icacheNextEvent
Event for the control flow method schedIcacheNext()
void schedDcacheNextEvent(Tick when)
Schedule event dcacheNextEvent at the given tick.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
bool isComp() const
Is the node a compute (non load/store) node.
const Params * params() const
const std::string name() const
Return port name (for DPRINTF).
void releaseStoreBuffer()
Release store buffer entry for a completed store.
IcachePort(TraceCPU *_cpu)
Default constructor.
void clear()
Make this element invalid.
RecordType type
Type of the node corresponding to the instruction modelled by it.
InputStream trace
Input stream used for reading the input trace file.
ProtoMessage::InstDepRecord Record
NodeRobNum oldestInFlightRobNum
The ROB number of the oldest in-flight node.
DcachePort dcachePort
Port to connect to L1 data cache.
uint8_t numRegDep
Number of register dependencies.
uint16_t numInFlightLoads
Number of ready loads for which request may or may not be sent.
std::array< NodeSeqNum, TheISA::MaxInstSrcRegs > RegDepArray
Typedef for the array containing the register dependencies.
Stats::Scalar numRetrySucceeded
bool send(Addr addr, unsigned size, const MemCmd &cmd, Request::FlagsType flags, Addr pc)
Creates a new request assigning the request parameters passed by the arguments.
uint32_t size
Size of request if any.
NodeSeqNum seqNum
The sequence number of the ready node.
Stats::Scalar dataLastTick
Tick when ElasticDataGen completes execution.
void dcacheRecvTimingResp(PacketPtr pkt)
When data cache port receives a response, this calls the dcache generator method handle to complete t...
ElasticDataGenStatGroup(Stats::Group *parent, const std::string &_name)
name is the extension to the name for these stats
uint8_t numRobDep
Number of order dependencies.
void release(const GraphNode *done_node)
Release appropriate structures for a completed node.
const std::string & name() const
Returns name of the FixedRetryGen instance.
void exit()
Exit the ElasticDataGen.
PacketPtr executeMemReq(GraphNode *node_ptr)
Creates a new request for a load or store assigning the request parameters.
TraceCPU::FixedRetryGen::FixedRetryGenStatGroup fixedStats
void occupy(const GraphNode *new_node)
Occupy appropriate structures for an issued node.
Stats::Scalar maxReadyListSize
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
ElasticDataGen(TraceCPU &_owner, const std::string &_name, RequestPort &_port, RequestorID requestor_id, const std::string &trace_file, TraceCPUParams *params)
std::queue< const GraphNode * > depFreeQueue
Queue of dependency-free nodes that are pending issue because resources are not available.
Stats::Scalar numOps
Stat for number of simulated micro-ops.
Stats::Scalar numSendAttempted
bool isValid() const
Check validity of this element.
std::string dataTraceFile
uint64_t NodeSeqNum
Node sequence number type.
static int numTraceCPUs
Number of Trace CPUs in the system used as a shared variable and passed to the CountedExitEvent event...
bool isLoad() const
Is the node a load.
PacketPtr retryPkt
PacketPtr used to store the packet to retry.
Addr virtAddr
The virtual address for the request if any.
static const uint8_t maxRobDep
The maximum no.
void recvTimingSnoopReq(PacketPtr pkt)
Required functionally but do nothing.
Stats::Scalar maxDependents
Stats for data memory accesses replayed.
const uint16_t sizeStoreBuffer
The size of store buffer.
const std::string & name() const
Returns name of the ElasticDataGen instance.
bool traceComplete
Set to true when end of trace is reached.
bool checkAndIssue(const GraphNode *node_ptr, bool first=true)
Attempts to issue a node once the node's source dependencies are complete.
bool tryNext()
This tries to send current or retry packet and returns true if successfull.
const uint32_t windowSize
Window size within which to check for dependencies.
EventFunctionWrapper dcacheNextEvent
Event for the control flow method schedDcacheNext()
Counter totalOps() const
Return totalOps as the number of committed micro-ops plus the speculatively issued loads that are mod...
RobDepArray robDep
Array of order dependencies.
Addr addr
The address for the request.
bool nextRead
Set to true when the next window of instructions need to be read.
Stats::Scalar numSendFailed
void recvReqRetry()
Handle a retry signalled by the cache if instruction read failed in the first attempt.
const RequestorID requestorId
RequestorID used for the requests being sent.
Port & getDataPort()
Used to get a reference to the dcache port.
void printOccupancy()
Print resource occupancy for debugging.
void icacheRetryRecvd()
When instruction cache port receives a retry, schedule event icacheNextEvent.
PacketPtr retryPkt
PacketPtr used to store the packet to retry.
void updateNumOps(uint64_t rob_num)
Stats::Formula cpi
Stat for the CPI.
Addr blocksize
The size of the access for the request.
ElasticDataGen dcacheGen
Instance of ElasticDataGen to replay data read and write requests.
Tick traceOffset
This stores the time offset in the trace, which is taken away from the ready times of requests.
uint64_t getMicroOpCount() const
Get number of micro-ops modelled in the TraceCPU replay.
const RequestorID instRequestorID
Requestor id for instruction read requests.
Tick execTick
The tick at which the ready node must be executed.
int64_t delta
Stores the difference in the send ticks of the current and last packets.
RegDepArray regDep
Array of register dependencies (incoming) if any.
std::string instTraceFile
File names for input instruction and data traces.
The trace cpu replays traces generated using the elastic trace probe attached to the O3 CPU model.
void writeElementAsTrace() const
Write out element in trace-compatible format using debug flag TraceCPUData.
const RequestorID dataRequestorID
Requestor id for data read and write requests.
bool isExecComplete() const
Returns the execComplete variable which is set when the last node is executed.
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