translation.hh

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/*
 * Copyright (c) 2011 ARM Limited
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 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2002-2005 The Regents of The University of Michigan
 * Copyright (c) 2009 The University of Edinburgh
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
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#ifndef __CPU_TRANSLATION_HH__
#define __CPU_TRANSLATION_HH__
 
#include "arch/generic/tlb.hh"
#include "sim/faults.hh"
 
class WholeTranslationState
{
  protected:
    int outstanding;
    Fault faults[2];
 
  public:
    bool delay;
    bool isSplit;
    RequestPtr mainReq;
    RequestPtr sreqLow;
    RequestPtr sreqHigh;
    uint8_t *data;
    uint64_t *res;
    BaseTLB::Mode mode;
 
    WholeTranslationState(const RequestPtr &_req, uint8_t *_data,
                          uint64_t *_res, BaseTLB::Mode _mode)
        : outstanding(1), delay(false), isSplit(false), mainReq(_req),
          sreqLow(NULL), sreqHigh(NULL), data(_data), res(_res), mode(_mode)
    {
        faults[0] = faults[1] = NoFault;
        assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
    }
 
    WholeTranslationState(const RequestPtr &_req, const RequestPtr &_sreqLow,
                          const RequestPtr &_sreqHigh, uint8_t *_data,
                          uint64_t *_res, BaseTLB::Mode _mode)
        : outstanding(2), delay(false), isSplit(true), mainReq(_req),
          sreqLow(_sreqLow), sreqHigh(_sreqHigh), data(_data), res(_res),
          mode(_mode)
    {
        faults[0] = faults[1] = NoFault;
        assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
    }
 
    bool
    finish(const Fault &fault, int index)
    {
        assert(outstanding);
        faults[index] = fault;
        outstanding--;
        if (isSplit && outstanding == 0) {
 
            // For ease later, we copy some state to the main request.
            if (faults[0] == NoFault) {
                mainReq->setPaddr(sreqLow->getPaddr());
            }
            mainReq->setFlags(sreqLow->getFlags());
            mainReq->setFlags(sreqHigh->getFlags());
        }
        return outstanding == 0;
    }
 
    Fault
    getFault() const
    {
        if (!isSplit)
            return faults[0];
        else if (faults[0] != NoFault)
            return faults[0];
        else if (faults[1] != NoFault)
            return faults[1];
        else
            return NoFault;
    }
 
    void
    setNoFault()
    {
        faults[0] = faults[1] = NoFault;
    }
 
    bool
    isStrictlyOrdered() const
    {
        return mainReq->isStrictlyOrdered();
    }
 
    bool
    isPrefetch() const
    {
        return mainReq->isPrefetch();
    }
 
    Addr
    getPaddr() const
    {
        return mainReq->getPaddr();
    }
 
    unsigned
    getFlags()
    {
        return mainReq->getFlags();
    }
 
    void
    deleteReqs()
    {
        mainReq.reset();
        if (isSplit) {
            sreqLow.reset();
            sreqHigh.reset();
        }
    }
};
 
 
template <class ExecContextPtr>
class DataTranslation : public BaseTLB::Translation
{
  protected:
    ExecContextPtr xc;
    WholeTranslationState *state;
    int index;
 
  public:
    DataTranslation(ExecContextPtr _xc, WholeTranslationState* _state)
        : xc(_xc), state(_state), index(0)
    {
    }
 
    DataTranslation(ExecContextPtr _xc, WholeTranslationState* _state,
                    int _index)
        : xc(_xc), state(_state), index(_index)
    {
    }
 
    void
    markDelayed()
    {
        state->delay = true;
    }
 
    void
    finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
           BaseTLB::Mode mode)
    {
        assert(state);
        assert(mode == state->mode);
        if (state->finish(fault, index)) {
            if (state->getFault() == NoFault) {
                // Don't access the request if faulted (due to squash)
                req->setTranslateLatency();
            }
            xc->finishTranslation(state);
        }
        delete this;
    }
 
    bool
    squashed() const
    {
        return xc->isSquashed();
    }
};
 
#endif // __CPU_TRANSLATION_HH__