gem5  v20.1.0.0
translation.hh
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41 
42 #ifndef __CPU_TRANSLATION_HH__
43 #define __CPU_TRANSLATION_HH__
44 
45 #include "arch/generic/tlb.hh"
46 #include "sim/faults.hh"
47 
59 {
60  protected:
63 
64  public:
65  bool delay;
66  bool isSplit;
70  uint8_t *data;
71  uint64_t *res;
73 
78  WholeTranslationState(const RequestPtr &_req, uint8_t *_data,
79  uint64_t *_res, BaseTLB::Mode _mode)
80  : outstanding(1), delay(false), isSplit(false), mainReq(_req),
81  sreqLow(NULL), sreqHigh(NULL), data(_data), res(_res), mode(_mode)
82  {
83  faults[0] = faults[1] = NoFault;
84  assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
85  }
86 
92  WholeTranslationState(const RequestPtr &_req, const RequestPtr &_sreqLow,
93  const RequestPtr &_sreqHigh, uint8_t *_data,
94  uint64_t *_res, BaseTLB::Mode _mode)
95  : outstanding(2), delay(false), isSplit(true), mainReq(_req),
96  sreqLow(_sreqLow), sreqHigh(_sreqHigh), data(_data), res(_res),
97  mode(_mode)
98  {
99  faults[0] = faults[1] = NoFault;
100  assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
101  }
102 
110  bool
111  finish(const Fault &fault, int index)
112  {
113  assert(outstanding);
114  faults[index] = fault;
115  outstanding--;
116  if (isSplit && outstanding == 0) {
117 
118  // For ease later, we copy some state to the main request.
119  if (faults[0] == NoFault) {
120  mainReq->setPaddr(sreqLow->getPaddr());
121  }
122  mainReq->setFlags(sreqLow->getFlags());
123  mainReq->setFlags(sreqHigh->getFlags());
124  }
125  return outstanding == 0;
126  }
127 
132  Fault
133  getFault() const
134  {
135  if (!isSplit)
136  return faults[0];
137  else if (faults[0] != NoFault)
138  return faults[0];
139  else if (faults[1] != NoFault)
140  return faults[1];
141  else
142  return NoFault;
143  }
144 
146  void
148  {
149  faults[0] = faults[1] = NoFault;
150  }
151 
157  bool
159  {
160  return mainReq->isStrictlyOrdered();
161  }
162 
168  bool
169  isPrefetch() const
170  {
171  return mainReq->isPrefetch();
172  }
173 
175  Addr
176  getPaddr() const
177  {
178  return mainReq->getPaddr();
179  }
180 
186  unsigned
188  {
189  return mainReq->getFlags();
190  }
191 
193  void
195  {
196  mainReq.reset();
197  if (isSplit) {
198  sreqLow.reset();
199  sreqHigh.reset();
200  }
201  }
202 };
203 
204 
214 template <class ExecContextPtr>
216 {
217  protected:
218  ExecContextPtr xc;
220  int index;
221 
222  public:
223  DataTranslation(ExecContextPtr _xc, WholeTranslationState* _state)
224  : xc(_xc), state(_state), index(0)
225  {
226  }
227 
228  DataTranslation(ExecContextPtr _xc, WholeTranslationState* _state,
229  int _index)
230  : xc(_xc), state(_state), index(_index)
231  {
232  }
233 
238  void
240  {
241  state->delay = true;
242  }
243 
248  void
249  finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
251  {
252  assert(state);
253  assert(mode == state->mode);
254  if (state->finish(fault, index)) {
255  if (state->getFault() == NoFault) {
256  // Don't access the request if faulted (due to squash)
257  req->setTranslateLatency();
258  }
259  xc->finishTranslation(state);
260  }
261  delete this;
262  }
263 
264  bool
265  squashed() const
266  {
267  return xc->isSquashed();
268  }
269 };
270 
271 #endif // __CPU_TRANSLATION_HH__
WholeTranslationState::mainReq
RequestPtr mainReq
Definition: translation.hh:67
BaseTLB::Read
@ Read
Definition: tlb.hh:57
MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:44
WholeTranslationState::WholeTranslationState
WholeTranslationState(const RequestPtr &_req, uint8_t *_data, uint64_t *_res, BaseTLB::Mode _mode)
Single translation state.
Definition: translation.hh:78
WholeTranslationState::faults
Fault faults[2]
Definition: translation.hh:62
WholeTranslationState::setNoFault
void setNoFault()
Remove all faults from the translation.
Definition: translation.hh:147
tlb.hh
BaseTLB::Mode
Mode
Definition: tlb.hh:57
RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:82
WholeTranslationState::data
uint8_t * data
Definition: translation.hh:70
WholeTranslationState::isPrefetch
bool isPrefetch() const
Check if this request is a prefetch.
Definition: translation.hh:169
WholeTranslationState::mode
BaseTLB::Mode mode
Definition: translation.hh:72
DataTranslation::state
WholeTranslationState * state
Definition: translation.hh:219
faults.hh
DataTranslation::finish
void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode)
Finish this part of the translation and indicate that the whole translation is complete if the state ...
Definition: translation.hh:249
WholeTranslationState
This class captures the state of an address translation.
Definition: translation.hh:58
WholeTranslationState::isSplit
bool isSplit
Definition: translation.hh:66
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:240
WholeTranslationState::finish
bool finish(const Fault &fault, int index)
Finish part of a translation.
Definition: translation.hh:111
WholeTranslationState::isStrictlyOrdered
bool isStrictlyOrdered() const
Check if this request is strictly ordered device access.
Definition: translation.hh:158
DataTranslation::DataTranslation
DataTranslation(ExecContextPtr _xc, WholeTranslationState *_state)
Definition: translation.hh:223
ArmISA::mode
Bitfield< 4, 0 > mode
Definition: miscregs_types.hh:70
BaseTLB::Translation
Definition: tlb.hh:59
WholeTranslationState::sreqHigh
RequestPtr sreqHigh
Definition: translation.hh:69
WholeTranslationState::res
uint64_t * res
Definition: translation.hh:71
NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:245
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
WholeTranslationState::outstanding
int outstanding
Definition: translation.hh:61
DataTranslation::DataTranslation
DataTranslation(ExecContextPtr _xc, WholeTranslationState *_state, int _index)
Definition: translation.hh:228
DataTranslation::squashed
bool squashed() const
This function is used by the page table walker to determine if it should translate the a pending requ...
Definition: translation.hh:265
BaseTLB::Write
@ Write
Definition: tlb.hh:57
WholeTranslationState::sreqLow
RequestPtr sreqLow
Definition: translation.hh:68
WholeTranslationState::deleteReqs
void deleteReqs()
Delete all requests that make up this translation.
Definition: translation.hh:194
WholeTranslationState::getFault
Fault getFault() const
Determine whether this translation produced a fault.
Definition: translation.hh:133
DataTranslation::index
int index
Definition: translation.hh:220
DataTranslation::markDelayed
void markDelayed()
Signal the translation state that the translation has been delayed due to a hw page table walk.
Definition: translation.hh:239
WholeTranslationState::getFlags
unsigned getFlags()
Get the flags associated with this request.
Definition: translation.hh:187
DataTranslation
This class represents part of a data address translation.
Definition: translation.hh:215
WholeTranslationState::WholeTranslationState
WholeTranslationState(const RequestPtr &_req, const RequestPtr &_sreqLow, const RequestPtr &_sreqHigh, uint8_t *_data, uint64_t *_res, BaseTLB::Mode _mode)
Split translation state.
Definition: translation.hh:92
WholeTranslationState::getPaddr
Addr getPaddr() const
Get the physical address of this request.
Definition: translation.hh:176
DataTranslation::xc
ExecContextPtr xc
Definition: translation.hh:218
WholeTranslationState::delay
bool delay
Definition: translation.hh:65

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