- c -

• Cache() : Cache
• cacheAvail() : CacheMemory , PerfectCacheMemory< ENTRY >
• CacheBlk() : CacheBlk
• CacheBlkPrintWrapper() : CacheBlkPrintWrapper
• cacheBlocked() : LSQ< Impl >
• cacheBlockSize() : DmaDevice
• CacheCmdStats() : BaseCache::CacheCmdStats
• cacheLineSize() : BaseCPU , ComputeUnit , LSQUnit< Impl > , System
• CacheMemory() : CacheMemory
• CacheMemoryStats() : CacheMemory::CacheMemoryStats
• cachePortAvailable() : LSQ< Impl >
• cachePortBusy() : LSQ< Impl >
• cacheProbe() : CacheMemory , PerfectCacheMemory< ENTRY >
• CacheRecorder() : CacheRecorder
• CacheReqPacketQueue() : BaseCache::CacheReqPacketQueue
• CacheRequestPort() : BaseCache::CacheRequestPort
• cacheResponding() : Packet
• CacheResponsePort() : BaseCache::CacheResponsePort
• CacheStats() : BaseCache::CacheStats
• CacheTracking() : FALRU::CacheTracking
• cacheUnblocked() : DefaultIEW< Impl > , InstructionQueue< Impl >
• calc_indices() : sc_dt::scfx_rep
• calcAddr() : Gcn3ISA::Inst_DS , Gcn3ISA::Inst_FLAT , Gcn3ISA::Inst_MUBUF , Gcn3ISA::Inst_SMEM
• calcConf() : LoopPredictor , MPP_LoopPredictor , TAGE_SC_L_LoopPredictor
• calcDep() : TAGE_SC_L_TAGE
• calcFreeIQEntries() : DefaultRename< Impl >
• calcFreeLQEntries() : DefaultRename< Impl >
• calcFreeROBEntries() : DefaultRename< Impl >
• calcFreeSQEntries() : DefaultRename< Impl >
• calcIndex() : StoreSet
• calcLocHistIdx() : TournamentBP
• calcPacketTiming() : BaseXBar
• calcPciConfigAddr() : Malta , T1000
• calcPciIOAddr() : Malta , T1000
• calcPciMemAddr() : Malta , T1000
• calcReceiveTick() : DistIface::RecvScheduler
• calcResolution() : BaseKvmTimer , PerfKvmTimer , PosixKvmTimer
• calcSaturation() : GenericSatCounter< T >
• calcSSID() : StoreSet
• calcStackDist() : StackDistCalc
• calcStackDistAndUpdate() : StackDistCalc
• calcTickShift() : ArmSemihosting
• calculateAccessLatency() : BaseCache
• calculateCompressionFactor() : SuperBlk
• calculateIndicesAndTags() : TAGE_SC_L_TAGE , TAGEBase
• calculateLookaheadConfidence() : Prefetcher::SignaturePath , Prefetcher::SignaturePathV2
• calculateParameters() : MPP_TAGE , TAGE_SC_L_TAGE , TAGEBase
• calculatePossiblePwrStates() : PowerDomain
• calculatePowerDomainState() : PowerDomain
• calculatePrefetch() : Prefetcher::AccessMapPatternMatching , Prefetcher::AMPM , Prefetcher::BOP , Prefetcher::DCPT , Prefetcher::DeltaCorrelatingPredictionTables , Prefetcher::IndirectMemory , Prefetcher::IrregularStreamBuffer , Prefetcher::PIF , Prefetcher::Queued , Prefetcher::SBOOE , Prefetcher::SignaturePath , Prefetcher::SlimAMPM , Prefetcher::STeMS , Prefetcher::Stride , Prefetcher::Tagged
• calculatePrefetchConfidence() : Prefetcher::SignaturePath , Prefetcher::SignaturePathV2
• calculateTagOnlyLatency() : BaseCache
• calculateVC() : NetworkInterface
• calculateVectorIndex() : TimeBuffer< T >
• call() : Iris::ThreadContext , m5::Coroutine< Arg, Ret > , sc_gem5::ProcessFuncWrapper , sc_gem5::ProcessMemberFuncWrapper< T > , sc_gem5::ProcessObjFuncWrapper< T > , sc_gem5::ProcessObjRetFuncWrapper< T, R >
• call32() : ArmSemihosting
• call64() : ArmSemihosting
• callback_binder_bw() : tlm_utils::callback_binder_bw< TYPES >
• callback_binder_fw() : tlm_utils::callback_binder_fw< TYPES >
• callClearStandByWfi() : ArmSystem
• callClearWakeRequest() : ArmSystem
• callClock() : ArmSemihosting
• callClose() : ArmSemihosting
• called() : sc_gem5::ScMainFiber
• callElapsed32() : ArmSemihosting
• callElapsed64() : ArmSemihosting
• callErrno() : ArmSemihosting
• CallerType() : m5::Coroutine< Arg, Ret >::CallerType
• callExit32() : ArmSemihosting
• callExit64() : ArmSemihosting
• callExitExtended() : ArmSemihosting
• callFLen() : ArmSemihosting
• callGem5PseudoOp32() : ArmSemihosting
• callGem5PseudoOp64() : ArmSemihosting
• callGetCmdLine() : ArmSemihosting
• callHeapInfo32() : ArmSemihosting
• callHeapInfo64() : ArmSemihosting
• callIsError() : ArmSemihosting
• callIsTTY() : ArmSemihosting
• callOpen() : ArmSemihosting
• callRead() : ArmSemihosting
• callReadC() : ArmSemihosting
• callRemove() : ArmSemihosting
• callRename() : ArmSemihosting
• callSeek() : ArmSemihosting
• callSemihosting() : ArmSystem
• callSemihosting32() : ArmSystem
• callSemihosting64() : ArmSystem
• callSetStandByWfi() : ArmSystem
• callSetWakeRequest() : ArmSystem
• callSystem() : ArmSemihosting
• callTickFreq() : ArmSemihosting
• callTime() : ArmSemihosting
• callTmpNam() : ArmSemihosting
• callWrite() : ArmSemihosting
• callWrite0() : ArmSemihosting
• callWriteC() : ArmSemihosting
• canAccept() : DRAMSim2Wrapper , DRAMsim3Wrapper
• canAllocate() : DynPoolManager , PoolManager , SimplePoolManager
• canAllocateSgprs() : RegisterManager , RegisterManagerPolicy , StaticRegisterManagerPolicy
• canAllocateVgprs() : RegisterManager , RegisterManagerPolicy , StaticRegisterManagerPolicy
• canBeSelectedFor1toNInterrupt() : Gicv3Redistributor
• cancel() : DmaReadFifo::DmaDoneEvent , sc_core::sc_event , sc_gem5::Event
• cancel_all() : sc_core::sc_event_queue , sc_core::sc_event_queue_if , tlm_utils::peq_with_cb_and_phase< OWNER, TYPES > , tlm_utils::peq_with_get< PAYLOAD >
• canceled() : DmaReadFifo::DmaDoneEvent
• cancelReason() : ArmISA::HTMCheckpoint
• cancelTimeout() : sc_gem5::Process
• canCoalesce() : TLBCoalescer
• canCoAllocate() : SuperBlk
• canCommit() : ROB< Impl >
• canForwardDataToLoad() : Minor::LSQ::StoreBuffer
• canInsert() : Minor::FUPipeline , Minor::LSQ::StoreBuffer
• canInstIssue() : Minor::Scoreboard
• canPrefetch() : MSHRQueue
• canPushIntoStoreBuffer() : Minor::LSQ
• canRename() : UnifiedRenameMap
• canRequest() : Minor::LSQ
• canReserve() : LdsState , Minor::InputBuffer< ElemType, ReportTraits, BubbleTraits > , Minor::Queue< ElemType, ReportTraits, BubbleTraits > , Minor::Reservable
• canScheduleReadOperands() : RegisterFile
• canScheduleWriteOperands() : RegisterFile
• canScheduleWriteOperandsFromLoad() : RegisterFile
• canSendToMemorySystem() : Minor::LSQ
• canWB() : LSQUnit< Impl >::SQEntry
• capabilities() : FuncUnit
• capacity() : CircleBuf< T > , CircularQueue< T > , Fifo< T > , TBEStorage
• capCoalescedMMIO() : Kvm
• capDebugRegs() : Kvm
• capExtendedCPUID() : Kvm
• capIRQChip() : Kvm
• capNumMemSlots() : Kvm
• capOneReg() : Kvm
• capSetTSSAddress() : Kvm
• captureFrameBuffer() : VncInput
• capUserMemory() : Kvm
• capUserNMI() : Kvm
• capVCPUEvents() : Kvm
• capXCRs() : Kvm
• capXSave() : Kvm
• cast() : sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::scfx_rep
• cast_switch() : sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::scfx_params
• category() : sc_gem5::DynamicSensitivity , sc_gem5::Sensitivity , sc_gem5::StaticSensitivity
• cbegin() : sc_core::sc_vector< T > , sc_core::sc_vector_assembly< T, MT > , SimpleRenameMap
• cc() : Net::TcpOpt
• cend() : sc_core::sc_vector< T > , sc_core::sc_vector_assembly< T, MT > , SimpleRenameMap
• chainRead() : VirtDescriptor
• chainSize() : VirtDescriptor
• chainWrite() : VirtDescriptor
• changeAddress() : Check
• changeConfig() : Sinic::Device
• changeDirectionPrediction() : IndirectPredictor , SimpleIndirectPredictor
• changedROBEntries() : DefaultCommit< Impl >
• changePermission() : AbstractCacheEntry , PerfectCacheMemory< ENTRY >
• changeStamp() : sc_gem5::Scheduler
• changeStream() : Minor::Fetch1
• Channel() : IdeController::Channel , PixelConverter::Channel , sc_gem5::Channel , X86ISA::I8237::Channel
• ChannelAddr() : ChannelAddr
• ChannelAddrRange() : ChannelAddrRange
• ChannelAddrReg() : X86ISA::I8237::Channel::ChannelAddrReg
• channelRead() : CopyEngine::CopyEngineChannel
• ChannelRemainingReg() : X86ISA::I8237::Channel::ChannelRemainingReg
• channelWrite() : CopyEngine::CopyEngineChannel
• Check() : Check
• check() : FALRU::CacheTracking , MockInfo , PacketFifo , PMAChecker , sc_gem5::TraceVal< T, Base > , sc_gem5::TraceVal<::sc_core::sc_event, Base > , sc_gem5::TraceVal<::sc_core::sc_signal_in_if< T >, Base > , sc_gem5::TraceValBase , sc_gem5::TraceValFxnumBase< T, Base > , Stats::Info , Stats::InfoAccess , Stats::InfoProxy< Stat, Base > , Stats::ProxyInfo , Stats::ValueBase< Derived > , Stats::Vector2dBase< Derived, Stor > , Stats::VectorBase< Derived, Stor > , Stats::VectorDistBase< Derived, Stor > , Trace::ArmNativeTrace , Trace::NativeTrace , Trace::SparcNativeTrace , Trace::X86NativeTrace
• check_bounds() : sc_dt::sc_proxy< X > , sc_dt::sc_subref_r< X >
• check_export_binding() : tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL >
• check_for_wakeup() : SwitchAllocator
• check_if_outside() : sc_dt::sc_signed , sc_dt::sc_unsigned
• check_index() : sc_dt::sc_int_base , sc_dt::sc_signed , sc_dt::sc_uint_base , sc_dt::sc_unsigned
• check_length() : sc_dt::sc_int_base , sc_dt::sc_uint_base
• check_range() : sc_dt::sc_int_base , sc_dt::sc_signed , sc_dt::sc_uint_base , sc_dt::sc_unsigned
• check_value() : sc_dt::sc_int_base , sc_dt::sc_uint_base
• check_wbounds() : sc_dt::sc_proxy< X >
• check_writer() : sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > >
• checkAccessMatchOnActiveEntries() : Prefetcher::IndirectMemory
• checkAddrSizeFaultAArch64() : ArmISA::TableWalker
• checkAdvSIMDOrFPEnabled32() : ArmISA::ArmStaticInst
• checkAndIssue() : TraceCPU::ElasticDataGen
• checkAndSchedExitEvent() : TraceCPU
• checkBpLen() : BaseRemoteGDB , RiscvISA::RemoteGDB , X86ISA::RemoteGDB
• checkCacheability() : MipsISA::TLB , PowerISA::TLB
• checkCandidate() : Prefetcher::AccessMapPatternMatching
• checkClear() : StoreSet
• checkCommandQueue() : Gicv3Its
• checkCondition() : X86ISA::X86MicroopBase
• checkConflict() : PacketQueue
• checkConflictingSnoop() : BaseCache::CacheReqPacketQueue
• checkDeadlock() : TesterThread , UncoalescedTable
• checkDrain() : FlashDevice , IGbE , UFSHostDevice
• checkDrainDone() : DRAMInterface::Rank
• checkDRF() : Episode , ProtocolTester , TesterThread
• checkEL1Trap() : MiscRegOp64
• checkEL2Trap() : MiscRegOp64
• checkEL3Trap() : MiscRegOp64
• checkELMatch() : ArmISA::TlbEntry
• Checker() : Checker< Impl >
• CheckerCPU() : CheckerCPU
• CheckerThreadContext() : CheckerThreadContext< TC >
• checkExit() : ProtocolTester
• checkExpansionContraction() : CompressionBlk
• checkExpected() : SwitchingFiber
• checkExtension() : Kvm
• checkFlags() : CheckerCPU
• checkForActiveGenerationsEnd() : Prefetcher::STeMS
• checkForDeadlock() : RubyDirectedTester , RubyTester
• checkForInterrupts() : BaseSimpleCPU
• checkForStdio() : OutputDirectory
• checkForWFxTrap32() : ArmISA::ArmStaticInst
• checkForWFxTrap64() : ArmISA::ArmStaticInst
• checkFPAdvSIMDEnabled64() : ArmISA::ArmStaticInst
• checkFPAdvSIMDTrap64() : ArmISA::ArmStaticInst
• checkIndex() : sc_core::sc_vector_base
• checkInst() : StoreSet
• checkInterrupt() : DefaultFetch< Impl > , RiscvISA::Interrupts
• checkInterrupts() : ArmISA::Interrupts , BaseCPU , BaseInterrupts , Iris::Interrupts , Minor::Execute , MipsISA::Interrupts , PowerISA::Interrupts , RiscvISA::Interrupts , SparcISA::Interrupts , X86ISA::Interrupts
• checkInterruptsRaw() : X86ISA::Interrupts
• checkLimit() : sc_gem5::ReportSevInfo
• checkLimits() : sc_gem5::ReportMsgInfo
• checkLockedAddrList() : AbstractMemory
• checkMask() : WaiterState
• checkMemResources() : ScheduleStage
• checkMisprediction() : DefaultIEW< Impl >
• checkNetworkAllocation() : Network
• checkPAN() : ArmISA::TLB
• checkPathRedirect() : Process
• checkPcEventQueue() : BaseSimpleCPU
• checkPermissions() : ArmISA::TLB , RiscvISA::TLB
• checkPermissions64() : ArmISA::TLB
• CheckpointIn() : CheckpointIn
• checkpointReschedule() : EventQueue
• checkPort() : sc_gem5::WriteChecker< sc_core::SC_MANY_WRITERS > , sc_gem5::WriteChecker< sc_core::SC_ONE_WRITER >
• checkProtocolVersion() : VncServer
• checkR11Reg() : Trace::X86NativeTrace
• checkRaw() : ArmISA::Interrupts
• checkRcxReg() : Trace::X86NativeTrace
• checkRefreshState() : DRAMInterface
• checkReg() : Trace::NativeTrace
• checkReschedule() : NetworkInterface
• checkResourceAvailable() : CacheMemory
• checkRfOperandReadComplete() : ScheduleStage
• checkSanity() : SimpleAddressMap
• checkSecurity() : VncServer
• checkSETENDEnabled() : ArmISA::ArmStaticInst
• checkSignalsAndUpdate() : DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl >
• checkSnoop() : LSQUnit< Impl >
• checkSoftInt() : SparcISA::ISA
• checkStall() : DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl >
• checkStallQueue() : NetworkInterface
• checkSveEnabled() : ArmISA::ArmStaticInst
• CheckTable() : CheckTable
• checkTransaction() : sc_gem5::TlmToGem5Bridge< BITWIDTH >
• checkVAddrSizeFaultAArch64() : ArmISA::TableWalker
• checkViolations() : LSQUnit< Impl >
• checkWaveReleaseBuf() : FetchUnit::FetchBufDesc
• checkWfiWake() : ArmISA::Interrupts
• checkWrite() : CacheBlk
• checkWriter() : sc_gem5::WriteChecker< sc_core::SC_MANY_WRITERS > , sc_gem5::WriteChecker< sc_core::SC_ONE_WRITER >
• checkXMM() : Trace::X86NativeTrace
• chkInterrupt() : IGbE
• choose() : ArmISA::Crypto
• chooseNext() : MemCtrl
• chooseNextFRFCFS() : DRAMInterface , MemCtrl , MemInterface , NVMInterface
• chooseRead() : NVMInterface
• chooseWave() : __SchedulingPolicy< Policy > , Scheduler , SchedulingPolicy
• chunkComplete() : DmaCallback
• ChunkGenerator() : ChunkGenerator
• chunkOffset() : DecodeCache::AddrMap< Value, CacheChunkShift >
• chunkStart() : DecodeCache::AddrMap< Value, CacheChunkShift >
• CircleBuf() : CircleBuf< T >
• circular_buffer() : tlm::circular_buffer< T >
• CircularQueue() : CircularQueue< T >
• cksum() : Net::TcpOpt
• claim() : SimpleATInitiator1::SimplePool , SimpleATInitiator2::SimplePool
• className() : RegId
• classValue() : RegId
• clean_tail() : sc_dt::sc_bitref< X > , sc_dt::sc_bv_base , sc_dt::sc_concref_r< X, Y > , sc_dt::sc_lv_base , sc_dt::sc_subref_r< X >
• cleanEvictBlk() : Cache
• cleanup() : ListenSocket , X86ISA::GpuTLB
• cleanupRefs() : BaseTags
• cleanupRefsVisitor() : BaseTags
• cleanUpRemovedInsts() : FullO3CPU< Impl >
• clear() : AddrRangeMap< V, max_cache_size > , ArmInterruptPin , ArmISA::Interrupts , ArmISA::ISA , ArmPPI , ArmSPI , BaseInterrupts , BaseStackTrace , BloomFilter::Base , BloomFilter::Multi , BloomFilter::Perfect , Compressed , cp::Format , DataBlock , EtherSwitch::Interface::PortFifo , ExpectedMap< RespType, DataType > , ExpectedMap< RespType, DataType >::ExpectedState< Type > , Flags< T > , FrameBuffer , FunctionProfile , Histogram , IntrControl , ItsCommand , Loader::SymbolTable , LSQUnit< Impl >::LSQEntry , LSQUnit< Impl >::SQEntry , MessageBuffer , MhuDoorbell , MipsISA::Interrupts , MipsISA::ISA , NetDest , PacketFifo , PacketFifoEntry , Plic , PowerISA::Interrupts , PowerISA::ISA , ProfileNode , RiscvISA::Interrupts , RiscvISA::ISA , RubyPrefetcher::NonUnitFilterEntry , sc_core::sc_vector< T > , sc_dt::sc_signed , sc_dt::sc_unsigned , sc_dt::scfx_mant , sc_dt::scfx_rep , sc_dt::scfx_string , sc_gem5::Scheduler , sc_gem5::Sensitivity , sc_gem5::SensitivityEvent , sc_gem5::SensitivityEvents , Set , SparcISA::Interrupts , SparcISA::ISA , SparcISA::PageTableEntry , SparcISA::TlbMap , StoreSet , Time , tlm::circular_buffer< T > , TraceCPU::FixedRetryGen::TraceElement , TraceGen::TraceElement , Trie< Key, Value > , Trie< Key, Value >::Node , WriteMask , X86ISA::Interrupts , X86ISA::ISA
• clear32() : ArmISA::ISA
• clear64() : ArmISA::ISA
• clear_cached_report() : sc_core::sc_report_handler
• clear_extension() : tlm::tlm_generic_payload , tlm_utils::instance_specific_extensions_per_accessor
• clear_request_vector() : SwitchAllocator
• clearAddress() : Doorbell
• clearAll() : ArmISA::Interrupts , BaseInterrupts , IntrControl , Iris::Interrupts , MipsISA::Interrupts , PowerISA::Interrupts , RiscvISA::Interrupts , SparcISA::Interrupts , X86ISA::Interrupts
• clearArchRegs() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• clearBankedDistRange() : MuxingKvmGic
• clearBlockCached() : Packet
• clearBlocked() : BaseCache::CacheResponsePort , BaseCache
• clearCanCommit() : BaseDynInst< Impl >
• clearCanIssue() : BaseDynInst< Impl >
• clearCoherenceBits() : CacheBlk
• clearConsoleInt() : HiFive , Malta , Pc , Platform , RealView , T1000
• clearDistRange() : MuxingKvmGic
• clearDoorbell() : SCMI::PlatformChannel
• clearDownstreamPending() : MSHR , MSHR::TargetList
• clearDynamic() : sc_gem5::Process
• clearEvents() : HSADriver::EventList
• clearFlags() : Event
• clearFromParent() : TimingSimpleCPU::SplitFragmentSenderState
• clearHtmTransactionalState() : BaseDynInst< Impl >
• clearIds() : Iris::ThreadContext::BpInfo
• clearInIQ() : BaseDynInst< Impl >
• clearInROB() : BaseDynInst< Impl >
• clearInst() : DependencyGraph< DynInstPtr >
• clearInstDests() : Minor::Scoreboard
• clearInt() : BaseGic , FastModel::GIC , GenericPciHost , GicV2 , Gicv3 , Gicv3Distributor , MuxingKvmGic , PciHost , PciHost::DeviceInterface , Sp805
• clearInterrupt() : Ap2ScpDoorbell , ArmISA::PMU , BaseCPU , MhuDoorbell , SCMI::Platform , Scp2ApDoorbell , Scp , UFSHostDevice
• clearInterrupts() : BaseCPU , Pl011
• clearIntr() : MaltaCChip , MaltaIO
• clearIPI() : MaltaCChip
• clearIrqCpuInterface() : Gicv3Distributor
• clearIssued() : BaseDynInst< Impl >
• clearITI() : MaltaCChip
• clearLdx() : ArmISA::SoftwareStep
• clearLoadLocks() : CacheBlk
• clearLocked() : AbstractCacheEntry , CacheMemory
• clearLockedAll() : CacheMemory
• clearMemBarrier() : Minor::LSQ
• clearParent() : sc_gem5::Event
• clearPciInt() : HiFive , Malta , Pc , Platform , RealView , T1000
• clearPendingInterrupts() : Gicv3CPUInterface
• clearPPI() : KvmKernelGicV2
• clearPPInt() : BaseGic , FastModel::GIC , GicV2 , Gicv3 , Gicv3Redistributor , MuxingKvmGic
• clearPrefetched() : CacheBlk
• clearReadSignal() : UFSHostDevice::UFSSCSIDevice
• clearRegArrayBit() : X86ISA::Interrupts
• clearReservedSpace() : Minor::Queue< ElemType, ReportTraits, BubbleTraits >
• clearSecure() : TaggedEntry
• clearSerializeAfter() : BaseDynInst< Impl >
• clearSerializeBefore() : BaseDynInst< Impl >
• clearSignal() : UFSHostDevice::UFSSCSIDevice
• clearSingleStep() : BaseRemoteGDB
• clearSPI() : KvmKernelGicV2
• clearStandByWfi() : FVPBasePwrCtrl
• clearStates() : DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl >
• clearStats() : AddressProfiler , MessageBuffer , PerfectSwitch , RubyDirectedTester , RubyTester , Throttle
• clearSummary() : StoreTrace
• clearTempStoreUntil() : ElasticTrace
• clearUnknownPages() : FlashDevice
• clearUsedBits() : SparcISA::TLB
• clearWaitCnts() : Wavefront
• clearWakeRequest() : FVPBasePwrCtrl
• clearWriteThrough() : Packet
• Clint() : Clint
• ClintRegisters() : Clint::ClintRegisters
• clkPeriodAtPerfLevel() : DVFSHandler , SrcClockDomain
• ClockDomain() : ClockDomain
• ClockDomainStats() : ClockDomain::ClockDomainStats
• Clocked() : Clocked
• clockEdge() : Clocked
• ClockedObject() : ClockedObject
• clockPeriod() : ClockDomain , Clocked , DRAMSim2Wrapper , DRAMsim3Wrapper , RealViewOsc , SrcClockDomain , X86ISA::Interrupts
• clockPeriodUpdated() : Clocked , Iris::BaseCPU
• ClockRateControlInitiatorSocket() : ClockRateControlInitiatorSocket
• ClockRateControlSlaveBase() : ClockRateControlSlaveBase
• clocksLeft() : Intel8254Timer::Counter::CounterEvent
• ClockTick() : sc_gem5::ClockTick
• clone() : AtomicGeneric2Op< T > , AtomicGeneric3Op< T > , AtomicGenericPair3Op< T > , AtomicOpAdd< T > , AtomicOpAnd< T > , AtomicOpCAS< T > , AtomicOpDec< T > , AtomicOpExch< T > , AtomicOpFunctor , AtomicOpInc< T > , AtomicOpMax< T > , AtomicOpMin< T > , AtomicOpOr< T > , AtomicOpSub< T > , AtomicOpXor< T > , DeviceFDEntry , FDEntry , FileFDEntry , Gem5SystemC::Gem5Extension , HBFDEntry , Message , my_extension , PipeFDEntry , Process , RiscvISA::AtomicGenericOp< T > , RubyRequest , sc_dt::sc_bitref< X > , sc_dt::sc_bitref_r< T > , sc_dt::sc_concref< X, Y > , sc_dt::sc_concref_r< X, Y > , sc_dt::sc_subref< X > , sc_dt::sc_subref_r< X > , SocketFDEntry , tlm::tlm_endian_context , tlm::tlm_extension< T > , tlm::tlm_extension_base , tlm_utils::instance_specific_extension_carrier , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::mm_end_event_ext , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::mm_end_event_ext , TypedAtomicOpFunctor< T > , X86ISA::I386Process , X86ISA::X86_64Process , X86ISA::X86Process
• close() : ArmSemihosting::File , ArmSemihosting::FileBase , OutputDirectory , RawDiskImage
• closeFDEntry() : FDArray
• closeStreams() : MemTraceProbe , Trace::InstPBTrace
• cmd_async_cont() : BaseRemoteGDB
• cmd_async_step() : BaseRemoteGDB
• cmd_clr_hw_bkpt() : BaseRemoteGDB
• cmd_cont() : BaseRemoteGDB
• cmd_detach() : BaseRemoteGDB
• cmd_mem_r() : BaseRemoteGDB
• cmd_mem_w() : BaseRemoteGDB
• cmd_query_var() : BaseRemoteGDB
• cmd_reg_r() : BaseRemoteGDB
• cmd_reg_w() : BaseRemoteGDB
• cmd_set_hw_bkpt() : BaseRemoteGDB
• cmd_set_thread() : BaseRemoteGDB
• cmd_signal() : BaseRemoteGDB
• cmd_step() : BaseRemoteGDB
• cmd_unsupported() : BaseRemoteGDB
• cmdDisable() : HDLcd
• cmdEnable() : HDLcd
• cmdline() : AtagCmdline
• CmdQueueCmdDmaEvent() : HSAPacketProcessor::CmdQueueCmdDmaEvent
• cmdStats() : BaseCache::CacheStats
• cmdString() : Packet
• cmdToIndex() : Packet
• Cmos() : X86ISA::Cmos
• cmpAndSwap() : BaseCache
• cmpMask() : WriteMask
• cnt() : LinearEquation
• coalesce() : BaseCache , WriteAllocator
• CoalescedRequest() : CoalescedRequest
• coalesceMMIO() : KvmVM
• coalescePacket() : GPUCoalescer
• coalescerReady() : GlobalMemPipeline
• coalescerTokenCount() : Gcn3ISA::GCN3GPUStaticInst , GPUStaticInst
• code() : MipsISA::AddressErrorFault , MipsISA::MipsFault< T > , MipsISA::MipsFaultBase , MipsISA::TlbFault< T > , MipsISA::TlbModifiedFault
• codeAddr() : HSAQueueEntry
• Coeff8() : Coeff8
• Coeff8x8() : Coeff8x8
• CoherentXBar() : CoherentXBar
• CoherentXBarRequestPort() : CoherentXBar::CoherentXBarRequestPort
• CoherentXBarResponsePort() : CoherentXBar::CoherentXBarResponsePort
• collateStats() : AbstractController , AddressProfiler , GarnetNetwork , GPUCoalescer , Network , PerfectSwitch , Profiler , Router , RubySystem , Sequencer , SimpleNetwork , Switch , Throttle
• collectionOutOfRange() : Gicv3Its , ItsCommand
• collectStatistics() : ExecStage , ScoreboardCheckStage
• combineTranslations() : SMMUTranslationProcess
• Command() : DRAMInterface::Command
• command() : Sinic::Device
• commandHandler() : UFSHostDevice
• commandName() : ItsCommand
• commandOffset() : DRAMInterface , MemInterface , NVMInterface
• commit() : DefaultCommit< Impl > , IndirectPredictor , InstructionQueue< Impl > , Minor::Execute , SimpleIndirectPredictor
• commitDrained() : FullO3CPU< Impl >
• commitHead() : DefaultCommit< Impl >
• commitInst() : Minor::Execute
• commitInsts() : DefaultCommit< Impl >
• commitLoad() : LSQUnit< Impl >
• commitLoads() : LSQ< Impl > , LSQUnit< Impl >
• CommitStats() : DefaultCommit< Impl >::CommitStats
• commitStores() : LSQ< Impl > , LSQUnit< Impl >
• committed() : LSQUnit< Impl >::SQEntry
• CommMonitor() : CommMonitor
• CommMonitorSenderState() : CommMonitor::CommMonitorSenderState
• Communication() : SCMI::Communication
• CompactorEntry() : Prefetcher::PIF::CompactorEntry
• compare() : ThreadContext
• compareAddress() : ArmISA::WatchPoint
• compareValue() : ArchTimer
• CompatAddrSpaceMod() : X86ISA::IntelMP::CompatAddrSpaceMod
• CompData() : Compressor::DictionaryCompressor< T >::CompData , Compressor::Perfect::CompData
• compDelayPhysRegDep() : ElasticTrace
• compDelayRob() : ElasticTrace
• complete() : ChunkGenerator , LSQ< Impl >::LSQRequest , LSQ< Impl >::LSQSenderState , LSQUnit< Impl >::LQSenderState , LSQUnit< Impl >::SQSenderState , SCMI::PlatformChannel
• completeAcc() : ArmISAInst::MicroTcommit64 , ArmISAInst::MicroTfence64 , ArmISAInst::Tcancel64 , ArmISAInst::Tstart64 , BaseO3DynInst< Impl > , Gcn3ISA::Inst_DS__DS_READ2_B32 , Gcn3ISA::Inst_DS__DS_READ2_B64 , Gcn3ISA::Inst_DS__DS_READ2ST64_B32 , Gcn3ISA::Inst_DS__DS_READ2ST64_B64 , Gcn3ISA::Inst_DS__DS_READ_B32 , Gcn3ISA::Inst_DS__DS_READ_B64 , Gcn3ISA::Inst_DS__DS_READ_U16 , Gcn3ISA::Inst_DS__DS_READ_U8 , Gcn3ISA::Inst_DS__DS_WRITE2_B32 , Gcn3ISA::Inst_DS__DS_WRITE2_B64 , Gcn3ISA::Inst_DS__DS_WRITE2ST64_B32 , Gcn3ISA::Inst_DS__DS_WRITE_B16 , Gcn3ISA::Inst_DS__DS_WRITE_B32 , Gcn3ISA::Inst_DS__DS_WRITE_B64 , Gcn3ISA::Inst_DS__DS_WRITE_B8 , Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_ADD , Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_ADD_X2 , Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP , Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2 , Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_DEC , Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_DEC_X2 , Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_INC , Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_INC_X2 , Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SUB , Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SUB_X2 , Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SWAP , Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORD , Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORDX2 , Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORDX3 , Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORDX4 , Gcn3ISA::Inst_FLAT__FLAT_LOAD_SBYTE , Gcn3ISA::Inst_FLAT__FLAT_LOAD_SSHORT , Gcn3ISA::Inst_FLAT__FLAT_LOAD_UBYTE , Gcn3ISA::Inst_FLAT__FLAT_LOAD_USHORT , Gcn3ISA::Inst_FLAT__FLAT_STORE_BYTE , Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORD , Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORDX2 , Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORDX3 , Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORDX4 , Gcn3ISA::Inst_FLAT__FLAT_STORE_SHORT , Gcn3ISA::Inst_MIMG__IMAGE_LOAD , Gcn3ISA::Inst_MIMG__IMAGE_LOAD_MIP , Gcn3ISA::Inst_MIMG__IMAGE_LOAD_MIP_PCK , Gcn3ISA::Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN , Gcn3ISA::Inst_MIMG__IMAGE_LOAD_PCK , Gcn3ISA::Inst_MIMG__IMAGE_LOAD_PCK_SGN , Gcn3ISA::Inst_MIMG__IMAGE_STORE , Gcn3ISA::Inst_MIMG__IMAGE_STORE_MIP , Gcn3ISA::Inst_MIMG__IMAGE_STORE_MIP_PCK , Gcn3ISA::Inst_MIMG__IMAGE_STORE_PCK , Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X , Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY , Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ , Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW , Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_X , Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY , Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ , Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW , Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X , Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY , Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ , Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW , Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_X , Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XY , Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ , Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW , Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORD , Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORDX2 , Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORDX3 , Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORDX4 , Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X , Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY , Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ , Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW , Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_X , Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XY , Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ , Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW , Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_SBYTE , Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_SSHORT , Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_UBYTE , Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_USHORT , Gcn3ISA::Inst_MUBUF__BUFFER_STORE_BYTE , Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORD , Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORDX2 , Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORDX3 , Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORDX4 , Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X , Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY , Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ , Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW , Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_X , Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XY , Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ , Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW , Gcn3ISA::Inst_MUBUF__BUFFER_STORE_SHORT , Gcn3ISA::Inst_MUBUF__BUFFER_WBINVL1 , Gcn3ISA::Inst_MUBUF__BUFFER_WBINVL1_VOL , Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORD , Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX16 , Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX2 , Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX4 , Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX8 , Gcn3ISA::Inst_SMEM__S_BUFFER_STORE_DWORD , Gcn3ISA::Inst_SMEM__S_BUFFER_STORE_DWORDX2 , Gcn3ISA::Inst_SMEM__S_BUFFER_STORE_DWORDX4 , Gcn3ISA::Inst_SMEM__S_LOAD_DWORD , Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX16 , Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX2 , Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX4 , Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX8 , Gcn3ISA::Inst_SMEM__S_STORE_DWORD , Gcn3ISA::Inst_SMEM__S_STORE_DWORDX2 , Gcn3ISA::Inst_SMEM__S_STORE_DWORDX4 , GPUDynInst , GPUStaticInst , RiscvISA::RiscvMacroInst , SparcISA::SparcMacroInst , StaticInst
• completed() : LSQUnit< Impl >::SQEntry , MemDepUnit< MemDepPred, Impl >
• completeDataAccess() : LSQ< Impl > , LSQUnit< Impl > , TimingSimpleCPU
• completeDisabledMemAccess() : Minor::LSQ::LSQRequest
• completeDrain() : ArmISA::TableWalker
• completeEpisode() : Episode
• completeHitCallback() : GPUCoalescer
• completeIfetch() : TimingSimpleCPU
• completeInst() : MemDepUnit< MemDepPred, Impl >
• completeIPI() : X86ISA::Interrupts
• completeIssue() : GPUCoalescer
• completeMemAccess() : TraceCPU::ElasticDataGen
• completeMemBarrierInst() : Minor::LSQ
• completePrefetch() : SMMUTranslationProcess
• completeRead() : MemChecker::ByteTracker , MemChecker
• completeRequest() : GarnetSyntheticTraffic , GlobalMemPipeline , MemTest
• completeStore() : LSQUnit< Impl >
• completeTimeSlot() : sc_gem5::Scheduler
• completeTransaction() : SMMUTranslationProcess
• completeWrite() : MemChecker::ByteTracker , MemChecker , MemChecker::WriteCluster
• completionSignal() : HSAQueueEntry
• completionWriteback() : IGbE::TxDescCache
• compltnPending() : AQLRingBuffer , HSAPacketProcessor::RQLEntry
• CompoundFlag() : Debug::CompoundFlag
• compress() : Compressor::Base , Compressor::BaseDelta< BaseType, DeltaSizeBits > , Compressor::DictionaryCompressor< T > , Compressor::FrequentValues , Compressor::Multi , Compressor::Perfect , Compressor::RepeatedQwords , Compressor::Zero
• Compressed() : Compressed
• compressed() : RiscvISA::Decoder , RiscvISA::PCState
• CompressedTags() : CompressedTags
• CompressedValue() : Compressor::FrequentValues::CompData::CompressedValue
• CompressionBlk() : CompressionBlk
• CompressionData() : Compressor::Base::CompressionData
• compressValue() : Compressor::DictionaryCompressor< T >
• compute_local_quantum() : tlm::tlm_global_quantum , tlm_utils::tlm_quantumkeeper
• computeActualWgSz() : Wavefront
• computeBits() : MultiperspectivePerceptron
• computeOutput() : MultiperspectivePerceptron
• computePartialSum() : MultiperspectivePerceptronTAGE
• computeRegClass() : X86ISA::InstRegIndex
• computeStats() : BaseTags , DRAMInterface::Rank , PowerState
• computeStatsVisitor() : BaseTags
• ComputeUnit() : ComputeUnit
• computeUnit() : GPUExecContext
• ComputeUnitStats() : ComputeUnit::ComputeUnitStats
• concat_clear_data() : sc_dt::sc_concatref , sc_dt::sc_value_base
• concat_get_ctrl() : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_dt::sc_concat_bool , sc_dt::sc_concatref , sc_dt::sc_int_base , sc_dt::sc_int_bitref_r , sc_dt::sc_int_subref_r , sc_dt::sc_signed , sc_dt::sc_signed_bitref_r , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_base , sc_dt::sc_uint_bitref_r , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned , sc_dt::sc_unsigned_bitref_r , sc_dt::sc_unsigned_subref_r , sc_dt::sc_value_base
• concat_get_data() : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_dt::sc_concat_bool , sc_dt::sc_concatref , sc_dt::sc_int_base , sc_dt::sc_int_bitref_r , sc_dt::sc_int_subref_r , sc_dt::sc_signed , sc_dt::sc_signed_bitref_r , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_base , sc_dt::sc_uint_bitref_r , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned , sc_dt::sc_unsigned_bitref_r , sc_dt::sc_unsigned_subref_r , sc_dt::sc_value_base
• concat_get_uint64() : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_dt::sc_concat_bool , sc_dt::sc_concatref , sc_dt::sc_int_base , sc_dt::sc_int_bitref_r , sc_dt::sc_int_subref_r , sc_dt::sc_signed , sc_dt::sc_signed_bitref_r , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_base , sc_dt::sc_uint_bitref_r , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned , sc_dt::sc_unsigned_bitref_r , sc_dt::sc_unsigned_subref_r , sc_dt::sc_value_base
• concat_length() : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_dt::sc_concat_bool , sc_dt::sc_concatref , sc_dt::sc_int_base , sc_dt::sc_int_bitref_r , sc_dt::sc_int_subref_r , sc_dt::sc_signed , sc_dt::sc_signed_bitref_r , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_base , sc_dt::sc_uint_bitref_r , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned , sc_dt::sc_unsigned_bitref_r , sc_dt::sc_unsigned_subref_r , sc_dt::sc_value_base
• concat_set() : sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_core::sc_int_sigref , sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > > , sc_core::sc_signed_sigref , sc_core::sc_uint_sigref , sc_core::sc_unsigned_sigref , sc_dt::sc_concatref , sc_dt::sc_int_base , sc_dt::sc_int_bitref , sc_dt::sc_int_subref , sc_dt::sc_signed , sc_dt::sc_signed_bitref , sc_dt::sc_signed_subref , sc_dt::sc_uint_base , sc_dt::sc_uint_bitref , sc_dt::sc_uint_subref , sc_dt::sc_unsigned , sc_dt::sc_unsigned_bitref , sc_dt::sc_unsigned_subref , sc_dt::sc_value_base
• condBranchUpdate() : LoopPredictor , MPP_StatisticalCorrector , StatisticalCorrector , TAGEBase
• conditionalSquash() : O3ThreadContext< Impl >
• CondLogicOp() : PowerISA::CondLogicOp
• CondMoveOp() : PowerISA::CondMoveOp
• condOk() : PowerISA::BranchCond
• ConfigCache() : ConfigCache
• configCacheLookup() : SMMUTranslationProcess
• configCacheUpdate() : SMMUTranslationProcess
• configCP() : MipsISA::ISA
• ConfigTable() : X86ISA::IntelMP::ConfigTable
• conflictAddr() : MSHR , QueueEntry , WriteQueueEntry
• connect() : BaseRemoteGDB , TCPIface
• connectMemPorts() : CheckerThreadContext< TC >
• connectSocket() : VirtIO9PSocket
• connectWrapper() : BaseRemoteGDB
• console_in() : Terminal
• const_iterator() : System::Threads::const_iterator
• ConstNode() : Stats::ConstNode< T >
• ConstProxyPtr() : ConstProxyPtr< T, Proxy >
• construct() : ExtensionPool< T > , sc_dt::sc_fxnum_fast_observer , sc_dt::sc_fxnum_observer , sc_dt::sc_fxval_fast_observer , sc_dt::sc_fxval_observer
• ConstVectorNode() : Stats::ConstVectorNode< T >
• consume() : FunctionProfile
• consumeByte() : X86ISA::Decoder
• consumeBytes() : ArmISA::Decoder , X86ISA::Decoder
• consumeDescriptor() : VirtQueue
• consumeLink() : NetworkLink
• Consumer() : Consumer
• ContainerPrint() : m5::stl_helpers::ContainerPrint< T >
• contains() : AddrRange , AddrRangeMap< V, max_cache_size > , ChannelAddrRange , Loader::MemoryImage , VMA
• containsAddrRangeOf() : Minor::LSQ::LSQRequest
• context() : BaseRemoteGDB
• Context() : sc_gem5::Thread::Context
• contextId() : BaseDynInst< Impl > , CheckerThreadContext< TC > , HSAQueueEntry , Iris::ThreadContext , LSQ< Impl >::LSQSenderState , Minor::ExecContext , O3ThreadContext< Impl > , Request , SimpleThread , ThreadContext , ThreadState
• contextIdToVCpuId() : KvmVM
• contextSwitchQ() : HWScheduler
• contextToThread() : BaseCPU
• contiguousHint() : ArmISA::TableWalker::LongDescriptor
• continueProcessing() : CopyEngine::CopyEngineChannel
• control() : ArchTimer
• ControllerStats() : AbstractController::ControllerStats
• convenience_socket_cb_holder() : tlm_utils::convenience_socket_cb_holder
• convert_2C_to_SM() : sc_dt::sc_signed , sc_dt::sc_unsigned
• convert_SM_to_2C() : sc_dt::sc_signed , sc_dt::sc_unsigned
• convert_SM_to_2C_to_SM() : sc_dt::sc_signed , sc_dt::sc_unsigned
• convertLlToRead() : Packet
• convertScToWrite() : Packet
• CoprocessorUnusableFault() : MipsISA::CoprocessorUnusableFault
• copy() : PollQueue , RefCountingPtr< T >
• copy_digits() : sc_dt::sc_signed , sc_dt::sc_unsigned
• copy_from() : Gem5SystemC::Gem5Extension , my_extension , tlm::tlm_endian_context , tlm::tlm_extension< T > , tlm::tlm_extension_base , tlm_utils::instance_specific_extension_carrier , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::mm_end_event_ext , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::mm_end_event_ext
• copyArchRegs() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• copyBankedDistRange() : MuxingKvmGic
• copyCpuRegister() : MuxingKvmGic
• copyDistRange() : MuxingKvmGic
• copyDistRegister() : MuxingKvmGic
• CopyEngine() : CopyEngine
• CopyEngineChannel() : CopyEngine::CopyEngineChannel
• CopyEngineStats() : CopyEngine::CopyEngineStats
• copyError() : Packet
• copyGicState() : MuxingKvmGic
• copyIn() : BaseBufferArg , FrameBuffer
• copyOut() : AtagHeader , BaseBufferArg , FrameBuffer
• copyout() : PacketFifo
• copyPartial() : DataBlock
• copyResponderFlags() : Packet
• copyResult() : Checker< Impl >
• copyState() : SimpleThread
• copyTo() : VecRegContainer< SIZE >
• CoreDecouplingLTInitiator() : CoreDecouplingLTInitiator
• coreId() : Sequencer
• CorePins() : FastModel::ScxEvsCortexR52< Types >::CorePins
• CoreSpecific() : MipsISA::CoreSpecific
• CoreTimers() : GenericTimer::CoreTimers
• Coroutine() : m5::Coroutine< Arg, Ret >
• CortexA76() : FastModel::CortexA76
• CortexA76Cluster() : FastModel::CortexA76Cluster
• CortexA76TC() : FastModel::CortexA76TC
• CortexR52() : FastModel::CortexR52
• CortexR52Cluster() : FastModel::CortexR52Cluster
• CortexR52TC() : FastModel::CortexR52TC
• count() : NetDest , Set
• Count() : Stats::Units::Count
• count() : SyscallReturn , WriteMask
• countBankConflicts() : LdsState
• countCycles() : Ticked
• CountedExitEvent() : CountedExitEvent
• Counter() : Intel8254Timer::Counter
• counterAtZero() : Sp804::Timer
• counterCtrlRead() : GenericTimerMem
• counterCtrlWrite() : GenericTimerMem
• CounterEvent() : Intel8254Timer::Counter::CounterEvent
• counterInterrupt() : Intel8254Timer , X86ISA::I8254 , X86ISA::I8254::X86Intel8254Timer
• counterLimitReached() : ArchTimer
• counterMatch() : PL031
• CounterState() : ArmISA::PMU::CounterState
• counterStatusRead() : GenericTimerMem
• counterStatusWrite() : GenericTimerMem
• countInst() : BaseSimpleCPU
• countInsts() : InstructionQueue< Impl > , ROB< Impl >
• countIssuedStore() : Minor::LSQ::StoreBuffer
• countPacketsAfter() : PacketFifo
• countPacketsBefore() : PacketFifo
• countReadStarvingForAddress() : PersistentTable
• countStarvingForAddress() : PersistentTable
• countStat() : ArmISA::ArmFault , ArmISA::ArmFaultVals< T > , SparcISA::SparcFault< T > , SparcISA::SparcFaultBase
• countUnbound() : FastModel::SCGIC::Terminator
• CowDiskImage() : CowDiskImage
• cp() : SparcISA::PageTableEntry
• CPack() : Compressor::CPack
• cpsrWriteByInstr() : ArmISA::ArmStaticInst
• CPU() : Iris::CPU< TC >
• cpuClearInt() : IGbE
• cpuEnabled() : GicV2
• cpuId() : BaseCPU , BaseDynInst< Impl > , CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext , ThreadState
• CpuidResult() : X86ISA::CpuidResult
• cpuInterrupt() : NSGigE , Sinic::Base
• cpuIntrAck() : NSGigE , Sinic::Base
• cpuIntrClear() : NSGigE , Sinic::Base
• cpuIntrPending() : NSGigE , Sinic::Base
• cpuIntrPost() : NSGigE , Sinic::Base
• CpuLocalTimer() : CpuLocalTimer
• cpuOnline() : Linux
• CpuPort() : GarnetSyntheticTraffic::CpuPort , MemTest::CpuPort , RubyDirectedTester::CpuPort , RubyTester::CpuPort
• cpuPostInt() : IGbE
• CPUProgressEvent() : CPUProgressEvent
• CpuSidePort() : BaseCache::CpuSidePort
• CPUSidePort() : SimpleCache::CPUSidePort , SimpleMemobj::CPUSidePort
• CpuSidePort() : TLBCoalescer::CpuSidePort , X86ISA::GpuTLB::CpuSidePort
• cpuStartup() : KvmVM
• CpuThread() : CpuThread
• create() : ArmSemihosting::FileBase , Kvm , OutputDirectory , QoS::QueuePolicy , StreamGen , tlm_utils::instance_specific_extension_container , tlm_utils::instance_specific_extension_container_pool
• create_element() : sc_core::sc_vector< T >
• createBackingStore() : PhysicalMemory
• createContext() : Fiber
• createDevice() : KvmVM
• createDmaEngine() : HDLcd
• createDram() : BaseTrafficGen
• createDramRot() : BaseTrafficGen
• createExit() : BaseTrafficGen
• createHybrid() : BaseTrafficGen
• createIdle() : BaseTrafficGen
• createIRQChip() : KvmVM
• createLinear() : BaseTrafficGen
• createLinks() : Topology
• createMemReqEvent() : ComputeUnit::DataPort
• createMemRespEvent() : ComputeUnit::DataPort
• createMissPacket() : BaseCache , Cache , NoncoherentCache
• createNvm() : BaseTrafficGen
• createPacket() : DmaPort::DmaReqState
• createPagefault() : RiscvISA::TLB
• createPkt() : Prefetcher::Queued::DeferredPacket
• createPrefetchRequest() : Prefetcher::Queued
• createProcess() : sc_gem5::ClockTick
• createRandom() : BaseTrafficGen
• createRead() : Packet
• createSpecs() : MultiperspectivePerceptron64KB , MultiperspectivePerceptron8KB , MultiperspectivePerceptron , MultiperspectivePerceptronTAGE64KB , MultiperspectivePerceptronTAGE8KB
• createStreams() : ProtoInputStream
• createStrided() : BaseTrafficGen
• createSubdirectory() : OutputDirectory
• createTimers() : GenericTimer
• createTrace() : BaseTrafficGen
• createTraceFile() : Trace::InstPBTrace
• createVCPU() : KvmVM
• createVM() : Kvm
• createWrite() : Packet
• Credit() : Credit
• CreditLink() : CreditLink
• CrossbarSwitch() : CrossbarSwitch
• CSROp() : RiscvISA::CSROp
• cSwap() : ArmISA::ArmStaticInst
• CThread() : sc_gem5::CThread
• CtrlStats() : MemCtrl::CtrlStats
• ctrOk() : PowerISA::BranchCond
• ctrUpdate() : StatisticalCorrector , TAGEBase
• curCycle() : Clocked
• curPrefix() : Packet::PrintReqState
• currEL() : Gicv3CPUInterface
• current() : sc_gem5::Scheduler
• currentCount() : Intel8254Timer::Counter
• currentFiber() : Fiber
• currentSection() : Serializable
• currentTemperature() : ThermalDomain
• curTaskInfo() : Linux::ThreadInfo
• curTaskMm() : Linux::ThreadInfo
• curTaskMmFromTaskStruct() : Linux::ThreadInfo
• curTaskName() : Linux::ThreadInfo
• curTaskNameFromTaskStruct() : Linux::ThreadInfo
• curTaskPID() : Linux::ThreadInfo
• curTaskPIDFromTaskStruct() : Linux::ThreadInfo
• curTaskStart() : Linux::ThreadInfo
• curTaskStartFromTaskStruct() : Linux::ThreadInfo
• curTaskTGID() : Linux::ThreadInfo
• curTaskTGIDFromTaskStruct() : Linux::ThreadInfo
• curThreadInfo() : Linux::ThreadInfo
• CuSidePort() : LdsState::CuSidePort
• CustomNoMaliGpu() : CustomNoMaliGpu
• cv() : SparcISA::PageTableEntry
• CxxConfigFileBase() : CxxConfigFileBase
• CxxConfigManager() : CxxConfigManager
• CxxConfigParams() : CxxConfigParams
• CxxIniFile() : CxxIniFile
• Cycle() : Stats::Units::Cycle
• Cycles() : Cycles
• cyclesBeforeInsert() : Minor::FUPipeline
• cyclesPerFrame() : DisplayTimings
• cyclesPerLine() : DisplayTimings
• cyclesSinceLastStopped() : Ticked
• cyclesToTicks() : Clocked