ArmISA::ISA Class Reference

#include <isa.hh>

Inheritance diagram for ArmISA::ISA:

Classes
struct	MiscRegLUTEntry
	MiscReg metadata. More...
class	MiscRegLUTEntryInitializer

Public Member Functions
void	clear ()
SelfDebug *	getSelfDebug () const
RegVal	readMiscRegNoEffect (int misc_reg) const
RegVal	readMiscReg (int misc_reg)
void	setMiscRegNoEffect (int misc_reg, RegVal val)
void	setMiscReg (int misc_reg, RegVal val)
RegId	flattenRegId (const RegId &regId) const
int	flattenIntIndex (int reg) const
int	flattenFloatIndex (int reg) const
int	flattenVecIndex (int reg) const
int	flattenVecElemIndex (int reg) const
int	flattenVecPredIndex (int reg) const
int	flattenCCIndex (int reg) const
int	flattenMiscIndex (int reg) const
int	redirectRegVHE (ThreadContext *tc, int misc_reg)
	Returns the enconcing equivalent when VHE is implemented and HCR_EL2.E2H is enabled and executing at EL2. More...
int	snsBankedIndex64 (MiscRegIndex reg, bool ns) const
std::pair< int, int >	getMiscIndices (int misc_reg) const
unsigned	getCurSveVecLenInBits () const
unsigned	getCurSveVecLenInBitsAtReset () const
void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...
void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...
void	startup () override
	startup() is the final initialization call before simulation. More...
void	setupThreadContext ()
void	takeOverFrom (ThreadContext *new_tc, ThreadContext *old_tc) override
Enums::DecoderFlavor	decoderFlavor () const
bool	haveGICv3CpuIfc () const
	Returns true if the ISA has a GICv3 cpu interface. More...
Enums::VecRegRenameMode	vecRegRenameMode () const
	PARAMS (ArmISA)
	ISA (const Params &p)
uint64_t	getExecutingAsid () const override
bool	inUserMode () const override
Public Member Functions inherited from BaseISA
virtual void	setThreadContext (ThreadContext *_tc)
Public Member Functions inherited from SimObject
const Params &	params () const
	SimObject (const Params &p)
virtual	~SimObject ()
virtual const std::string	name () const
virtual void	init ()
	init() is called after all C++ SimObjects have been created and all ports are connected. More...
virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...
virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...
virtual void	regProbePoints ()
	Register probe points for this object. More...
virtual void	regProbeListeners ()
	Register probe listeners for this object. More...
ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...
virtual Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID)
	Get a port with a given name and index. More...
DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...
virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...
virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...
void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...
void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...
Public Member Functions inherited from EventManager
EventQueue *	eventQueue () const
void	schedule (Event &event, Tick when)
void	deschedule (Event &event)
void	reschedule (Event &event, Tick when, bool always=false)
void	schedule (Event *event, Tick when)
void	deschedule (Event *event)
void	reschedule (Event *event, Tick when, bool always=false)
void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...
void	setCurTick (Tick newVal)
	EventManager (EventManager &em)
	Event manger manages events in the event queue. More...
	EventManager (EventManager *em)
	EventManager (EventQueue *eq)
Public Member Functions inherited from Serializable
	Serializable ()
virtual	~Serializable ()
void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...
void	serializeSection (CheckpointOut &cp, const std::string &name) const
void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...
void	unserializeSection (CheckpointIn &cp, const std::string &name)
Public Member Functions inherited from Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...
virtual void	notifyFork ()
	Notify a child process of a fork. More...
Public Member Functions inherited from Stats::Group
	Group (Group *parent, const char *name=nullptr)
	Construct a new statistics group. More...
virtual	~Group ()
virtual void	regStats ()
	Callback to set stat parameters. More...
virtual void	resetStats ()
	Callback to reset stats. More...
virtual void	preDumpStats ()
	Callback before stats are dumped. More...
void	addStat (Stats::Info *info)
	Register a stat with this group. More...
const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...
const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...
void	addStatGroup (const char *name, Group *block)
	Add a stat block as a child of this block. More...
const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...
void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block. More...
	Group ()=delete
	Group (const Group &)=delete
Group &	operator= (const Group &)=delete

Static Public Member Functions
static SelfDebug *	getSelfDebug (ThreadContext *tc)
static void	zeroSveVecRegUpperPart (VecRegContainer &vc, unsigned eCount)
Static Public Member Functions inherited from SimObject
static void	serializeAll (CheckpointOut &cp)
	Serialize all SimObjects in the system. More...
static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...
Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...
static void	serializeAll (const std::string &cpt_dir)
	Serializes all the SimObjects. More...
static void	unserializeGlobals (CheckpointIn &cp)

Protected Member Functions
const MiscRegLUTEntryInitializer	InitReg (uint32_t reg)
void	initializeMiscRegMetadata ()
void	updateRegMap (CPSR cpsr)
BaseISADevice &	getGenericTimer ()
BaseISADevice &	getGICv3CPUInterface ()
void	clear32 (const ArmISAParams &p, const SCTLR &sctlr_rst)
void	clear64 (const ArmISAParams &p)
void	initID32 (const ArmISAParams &p)
void	initID64 (const ArmISAParams &p)
void	addressTranslation (TLB::ArmTranslationType tran_type, BaseTLB::Mode mode, Request::Flags flags, RegVal val)
void	addressTranslation64 (TLB::ArmTranslationType tran_type, BaseTLB::Mode mode, Request::Flags flags, RegVal val)
Protected Member Functions inherited from BaseISA
	SimObject (const Params &p)
Protected Member Functions inherited from Drainable
	Drainable ()
virtual	~Drainable ()
virtual void	drainResume ()
	Resume execution after a successful drain. More...
void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Attributes
ArmSystem *	system
const Enums::DecoderFlavor	_decoderFlavor
const Enums::VecRegRenameMode	_vecRegRenameMode
DummyISADevice	dummyDevice
	Dummy device for to handle non-existing ISA devices. More...
BaseISADevice *	pmu
std::unique_ptr< BaseISADevice >	timer
std::unique_ptr< BaseISADevice >	gicv3CpuInterface
bool	highestELIs64
bool	haveSecurity
bool	haveLPAE
bool	haveVirtualization
bool	haveCrypto
bool	haveLargeAsid64
uint8_t	physAddrRange
bool	haveSVE
bool	haveLSE
bool	haveVHE
bool	havePAN
bool	haveSecEL2
bool	haveTME
unsigned	sveVL
	SVE vector length in quadwords. More...
bool	impdefAsNop
	If true, accesses to IMPLEMENTATION DEFINED registers are treated as NOP hence not causing UNDEFINED INSTRUCTION. More...
bool	afterStartup
SelfDebug *	selfDebug
RegVal	miscRegs [NumMiscRegs]
const IntRegIndex *	intRegMap
Protected Attributes inherited from BaseISA
ThreadContext *	tc = nullptr
Protected Attributes inherited from SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters. More...
Protected Attributes inherited from EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Static Protected Attributes
static std::vector< struct MiscRegLUTEntry >	lookUpMiscReg
	Metadata table accessible via the value of the register. More...

Private Member Functions
void	assert32 ()
void	assert64 ()

Additional Inherited Members
Public Types inherited from SimObject
typedef SimObjectParams	Params

Detailed Description

Definition at line 66 of file isa.hh.

Constructor & Destructor Documentation

ISA()

ArmISA::ISA::ISA

(

const Params &

p

)

Definition at line 63 of file isa.cc.

References _vecRegRenameMode, clear(), dummyDevice, FullSystem, haveCrypto, ArmSystem::haveCrypto(), haveLargeAsid64, ArmSystem::haveLargeAsid64(), haveLPAE, ArmSystem::haveLPAE(), haveLSE, ArmSystem::haveLSE(), havePAN, ArmSystem::havePAN(), haveSecEL2, ArmSystem::haveSecEL2(), haveSecurity, ArmSystem::haveSecurity(), haveSVE, ArmSystem::haveSVE(), haveTME, ArmSystem::haveTME(), haveVHE, ArmSystem::haveVHE(), haveVirtualization, ArmSystem::haveVirtualization(), highestELIs64, ArmSystem::highestELIs64(), initializeMiscRegMetadata(), ArmISA::MISCREG_SCTLR_RST, miscRegs, MipsISA::p, physAddrRange, ArmSystem::physAddrRange(), pmu, ArmISA::preUnflattenMiscReg(), selfDebug, ArmISA::BaseISADevice::setISA(), sveVL, ArmSystem::sveVL(), and system.

Member Function Documentation

addressTranslation()

void ArmISA::ISA::addressTranslation ( TLB::ArmTranslationType  tran_type, BaseTLB::Mode  mode, Request::Flags  flags, RegVal  val  )

protected

Definition at line 2427 of file isa.cc.

References ThreadContext::contextId(), DPRINTF, Request::funcRequestorId, ArmISA::MMU::getAttr(), ArmISA::ArmFault::getFsr(), ArmISA::getMMUPtr(), haveLPAE, ArmISA::TLB::HypMode, ArmISA::ArmFault::iss(), ArmISA::ArmFault::isStage2(), ArmISA::mask, ArmISA::MISCREG_HCR, ArmISA::MISCREG_PAR, ArmISA::MISCREG_TTBCR, ArmISA::mode, NoFault, ThreadContext::pcState(), readMiscRegNoEffect(), ArmISA::TLB::S1S2NsTran, setMiscRegNoEffect(), BaseISA::tc, ArmISA::MMU::translateFunctional(), ArmISA::ArmFault::update(), X86ISA::val, and warn_once.

Referenced by setMiscReg().

addressTranslation64()

void ArmISA::ISA::addressTranslation64 ( TLB::ArmTranslationType  tran_type, BaseTLB::Mode  mode, Request::Flags  flags, RegVal  val  )

protected

Definition at line 2376 of file isa.cc.

References ArmISA::attr, ThreadContext::contextId(), DPRINTF, Request::funcRequestorId, ArmISA::MMU::getAttr(), ArmISA::ArmFault::getFsr(), ArmISA::getMMUPtr(), ArmISA::ArmFault::iss(), ArmISA::ArmFault::isStage2(), ArmISA::mask, ArmISA::MISCREG_PAR_EL1, ArmISA::mode, NoFault, ThreadContext::pcState(), setMiscRegNoEffect(), BaseISA::tc, ArmISA::MMU::translateFunctional(), ArmISA::ArmFault::update(), X86ISA::val, and warn_once.

Referenced by setMiscReg().

assert32()

void ArmISA::ISA::assert32 ( )

inlineprivate

Definition at line 502 of file isa.hh.

References ArmISA::MISCREG_CPSR, readMiscReg(), and ArmISA::width.

Referenced by setMiscReg().

assert64()

void ArmISA::ISA::assert64 ( )

inlineprivate

Definition at line 503 of file isa.hh.

References ArmISA::MISCREG_CPSR, readMiscReg(), and ArmISA::width.

Referenced by setMiscReg().

clear()

void ArmISA::ISA::clear

(

)

Definition at line 126 of file isa.cc.

References clear32(), clear64(), FullSystem, ArmISA::getMMUPtr(), ArmSystem::highestELIs64(), initID32(), initID64(), ArmISA::MMU::invalidateMiscReg(), ArmISA::MISCREG_MVFR0, ArmISA::MISCREG_MVFR1, ArmISA::MISCREG_NMRR_NS, ArmISA::MISCREG_PRRR_NS, ArmISA::MISCREG_SCTLR_RST, ArmISA::MISCREG_SEV_MAILBOX, ArmISA::MISCREG_TLBTR, miscRegs, MipsISA::p, SimObject::params(), system, and BaseISA::tc.

Referenced by ISA().

clear32()

void ArmISA::ISA::clear32 ( const ArmISAParams &  p, const SCTLR &  sctlr_rst  )

protected

Definition at line 218 of file isa.cc.

References FullSystem, haveLPAE, haveSecurity, ArmISA::MISCREG_CPACR, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_FPSID, ArmISA::MISCREG_HCPTR, ArmISA::MISCREG_ID_MMFR0, ArmISA::MISCREG_MVBAR, ArmISA::MISCREG_SCR, ArmISA::MISCREG_SCTLR_NS, ArmISA::MISCREG_SCTLR_RST, ArmISA::MISCREG_SCTLR_S, ArmISA::MISCREG_TTBCR_NS, ArmISA::MISCREG_VBAR_S, miscRegs, ArmISA::MODE_USER, MipsISA::p, ArmSystem::resetAddr(), system, and updateRegMap().

Referenced by clear().

clear64()

void ArmISA::ISA::clear64 ( const ArmISAParams &  p )

protected

Definition at line 270 of file isa.cc.

References ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, haveSecurity, haveVirtualization, ArmSystem::highestEL(), ArmISA::MISCREG_CPSR, ArmISA::MISCREG_HSCTLR, ArmISA::MISCREG_MPIDR_EL1, ArmISA::MISCREG_RVBAR_EL1, ArmISA::MISCREG_RVBAR_EL2, ArmISA::MISCREG_RVBAR_EL3, ArmISA::MISCREG_SCR_EL3, ArmISA::MISCREG_SCTLR_EL3, ArmISA::MISCREG_SCTLR_NS, miscRegs, ArmISA::MODE_EL1H, ArmISA::MODE_EL2H, ArmISA::MODE_EL3H, panic, ArmSystem::resetAddr(), system, and updateRegMap().

Referenced by clear().

decoderFlavor()

Enums::DecoderFlavor ArmISA::ISA::decoderFlavor ( ) const

inline

Definition at line 868 of file isa.hh.

References _decoderFlavor.

flattenCCIndex()

int ArmISA::ISA::flattenCCIndex ( int  reg ) const

inline

Definition at line 623 of file isa.hh.

References X86ISA::reg.

Referenced by flattenRegId().

flattenFloatIndex()

int ArmISA::ISA::flattenFloatIndex ( int  reg ) const

inline

Definition at line 595 of file isa.hh.

References X86ISA::reg.

Referenced by flattenRegId().

flattenIntIndex()

int ArmISA::ISA::flattenIntIndex ( int  reg ) const

inline

Definition at line 563 of file isa.hh.

References ArmISA::el, ArmISA::EL0, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, ArmISA::flattenIntRegModeIndex(), ArmISA::INTREG_SP0, ArmISA::INTREG_SP1, ArmISA::INTREG_SP2, ArmISA::INTREG_SP3, ArmISA::INTREG_SPX, intRegMap, ArmISA::MISCREG_CPSR, miscRegs, ArmISA::NUM_ARCH_INTREGS, ArmISA::NUM_INTREGS, ArmISA::opModeToEL(), panic, and X86ISA::reg.

Referenced by flattenRegId().

flattenMiscIndex()

int ArmISA::ISA::flattenMiscIndex ( int  reg ) const

inline

Definition at line 630 of file isa.hh.

References haveSecurity, highestELIs64, ArmISA::inSecureState(), ArmISA::MISCREG_BANKED, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_MAIR0, ArmISA::MISCREG_MAIR1, ArmISA::MISCREG_MUTEX, ArmISA::MISCREG_NMRR, ArmISA::MISCREG_NMRR_MAIR1, ArmISA::MISCREG_NMRR_MAIR1_NS, ArmISA::MISCREG_NMRR_MAIR1_S, ArmISA::MISCREG_PMCCFILTR, ArmISA::MISCREG_PMSELR, ArmISA::MISCREG_PMXEVTYPER, ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR, ArmISA::MISCREG_PRRR, ArmISA::MISCREG_PRRR_MAIR0, ArmISA::MISCREG_PRRR_MAIR0_NS, ArmISA::MISCREG_PRRR_MAIR0_S, ArmISA::MISCREG_SCR, ArmISA::MISCREG_SPSR, ArmISA::MISCREG_SPSR_ABT, ArmISA::MISCREG_SPSR_EL1, ArmISA::MISCREG_SPSR_EL2, ArmISA::MISCREG_SPSR_EL3, ArmISA::MISCREG_SPSR_FIQ, ArmISA::MISCREG_SPSR_HYP, ArmISA::MISCREG_SPSR_IRQ, ArmISA::MISCREG_SPSR_MON, ArmISA::MISCREG_SPSR_SVC, ArmISA::MISCREG_SPSR_UND, ArmISA::MISCREG_TTBCR, ArmISA::miscRegInfo, miscRegs, ArmISA::MODE_ABORT, ArmISA::MODE_EL0T, ArmISA::MODE_EL1H, ArmISA::MODE_EL1T, ArmISA::MODE_EL2H, ArmISA::MODE_EL2T, ArmISA::MODE_EL3H, ArmISA::MODE_EL3T, ArmISA::MODE_FIQ, ArmISA::MODE_HYP, ArmISA::MODE_IRQ, ArmISA::MODE_MON, ArmISA::MODE_SVC, ArmISA::MODE_UNDEFINED, ArmISA::MODE_USER, panic, readMiscRegNoEffect(), X86ISA::reg, snsBankedIndex64(), and warn.

Referenced by flattenRegId(), and getMiscIndices().

flattenRegId()

RegId ArmISA::ISA::flattenRegId ( const RegId &  regId ) const

inline

Definition at line 539 of file isa.hh.

References CCRegClass, RegId::classValue(), RegId::elemIndex(), flattenCCIndex(), flattenFloatIndex(), flattenIntIndex(), flattenMiscIndex(), flattenVecElemIndex(), flattenVecIndex(), flattenVecPredIndex(), FloatRegClass, RegId::index(), IntRegClass, MiscRegClass, VecElemClass, VecPredRegClass, and VecRegClass.

flattenVecElemIndex()

int ArmISA::ISA::flattenVecElemIndex ( int  reg ) const

inline

Definition at line 609 of file isa.hh.

References X86ISA::reg.

Referenced by flattenRegId().

flattenVecIndex()

int ArmISA::ISA::flattenVecIndex ( int  reg ) const

inline

Definition at line 602 of file isa.hh.

References X86ISA::reg.

Referenced by flattenRegId().

flattenVecPredIndex()

int ArmISA::ISA::flattenVecPredIndex ( int  reg ) const

inline

Definition at line 616 of file isa.hh.

References X86ISA::reg.

Referenced by flattenRegId().

getCurSveVecLenInBits()

unsigned ArmISA::ISA::getCurSveVecLenInBits

(

)

const

Definition at line 2307 of file isa.cc.

References ArmISA::el, ArmISA::EL0, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, ArmISA::ELIsInHost(), FullSystem, haveSecurity, haveVirtualization, ArmISA::isSecure(), ArmISA::len, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_ZCR_EL1, ArmISA::MISCREG_ZCR_EL2, ArmISA::MISCREG_ZCR_EL3, miscRegs, panic_if, sveVL, and BaseISA::tc.

Referenced by ArmISA::ArmStaticInst::getCurSveVecLenInBits(), and setMiscReg().

getCurSveVecLenInBitsAtReset()

unsigned ArmISA::ISA::getCurSveVecLenInBitsAtReset ( ) const

inline

Definition at line 853 of file isa.hh.

References sveVL.

Referenced by ArmISA::Decoder::Decoder().

getExecutingAsid()

uint64_t ArmISA::ISA::getExecutingAsid ( ) const

inlineoverridevirtual

Reimplemented from BaseISA.

Definition at line 891 of file isa.hh.

References ArmISA::MISCREG_CONTEXTIDR, and readMiscRegNoEffect().

getGenericTimer()

BaseISADevice & ArmISA::ISA::getGenericTimer ( )

protected

Definition at line 2279 of file isa.cc.

References ThreadContext::contextId(), ArmSystem::getGenericTimer(), panic, system, BaseISA::tc, and timer.

Referenced by readMiscReg(), and setMiscReg().

getGICv3CPUInterface()

BaseISADevice & ArmISA::ISA::getGICv3CPUInterface ( )

protected

Definition at line 2300 of file isa.cc.

References gicv3CpuInterface, and panic_if.

Referenced by readMiscReg(), and setMiscReg().

getMiscIndices()

std::pair<int,int> ArmISA::ISA::getMiscIndices ( int  misc_reg ) const

inline

Definition at line 830 of file isa.hh.

References flattenMiscIndex(), haveSecurity, highestELIs64, ArmISA::inSecureState(), lookUpMiscReg, ArmISA::MISCREG_BANKED_CHILD, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_SCR, ArmISA::miscRegInfo, and miscRegs.

Referenced by readMiscRegNoEffect(), and setMiscRegNoEffect().

getSelfDebug() [1/2]

SelfDebug* ArmISA::ISA::getSelfDebug ( ) const

inline

Definition at line 521 of file isa.hh.

References selfDebug.

Referenced by ArmISA::ArmStaticInst::activateBreakpoint(), DebugStep::execute(), ArmISA::ArmStaticInst::getPSTATEFromPSR(), getSelfDebug(), ArmISA::TLB::translateFs(), and ArmISA::ArmFault::vectorCatch().

getSelfDebug() [2/2]

static SelfDebug* ArmISA::ISA::getSelfDebug ( ThreadContext *  tc )

inlinestatic

Definition at line 527 of file isa.hh.

References ThreadContext::getIsaPtr(), getSelfDebug(), and BaseISA::tc.

haveGICv3CpuIfc()

bool ArmISA::ISA::haveGICv3CpuIfc ( ) const

inline

Returns true if the ISA has a GICv3 cpu interface.

Definition at line 871 of file isa.hh.

References afterStartup, and gicv3CpuInterface.

initializeMiscRegMetadata()

void ArmISA::ISA::initializeMiscRegMetadata ( )

protected

Some registers alias with others, and therefore need to be translated. When two mapping registers are given, they are the 32b lower and upper halves, respectively, of the 64b register being mapped. aligned with reference documentation ARM DDI 0487A.i pp 1540-1543

NAM = "not architecturally mandated", from ARM DDI 0487A.i, template text "AArch64 System register ___ can be mapped to AArch32 System register ___, but this is not architecturally mandated."

Definition at line 3397 of file miscregs.cc.

References ArmISA::ISA::MiscRegLUTEntryInitializer::allPrivileges(), ArmISA::ISA::MiscRegLUTEntryInitializer::banked(), ArmISA::ISA::MiscRegLUTEntryInitializer::banked64(), ArmISA::ISA::MiscRegLUTEntryInitializer::bankedChild(), ArmISA::EL1, ArmISA::EL2, FullSystem, havePAN, haveSecurity, ArmSystem::highestEL(), highestELIs64, ArmISA::ISA::MiscRegLUTEntryInitializer::hyp(), ArmISA::ISA::MiscRegLUTEntryInitializer::hypSecure(), ArmISA::ISA::MiscRegLUTEntryInitializer::hypWrite(), impdefAsNop, InitReg(), ArmISA::ISA::MiscRegLUTEntryInitializer::mapsTo(), ArmISA::MISCREG_ACTLR, ArmISA::MISCREG_ACTLR_EL1, ArmISA::MISCREG_ACTLR_EL2, ArmISA::MISCREG_ACTLR_EL3, ArmISA::MISCREG_ACTLR_NS, ArmISA::MISCREG_ACTLR_S, ArmISA::MISCREG_ADFSR, ArmISA::MISCREG_ADFSR_NS, ArmISA::MISCREG_ADFSR_S, ArmISA::MISCREG_AFSR0_EL1, ArmISA::MISCREG_AFSR0_EL12, ArmISA::MISCREG_AFSR0_EL2, ArmISA::MISCREG_AFSR0_EL3, ArmISA::MISCREG_AFSR1_EL1, ArmISA::MISCREG_AFSR1_EL12, ArmISA::MISCREG_AFSR1_EL2, ArmISA::MISCREG_AFSR1_EL3, ArmISA::MISCREG_AIDR, ArmISA::MISCREG_AIDR_EL1, ArmISA::MISCREG_AIFSR, ArmISA::MISCREG_AIFSR_NS, ArmISA::MISCREG_AIFSR_S, ArmISA::MISCREG_AMAIR0, ArmISA::MISCREG_AMAIR0_NS, ArmISA::MISCREG_AMAIR0_S, ArmISA::MISCREG_AMAIR1, ArmISA::MISCREG_AMAIR1_NS, ArmISA::MISCREG_AMAIR1_S, ArmISA::MISCREG_AMAIR_EL1, ArmISA::MISCREG_AMAIR_EL12, ArmISA::MISCREG_AMAIR_EL2, ArmISA::MISCREG_AMAIR_EL3, ArmISA::MISCREG_APDAKeyHi_EL1, ArmISA::MISCREG_APDAKeyLo_EL1, ArmISA::MISCREG_APDBKeyHi_EL1, ArmISA::MISCREG_APDBKeyLo_EL1, ArmISA::MISCREG_APGAKeyHi_EL1, ArmISA::MISCREG_APGAKeyLo_EL1, ArmISA::MISCREG_APIAKeyHi_EL1, ArmISA::MISCREG_APIAKeyLo_EL1, ArmISA::MISCREG_APIBKeyHi_EL1, ArmISA::MISCREG_APIBKeyLo_EL1, ArmISA::MISCREG_AT_S12E0R_Xt, ArmISA::MISCREG_AT_S12E0W_Xt, ArmISA::MISCREG_AT_S12E1R_Xt, ArmISA::MISCREG_AT_S12E1W_Xt, ArmISA::MISCREG_AT_S1E0R_Xt, ArmISA::MISCREG_AT_S1E0W_Xt, ArmISA::MISCREG_AT_S1E1R_Xt, ArmISA::MISCREG_AT_S1E1W_Xt, ArmISA::MISCREG_AT_S1E2R_Xt, ArmISA::MISCREG_AT_S1E2W_Xt, ArmISA::MISCREG_AT_S1E3R_Xt, ArmISA::MISCREG_AT_S1E3W_Xt, ArmISA::MISCREG_ATS12NSOPR, ArmISA::MISCREG_ATS12NSOPW, ArmISA::MISCREG_ATS12NSOUR, ArmISA::MISCREG_ATS12NSOUW, ArmISA::MISCREG_ATS1CPR, ArmISA::MISCREG_ATS1CPW, ArmISA::MISCREG_ATS1CUR, ArmISA::MISCREG_ATS1CUW, ArmISA::MISCREG_ATS1HR, ArmISA::MISCREG_ATS1HW, ArmISA::MISCREG_BPIALL, ArmISA::MISCREG_BPIALLIS, ArmISA::MISCREG_BPIMVA, ArmISA::MISCREG_CBAR, ArmISA::MISCREG_CBAR_EL1, ArmISA::MISCREG_CCSIDR, ArmISA::MISCREG_CCSIDR_EL1, ArmISA::MISCREG_CLIDR, ArmISA::MISCREG_CLIDR_EL1, ArmISA::MISCREG_CNTFRQ, ArmISA::MISCREG_CNTFRQ_EL0, ArmISA::MISCREG_CNTHCTL, ArmISA::MISCREG_CNTHCTL_EL2, ArmISA::MISCREG_CNTHP_CTL, ArmISA::MISCREG_CNTHP_CTL_EL2, ArmISA::MISCREG_CNTHP_CVAL, ArmISA::MISCREG_CNTHP_CVAL_EL2, ArmISA::MISCREG_CNTHP_TVAL, ArmISA::MISCREG_CNTHP_TVAL_EL2, ArmISA::MISCREG_CNTHPS_CTL_EL2, ArmISA::MISCREG_CNTHPS_CVAL_EL2, ArmISA::MISCREG_CNTHPS_TVAL_EL2, ArmISA::MISCREG_CNTHV_CTL_EL2, ArmISA::MISCREG_CNTHV_CVAL_EL2, ArmISA::MISCREG_CNTHV_TVAL_EL2, ArmISA::MISCREG_CNTHVS_CTL_EL2, ArmISA::MISCREG_CNTHVS_CVAL_EL2, ArmISA::MISCREG_CNTHVS_TVAL_EL2, ArmISA::MISCREG_CNTKCTL, ArmISA::MISCREG_CNTKCTL_EL1, ArmISA::MISCREG_CNTKCTL_EL12, ArmISA::MISCREG_CNTP_CTL, ArmISA::MISCREG_CNTP_CTL_EL0, ArmISA::MISCREG_CNTP_CTL_EL02, ArmISA::MISCREG_CNTP_CTL_NS, ArmISA::MISCREG_CNTP_CTL_S, ArmISA::MISCREG_CNTP_CVAL, ArmISA::MISCREG_CNTP_CVAL_EL0, ArmISA::MISCREG_CNTP_CVAL_EL02, ArmISA::MISCREG_CNTP_CVAL_NS, ArmISA::MISCREG_CNTP_CVAL_S, ArmISA::MISCREG_CNTP_TVAL, ArmISA::MISCREG_CNTP_TVAL_EL0, ArmISA::MISCREG_CNTP_TVAL_EL02, ArmISA::MISCREG_CNTP_TVAL_NS, ArmISA::MISCREG_CNTP_TVAL_S, ArmISA::MISCREG_CNTPCT, ArmISA::MISCREG_CNTPCT_EL0, ArmISA::MISCREG_CNTPS_CTL_EL1, ArmISA::MISCREG_CNTPS_CVAL_EL1, ArmISA::MISCREG_CNTPS_TVAL_EL1, ArmISA::MISCREG_CNTV_CTL, ArmISA::MISCREG_CNTV_CTL_EL0, ArmISA::MISCREG_CNTV_CTL_EL02, ArmISA::MISCREG_CNTV_CVAL, ArmISA::MISCREG_CNTV_CVAL_EL0, ArmISA::MISCREG_CNTV_CVAL_EL02, ArmISA::MISCREG_CNTV_TVAL, ArmISA::MISCREG_CNTV_TVAL_EL0, ArmISA::MISCREG_CNTV_TVAL_EL02, ArmISA::MISCREG_CNTVCT, ArmISA::MISCREG_CNTVCT_EL0, ArmISA::MISCREG_CNTVOFF, ArmISA::MISCREG_CNTVOFF_EL2, ArmISA::MISCREG_CONTEXTIDR, ArmISA::MISCREG_CONTEXTIDR_EL1, ArmISA::MISCREG_CONTEXTIDR_EL12, ArmISA::MISCREG_CONTEXTIDR_EL2, ArmISA::MISCREG_CONTEXTIDR_NS, ArmISA::MISCREG_CONTEXTIDR_S, ArmISA::MISCREG_CP14_UNIMPL, ArmISA::MISCREG_CP15_UNIMPL, ArmISA::MISCREG_CP15DMB, ArmISA::MISCREG_CP15DSB, ArmISA::MISCREG_CP15ISB, ArmISA::MISCREG_CPACR, ArmISA::MISCREG_CPACR_EL1, ArmISA::MISCREG_CPACR_EL12, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_CPSR_MODE, ArmISA::MISCREG_CPSR_Q, ArmISA::MISCREG_CPTR_EL2, ArmISA::MISCREG_CPTR_EL3, ArmISA::MISCREG_CPUACTLR_EL1, ArmISA::MISCREG_CPUECTLR_EL1, ArmISA::MISCREG_CPUMERRSR, ArmISA::MISCREG_CPUMERRSR_EL1, ArmISA::MISCREG_CSSELR, ArmISA::MISCREG_CSSELR_EL1, ArmISA::MISCREG_CSSELR_NS, ArmISA::MISCREG_CSSELR_S, ArmISA::MISCREG_CTR, ArmISA::MISCREG_CTR_EL0, ArmISA::MISCREG_CURRENTEL, ArmISA::MISCREG_DACR, ArmISA::MISCREG_DACR32_EL2, ArmISA::MISCREG_DACR_NS, ArmISA::MISCREG_DACR_S, ArmISA::MISCREG_DAIF, ArmISA::MISCREG_DBGAUTHSTATUS, ArmISA::MISCREG_DBGAUTHSTATUS_EL1, ArmISA::MISCREG_DBGBCR0, ArmISA::MISCREG_DBGBCR0_EL1, ArmISA::MISCREG_DBGBCR1, ArmISA::MISCREG_DBGBCR10, ArmISA::MISCREG_DBGBCR10_EL1, ArmISA::MISCREG_DBGBCR11, ArmISA::MISCREG_DBGBCR11_EL1, ArmISA::MISCREG_DBGBCR12, ArmISA::MISCREG_DBGBCR12_EL1, ArmISA::MISCREG_DBGBCR13, ArmISA::MISCREG_DBGBCR13_EL1, ArmISA::MISCREG_DBGBCR14, ArmISA::MISCREG_DBGBCR14_EL1, ArmISA::MISCREG_DBGBCR15, ArmISA::MISCREG_DBGBCR15_EL1, ArmISA::MISCREG_DBGBCR1_EL1, ArmISA::MISCREG_DBGBCR2, ArmISA::MISCREG_DBGBCR2_EL1, ArmISA::MISCREG_DBGBCR3, ArmISA::MISCREG_DBGBCR3_EL1, ArmISA::MISCREG_DBGBCR4, ArmISA::MISCREG_DBGBCR4_EL1, ArmISA::MISCREG_DBGBCR5, ArmISA::MISCREG_DBGBCR5_EL1, ArmISA::MISCREG_DBGBCR6, ArmISA::MISCREG_DBGBCR6_EL1, ArmISA::MISCREG_DBGBCR7, ArmISA::MISCREG_DBGBCR7_EL1, ArmISA::MISCREG_DBGBCR8, ArmISA::MISCREG_DBGBCR8_EL1, ArmISA::MISCREG_DBGBCR9, ArmISA::MISCREG_DBGBCR9_EL1, ArmISA::MISCREG_DBGBVR0, ArmISA::MISCREG_DBGBVR0_EL1, ArmISA::MISCREG_DBGBVR1, ArmISA::MISCREG_DBGBVR10, ArmISA::MISCREG_DBGBVR10_EL1, ArmISA::MISCREG_DBGBVR11, ArmISA::MISCREG_DBGBVR11_EL1, ArmISA::MISCREG_DBGBVR12, ArmISA::MISCREG_DBGBVR12_EL1, ArmISA::MISCREG_DBGBVR13, ArmISA::MISCREG_DBGBVR13_EL1, ArmISA::MISCREG_DBGBVR14, ArmISA::MISCREG_DBGBVR14_EL1, ArmISA::MISCREG_DBGBVR15, ArmISA::MISCREG_DBGBVR15_EL1, ArmISA::MISCREG_DBGBVR1_EL1, ArmISA::MISCREG_DBGBVR2, ArmISA::MISCREG_DBGBVR2_EL1, ArmISA::MISCREG_DBGBVR3, ArmISA::MISCREG_DBGBVR3_EL1, ArmISA::MISCREG_DBGBVR4, ArmISA::MISCREG_DBGBVR4_EL1, ArmISA::MISCREG_DBGBVR5, ArmISA::MISCREG_DBGBVR5_EL1, ArmISA::MISCREG_DBGBVR6, ArmISA::MISCREG_DBGBVR6_EL1, ArmISA::MISCREG_DBGBVR7, ArmISA::MISCREG_DBGBVR7_EL1, ArmISA::MISCREG_DBGBVR8, ArmISA::MISCREG_DBGBVR8_EL1, ArmISA::MISCREG_DBGBVR9, ArmISA::MISCREG_DBGBVR9_EL1, ArmISA::MISCREG_DBGBXVR0, ArmISA::MISCREG_DBGBXVR1, ArmISA::MISCREG_DBGBXVR10, ArmISA::MISCREG_DBGBXVR11, ArmISA::MISCREG_DBGBXVR12, ArmISA::MISCREG_DBGBXVR13, ArmISA::MISCREG_DBGBXVR14, ArmISA::MISCREG_DBGBXVR15, ArmISA::MISCREG_DBGBXVR2, ArmISA::MISCREG_DBGBXVR3, ArmISA::MISCREG_DBGBXVR4, ArmISA::MISCREG_DBGBXVR5, ArmISA::MISCREG_DBGBXVR6, ArmISA::MISCREG_DBGBXVR7, ArmISA::MISCREG_DBGBXVR8, ArmISA::MISCREG_DBGBXVR9, ArmISA::MISCREG_DBGCLAIMCLR, ArmISA::MISCREG_DBGCLAIMCLR_EL1, ArmISA::MISCREG_DBGCLAIMSET, ArmISA::MISCREG_DBGCLAIMSET_EL1, ArmISA::MISCREG_DBGDCCINT, ArmISA::MISCREG_DBGDEVID0, ArmISA::MISCREG_DBGDEVID1, ArmISA::MISCREG_DBGDEVID2, ArmISA::MISCREG_DBGDIDR, ArmISA::MISCREG_DBGDRAR, ArmISA::MISCREG_DBGDSAR, ArmISA::MISCREG_DBGDSCRext, ArmISA::MISCREG_DBGDSCRint, ArmISA::MISCREG_DBGDTRRXext, ArmISA::MISCREG_DBGDTRRXint, ArmISA::MISCREG_DBGDTRTXext, ArmISA::MISCREG_DBGDTRTXint, ArmISA::MISCREG_DBGOSDLR, ArmISA::MISCREG_DBGOSECCR, ArmISA::MISCREG_DBGOSLAR, ArmISA::MISCREG_DBGOSLSR, ArmISA::MISCREG_DBGPRCR, ArmISA::MISCREG_DBGPRCR_EL1, ArmISA::MISCREG_DBGVCR, ArmISA::MISCREG_DBGVCR32_EL2, ArmISA::MISCREG_DBGWCR0, ArmISA::MISCREG_DBGWCR0_EL1, ArmISA::MISCREG_DBGWCR1, ArmISA::MISCREG_DBGWCR10, ArmISA::MISCREG_DBGWCR10_EL1, ArmISA::MISCREG_DBGWCR11, ArmISA::MISCREG_DBGWCR11_EL1, ArmISA::MISCREG_DBGWCR12, ArmISA::MISCREG_DBGWCR12_EL1, ArmISA::MISCREG_DBGWCR13, ArmISA::MISCREG_DBGWCR13_EL1, ArmISA::MISCREG_DBGWCR14, ArmISA::MISCREG_DBGWCR14_EL1, ArmISA::MISCREG_DBGWCR15, ArmISA::MISCREG_DBGWCR15_EL1, ArmISA::MISCREG_DBGWCR1_EL1, ArmISA::MISCREG_DBGWCR2, ArmISA::MISCREG_DBGWCR2_EL1, ArmISA::MISCREG_DBGWCR3, ArmISA::MISCREG_DBGWCR3_EL1, ArmISA::MISCREG_DBGWCR4, ArmISA::MISCREG_DBGWCR4_EL1, ArmISA::MISCREG_DBGWCR5, ArmISA::MISCREG_DBGWCR5_EL1, ArmISA::MISCREG_DBGWCR6, ArmISA::MISCREG_DBGWCR6_EL1, ArmISA::MISCREG_DBGWCR7, ArmISA::MISCREG_DBGWCR7_EL1, ArmISA::MISCREG_DBGWCR8, ArmISA::MISCREG_DBGWCR8_EL1, ArmISA::MISCREG_DBGWCR9, ArmISA::MISCREG_DBGWCR9_EL1, ArmISA::MISCREG_DBGWFAR, ArmISA::MISCREG_DBGWVR0, ArmISA::MISCREG_DBGWVR0_EL1, ArmISA::MISCREG_DBGWVR1, ArmISA::MISCREG_DBGWVR10, ArmISA::MISCREG_DBGWVR10_EL1, ArmISA::MISCREG_DBGWVR11, ArmISA::MISCREG_DBGWVR11_EL1, ArmISA::MISCREG_DBGWVR12, ArmISA::MISCREG_DBGWVR12_EL1, ArmISA::MISCREG_DBGWVR13, ArmISA::MISCREG_DBGWVR13_EL1, ArmISA::MISCREG_DBGWVR14, ArmISA::MISCREG_DBGWVR14_EL1, ArmISA::MISCREG_DBGWVR15, ArmISA::MISCREG_DBGWVR15_EL1, ArmISA::MISCREG_DBGWVR1_EL1, ArmISA::MISCREG_DBGWVR2, ArmISA::MISCREG_DBGWVR2_EL1, ArmISA::MISCREG_DBGWVR3, ArmISA::MISCREG_DBGWVR3_EL1, ArmISA::MISCREG_DBGWVR4, ArmISA::MISCREG_DBGWVR4_EL1, ArmISA::MISCREG_DBGWVR5, ArmISA::MISCREG_DBGWVR5_EL1, ArmISA::MISCREG_DBGWVR6, ArmISA::MISCREG_DBGWVR6_EL1, ArmISA::MISCREG_DBGWVR7, ArmISA::MISCREG_DBGWVR7_EL1, ArmISA::MISCREG_DBGWVR8, ArmISA::MISCREG_DBGWVR8_EL1, ArmISA::MISCREG_DBGWVR9, ArmISA::MISCREG_DBGWVR9_EL1, ArmISA::MISCREG_DC_CISW_Xt, ArmISA::MISCREG_DC_CIVAC_Xt, ArmISA::MISCREG_DC_CSW_Xt, ArmISA::MISCREG_DC_CVAC_Xt, ArmISA::MISCREG_DC_CVAU_Xt, ArmISA::MISCREG_DC_ISW_Xt, ArmISA::MISCREG_DC_IVAC_Xt, ArmISA::MISCREG_DC_ZVA_Xt, ArmISA::MISCREG_DCCIMVAC, ArmISA::MISCREG_DCCISW, ArmISA::MISCREG_DCCMVAC, ArmISA::MISCREG_DCCMVAU, ArmISA::MISCREG_DCCSW, ArmISA::MISCREG_DCIMVAC, ArmISA::MISCREG_DCISW, ArmISA::MISCREG_DCZID_EL0, ArmISA::MISCREG_DFAR, ArmISA::MISCREG_DFAR_NS, ArmISA::MISCREG_DFAR_S, ArmISA::MISCREG_DFSR, ArmISA::MISCREG_DFSR_NS, ArmISA::MISCREG_DFSR_S, ArmISA::MISCREG_DISR_EL1, ArmISA::MISCREG_DL1DATA0, ArmISA::MISCREG_DL1DATA0_EL1, ArmISA::MISCREG_DL1DATA1, ArmISA::MISCREG_DL1DATA1_EL1, ArmISA::MISCREG_DL1DATA2, ArmISA::MISCREG_DL1DATA2_EL1, ArmISA::MISCREG_DL1DATA3, ArmISA::MISCREG_DL1DATA3_EL1, ArmISA::MISCREG_DL1DATA4, ArmISA::MISCREG_DL1DATA4_EL1, ArmISA::MISCREG_DLR_EL0, ArmISA::MISCREG_DSPSR_EL0, ArmISA::MISCREG_DTLBIALL, ArmISA::MISCREG_DTLBIASID, ArmISA::MISCREG_DTLBIMVA, ArmISA::MISCREG_ELR_EL1, ArmISA::MISCREG_ELR_EL12, ArmISA::MISCREG_ELR_EL2, ArmISA::MISCREG_ELR_EL3, ArmISA::MISCREG_ELR_HYP, ArmISA::MISCREG_ERRIDR_EL1, ArmISA::MISCREG_ERRSELR_EL1, ArmISA::MISCREG_ERXADDR_EL1, ArmISA::MISCREG_ERXCTLR_EL1, ArmISA::MISCREG_ERXFR_EL1, ArmISA::MISCREG_ERXMISC0_EL1, ArmISA::MISCREG_ERXMISC1_EL1, ArmISA::MISCREG_ERXSTATUS_EL1, ArmISA::MISCREG_ESR_EL1, ArmISA::MISCREG_ESR_EL12, ArmISA::MISCREG_ESR_EL2, ArmISA::MISCREG_ESR_EL3, ArmISA::MISCREG_FAR_EL1, ArmISA::MISCREG_FAR_EL12, ArmISA::MISCREG_FAR_EL2, ArmISA::MISCREG_FAR_EL3, ArmISA::MISCREG_FCSEIDR, ArmISA::MISCREG_FPCR, ArmISA::MISCREG_FPEXC, ArmISA::MISCREG_FPEXC32_EL2, ArmISA::MISCREG_FPSCR, ArmISA::MISCREG_FPSCR_EXC, ArmISA::MISCREG_FPSCR_QC, ArmISA::MISCREG_FPSID, ArmISA::MISCREG_FPSR, ArmISA::MISCREG_HACR, ArmISA::MISCREG_HACR_EL2, ArmISA::MISCREG_HACTLR, ArmISA::MISCREG_HADFSR, ArmISA::MISCREG_HAIFSR, ArmISA::MISCREG_HAMAIR0, ArmISA::MISCREG_HAMAIR1, ArmISA::MISCREG_HCPTR, ArmISA::MISCREG_HCR, ArmISA::MISCREG_HCR2, ArmISA::MISCREG_HCR_EL2, ArmISA::MISCREG_HDCR, ArmISA::MISCREG_HDFAR, ArmISA::MISCREG_HIFAR, ArmISA::MISCREG_HMAIR0, ArmISA::MISCREG_HMAIR1, ArmISA::MISCREG_HPFAR, ArmISA::MISCREG_HPFAR_EL2, ArmISA::MISCREG_HSCTLR, ArmISA::MISCREG_HSR, ArmISA::MISCREG_HSTR, ArmISA::MISCREG_HSTR_EL2, ArmISA::MISCREG_HTCR, ArmISA::MISCREG_HTPIDR, ArmISA::MISCREG_HTTBR, ArmISA::MISCREG_HVBAR, ArmISA::MISCREG_IC_IALLU, ArmISA::MISCREG_IC_IALLUIS, ArmISA::MISCREG_IC_IVAU_Xt, ArmISA::MISCREG_ICC_AP0R0, ArmISA::MISCREG_ICC_AP0R0_EL1, ArmISA::MISCREG_ICC_AP0R1, ArmISA::MISCREG_ICC_AP0R1_EL1, ArmISA::MISCREG_ICC_AP0R2, ArmISA::MISCREG_ICC_AP0R2_EL1, ArmISA::MISCREG_ICC_AP0R3, ArmISA::MISCREG_ICC_AP0R3_EL1, ArmISA::MISCREG_ICC_AP1R0, ArmISA::MISCREG_ICC_AP1R0_EL1, ArmISA::MISCREG_ICC_AP1R0_EL1_NS, ArmISA::MISCREG_ICC_AP1R0_EL1_S, ArmISA::MISCREG_ICC_AP1R0_NS, ArmISA::MISCREG_ICC_AP1R0_S, ArmISA::MISCREG_ICC_AP1R1, ArmISA::MISCREG_ICC_AP1R1_EL1, ArmISA::MISCREG_ICC_AP1R1_EL1_NS, ArmISA::MISCREG_ICC_AP1R1_EL1_S, ArmISA::MISCREG_ICC_AP1R1_NS, ArmISA::MISCREG_ICC_AP1R1_S, ArmISA::MISCREG_ICC_AP1R2, ArmISA::MISCREG_ICC_AP1R2_EL1, ArmISA::MISCREG_ICC_AP1R2_EL1_NS, ArmISA::MISCREG_ICC_AP1R2_EL1_S, ArmISA::MISCREG_ICC_AP1R2_NS, ArmISA::MISCREG_ICC_AP1R2_S, ArmISA::MISCREG_ICC_AP1R3, ArmISA::MISCREG_ICC_AP1R3_EL1, ArmISA::MISCREG_ICC_AP1R3_EL1_NS, ArmISA::MISCREG_ICC_AP1R3_EL1_S, ArmISA::MISCREG_ICC_AP1R3_NS, ArmISA::MISCREG_ICC_AP1R3_S, ArmISA::MISCREG_ICC_ASGI1R, ArmISA::MISCREG_ICC_ASGI1R_EL1, ArmISA::MISCREG_ICC_BPR0, ArmISA::MISCREG_ICC_BPR0_EL1, ArmISA::MISCREG_ICC_BPR1, ArmISA::MISCREG_ICC_BPR1_EL1, ArmISA::MISCREG_ICC_BPR1_EL1_NS, ArmISA::MISCREG_ICC_BPR1_EL1_S, ArmISA::MISCREG_ICC_BPR1_NS, ArmISA::MISCREG_ICC_BPR1_S, ArmISA::MISCREG_ICC_CTLR, ArmISA::MISCREG_ICC_CTLR_EL1, ArmISA::MISCREG_ICC_CTLR_EL1_NS, ArmISA::MISCREG_ICC_CTLR_EL1_S, ArmISA::MISCREG_ICC_CTLR_EL3, ArmISA::MISCREG_ICC_CTLR_NS, ArmISA::MISCREG_ICC_CTLR_S, ArmISA::MISCREG_ICC_DIR, ArmISA::MISCREG_ICC_DIR_EL1, ArmISA::MISCREG_ICC_EOIR0, ArmISA::MISCREG_ICC_EOIR0_EL1, ArmISA::MISCREG_ICC_EOIR1, ArmISA::MISCREG_ICC_EOIR1_EL1, ArmISA::MISCREG_ICC_HPPIR0, ArmISA::MISCREG_ICC_HPPIR0_EL1, ArmISA::MISCREG_ICC_HPPIR1, ArmISA::MISCREG_ICC_HPPIR1_EL1, ArmISA::MISCREG_ICC_HSRE, ArmISA::MISCREG_ICC_IAR0, ArmISA::MISCREG_ICC_IAR0_EL1, ArmISA::MISCREG_ICC_IAR1, ArmISA::MISCREG_ICC_IAR1_EL1, ArmISA::MISCREG_ICC_IGRPEN0, ArmISA::MISCREG_ICC_IGRPEN0_EL1, ArmISA::MISCREG_ICC_IGRPEN1, ArmISA::MISCREG_ICC_IGRPEN1_EL1, ArmISA::MISCREG_ICC_IGRPEN1_EL1_NS, ArmISA::MISCREG_ICC_IGRPEN1_EL1_S, ArmISA::MISCREG_ICC_IGRPEN1_EL3, ArmISA::MISCREG_ICC_IGRPEN1_NS, ArmISA::MISCREG_ICC_IGRPEN1_S, ArmISA::MISCREG_ICC_MCTLR, ArmISA::MISCREG_ICC_MGRPEN1, ArmISA::MISCREG_ICC_MSRE, ArmISA::MISCREG_ICC_PMR, ArmISA::MISCREG_ICC_PMR_EL1, ArmISA::MISCREG_ICC_RPR, ArmISA::MISCREG_ICC_RPR_EL1, ArmISA::MISCREG_ICC_SGI0R, ArmISA::MISCREG_ICC_SGI0R_EL1, ArmISA::MISCREG_ICC_SGI1R, ArmISA::MISCREG_ICC_SGI1R_EL1, ArmISA::MISCREG_ICC_SRE, ArmISA::MISCREG_ICC_SRE_EL1, ArmISA::MISCREG_ICC_SRE_EL1_NS, ArmISA::MISCREG_ICC_SRE_EL1_S, ArmISA::MISCREG_ICC_SRE_EL2, ArmISA::MISCREG_ICC_SRE_EL3, ArmISA::MISCREG_ICC_SRE_NS, ArmISA::MISCREG_ICC_SRE_S, ArmISA::MISCREG_ICH_AP0R0, ArmISA::MISCREG_ICH_AP0R0_EL2, ArmISA::MISCREG_ICH_AP0R1, ArmISA::MISCREG_ICH_AP0R1_EL2, ArmISA::MISCREG_ICH_AP0R2, ArmISA::MISCREG_ICH_AP0R2_EL2, ArmISA::MISCREG_ICH_AP0R3, ArmISA::MISCREG_ICH_AP0R3_EL2, ArmISA::MISCREG_ICH_AP1R0, ArmISA::MISCREG_ICH_AP1R0_EL2, ArmISA::MISCREG_ICH_AP1R1, ArmISA::MISCREG_ICH_AP1R1_EL2, ArmISA::MISCREG_ICH_AP1R2, ArmISA::MISCREG_ICH_AP1R2_EL2, ArmISA::MISCREG_ICH_AP1R3, ArmISA::MISCREG_ICH_AP1R3_EL2, ArmISA::MISCREG_ICH_EISR, ArmISA::MISCREG_ICH_EISR_EL2, ArmISA::MISCREG_ICH_ELRSR, ArmISA::MISCREG_ICH_ELRSR_EL2, ArmISA::MISCREG_ICH_HCR, ArmISA::MISCREG_ICH_HCR_EL2, ArmISA::MISCREG_ICH_LR0, ArmISA::MISCREG_ICH_LR0_EL2, ArmISA::MISCREG_ICH_LR1, ArmISA::MISCREG_ICH_LR10, ArmISA::MISCREG_ICH_LR10_EL2, ArmISA::MISCREG_ICH_LR11, ArmISA::MISCREG_ICH_LR11_EL2, ArmISA::MISCREG_ICH_LR12, ArmISA::MISCREG_ICH_LR12_EL2, ArmISA::MISCREG_ICH_LR13, ArmISA::MISCREG_ICH_LR13_EL2, ArmISA::MISCREG_ICH_LR14, ArmISA::MISCREG_ICH_LR14_EL2, ArmISA::MISCREG_ICH_LR15, ArmISA::MISCREG_ICH_LR15_EL2, ArmISA::MISCREG_ICH_LR1_EL2, ArmISA::MISCREG_ICH_LR2, ArmISA::MISCREG_ICH_LR2_EL2, ArmISA::MISCREG_ICH_LR3, ArmISA::MISCREG_ICH_LR3_EL2, ArmISA::MISCREG_ICH_LR4, ArmISA::MISCREG_ICH_LR4_EL2, ArmISA::MISCREG_ICH_LR5, ArmISA::MISCREG_ICH_LR5_EL2, ArmISA::MISCREG_ICH_LR6, ArmISA::MISCREG_ICH_LR6_EL2, ArmISA::MISCREG_ICH_LR7, ArmISA::MISCREG_ICH_LR7_EL2, ArmISA::MISCREG_ICH_LR8, ArmISA::MISCREG_ICH_LR8_EL2, ArmISA::MISCREG_ICH_LR9, ArmISA::MISCREG_ICH_LR9_EL2, ArmISA::MISCREG_ICH_LRC0, ArmISA::MISCREG_ICH_LRC1, ArmISA::MISCREG_ICH_LRC10, ArmISA::MISCREG_ICH_LRC11, ArmISA::MISCREG_ICH_LRC12, ArmISA::MISCREG_ICH_LRC13, ArmISA::MISCREG_ICH_LRC14, ArmISA::MISCREG_ICH_LRC15, ArmISA::MISCREG_ICH_LRC2, ArmISA::MISCREG_ICH_LRC3, ArmISA::MISCREG_ICH_LRC4, ArmISA::MISCREG_ICH_LRC5, ArmISA::MISCREG_ICH_LRC6, ArmISA::MISCREG_ICH_LRC7, ArmISA::MISCREG_ICH_LRC8, ArmISA::MISCREG_ICH_LRC9, ArmISA::MISCREG_ICH_MISR, ArmISA::MISCREG_ICH_MISR_EL2, ArmISA::MISCREG_ICH_VMCR, ArmISA::MISCREG_ICH_VMCR_EL2, ArmISA::MISCREG_ICH_VTR, ArmISA::MISCREG_ICH_VTR_EL2, ArmISA::MISCREG_ICIALLU, ArmISA::MISCREG_ICIALLUIS, ArmISA::MISCREG_ICIMVAU, ArmISA::MISCREG_ID_AA64AFR0_EL1, ArmISA::MISCREG_ID_AA64AFR1_EL1, ArmISA::MISCREG_ID_AA64DFR0_EL1, ArmISA::MISCREG_ID_AA64DFR1_EL1, ArmISA::MISCREG_ID_AA64ISAR0_EL1, ArmISA::MISCREG_ID_AA64ISAR1_EL1, ArmISA::MISCREG_ID_AA64MMFR0_EL1, ArmISA::MISCREG_ID_AA64MMFR1_EL1, ArmISA::MISCREG_ID_AA64MMFR2_EL1, ArmISA::MISCREG_ID_AA64PFR0_EL1, ArmISA::MISCREG_ID_AA64PFR1_EL1, ArmISA::MISCREG_ID_AA64ZFR0_EL1, ArmISA::MISCREG_ID_AFR0, ArmISA::MISCREG_ID_AFR0_EL1, ArmISA::MISCREG_ID_DFR0, ArmISA::MISCREG_ID_DFR0_EL1, ArmISA::MISCREG_ID_ISAR0, ArmISA::MISCREG_ID_ISAR0_EL1, ArmISA::MISCREG_ID_ISAR1, ArmISA::MISCREG_ID_ISAR1_EL1, ArmISA::MISCREG_ID_ISAR2, ArmISA::MISCREG_ID_ISAR2_EL1, ArmISA::MISCREG_ID_ISAR3, ArmISA::MISCREG_ID_ISAR3_EL1, ArmISA::MISCREG_ID_ISAR4, ArmISA::MISCREG_ID_ISAR4_EL1, ArmISA::MISCREG_ID_ISAR5, ArmISA::MISCREG_ID_ISAR5_EL1, ArmISA::MISCREG_ID_ISAR6, ArmISA::MISCREG_ID_ISAR6_EL1, ArmISA::MISCREG_ID_MMFR0, ArmISA::MISCREG_ID_MMFR0_EL1, ArmISA::MISCREG_ID_MMFR1, ArmISA::MISCREG_ID_MMFR1_EL1, ArmISA::MISCREG_ID_MMFR2, ArmISA::MISCREG_ID_MMFR2_EL1, ArmISA::MISCREG_ID_MMFR3, ArmISA::MISCREG_ID_MMFR3_EL1, ArmISA::MISCREG_ID_MMFR4, ArmISA::MISCREG_ID_MMFR4_EL1, ArmISA::MISCREG_ID_PFR0, ArmISA::MISCREG_ID_PFR0_EL1, ArmISA::MISCREG_ID_PFR1, ArmISA::MISCREG_ID_PFR1_EL1, ArmISA::MISCREG_IFAR, ArmISA::MISCREG_IFAR_NS, ArmISA::MISCREG_IFAR_S, ArmISA::MISCREG_IFSR, ArmISA::MISCREG_IFSR32_EL2, ArmISA::MISCREG_IFSR_NS, ArmISA::MISCREG_IFSR_S, ArmISA::MISCREG_IL1DATA0, ArmISA::MISCREG_IL1DATA0_EL1, ArmISA::MISCREG_IL1DATA1, ArmISA::MISCREG_IL1DATA1_EL1, ArmISA::MISCREG_IL1DATA2, ArmISA::MISCREG_IL1DATA2_EL1, ArmISA::MISCREG_IL1DATA3, ArmISA::MISCREG_IL1DATA3_EL1, ArmISA::MISCREG_IMPDEF_UNIMPL, ArmISA::MISCREG_ISR, ArmISA::MISCREG_ISR_EL1, ArmISA::MISCREG_ITLBIALL, ArmISA::MISCREG_ITLBIASID, ArmISA::MISCREG_ITLBIMVA, ArmISA::MISCREG_JIDR, ArmISA::MISCREG_JMCR, ArmISA::MISCREG_JOSCR, ArmISA::MISCREG_L2ACTLR, ArmISA::MISCREG_L2ACTLR_EL1, ArmISA::MISCREG_L2CTLR, ArmISA::MISCREG_L2CTLR_EL1, ArmISA::MISCREG_L2ECTLR, ArmISA::MISCREG_L2ECTLR_EL1, ArmISA::MISCREG_L2MERRSR, ArmISA::MISCREG_L2MERRSR_EL1, ArmISA::MISCREG_LOCKADDR, ArmISA::MISCREG_LOCKFLAG, ArmISA::MISCREG_MAIR0, ArmISA::MISCREG_MAIR0_NS, ArmISA::MISCREG_MAIR0_S, ArmISA::MISCREG_MAIR1, ArmISA::MISCREG_MAIR1_NS, ArmISA::MISCREG_MAIR1_S, ArmISA::MISCREG_MAIR_EL1, ArmISA::MISCREG_MAIR_EL12, ArmISA::MISCREG_MAIR_EL2, ArmISA::MISCREG_MAIR_EL3, ArmISA::MISCREG_MDCCINT_EL1, ArmISA::MISCREG_MDCCSR_EL0, ArmISA::MISCREG_MDCR_EL2, ArmISA::MISCREG_MDCR_EL3, ArmISA::MISCREG_MDDTR_EL0, ArmISA::MISCREG_MDDTRRX_EL0, ArmISA::MISCREG_MDDTRTX_EL0, ArmISA::MISCREG_MDRAR_EL1, ArmISA::MISCREG_MDSCR_EL1, ArmISA::MISCREG_MIDR, ArmISA::MISCREG_MIDR_EL1, ArmISA::MISCREG_MPIDR, ArmISA::MISCREG_MPIDR_EL1, ArmISA::MISCREG_MVBAR, ArmISA::MISCREG_MVFR0, ArmISA::MISCREG_MVFR0_EL1, ArmISA::MISCREG_MVFR1, ArmISA::MISCREG_MVFR1_EL1, ArmISA::MISCREG_MVFR2_EL1, ArmISA::MISCREG_NMRR, ArmISA::MISCREG_NMRR_MAIR1, ArmISA::MISCREG_NMRR_MAIR1_NS, ArmISA::MISCREG_NMRR_MAIR1_S, ArmISA::MISCREG_NMRR_NS, ArmISA::MISCREG_NMRR_S, ArmISA::MISCREG_NOP, ArmISA::MISCREG_NSACR, ArmISA::MISCREG_NZCV, ArmISA::MISCREG_OSDLR_EL1, ArmISA::MISCREG_OSDTRRX_EL1, ArmISA::MISCREG_OSDTRTX_EL1, ArmISA::MISCREG_OSECCR_EL1, ArmISA::MISCREG_OSLAR_EL1, ArmISA::MISCREG_OSLSR_EL1, ArmISA::MISCREG_PAN, ArmISA::MISCREG_PAR, ArmISA::MISCREG_PAR_EL1, ArmISA::MISCREG_PAR_NS, ArmISA::MISCREG_PAR_S, ArmISA::MISCREG_PMCCFILTR, ArmISA::MISCREG_PMCCFILTR_EL0, ArmISA::MISCREG_PMCCNTR, ArmISA::MISCREG_PMCCNTR_EL0, ArmISA::MISCREG_PMCEID0, ArmISA::MISCREG_PMCEID0_EL0, ArmISA::MISCREG_PMCEID1, ArmISA::MISCREG_PMCEID1_EL0, ArmISA::MISCREG_PMCNTENCLR, ArmISA::MISCREG_PMCNTENCLR_EL0, ArmISA::MISCREG_PMCNTENSET, ArmISA::MISCREG_PMCNTENSET_EL0, ArmISA::MISCREG_PMCR, ArmISA::MISCREG_PMCR_EL0, ArmISA::MISCREG_PMEVCNTR0_EL0, ArmISA::MISCREG_PMEVCNTR1_EL0, ArmISA::MISCREG_PMEVCNTR2_EL0, ArmISA::MISCREG_PMEVCNTR3_EL0, ArmISA::MISCREG_PMEVCNTR4_EL0, ArmISA::MISCREG_PMEVCNTR5_EL0, ArmISA::MISCREG_PMEVTYPER0_EL0, ArmISA::MISCREG_PMEVTYPER1_EL0, ArmISA::MISCREG_PMEVTYPER2_EL0, ArmISA::MISCREG_PMEVTYPER3_EL0, ArmISA::MISCREG_PMEVTYPER4_EL0, ArmISA::MISCREG_PMEVTYPER5_EL0, ArmISA::MISCREG_PMINTENCLR, ArmISA::MISCREG_PMINTENCLR_EL1, ArmISA::MISCREG_PMINTENSET, ArmISA::MISCREG_PMINTENSET_EL1, ArmISA::MISCREG_PMOVSCLR_EL0, ArmISA::MISCREG_PMOVSR, ArmISA::MISCREG_PMOVSSET, ArmISA::MISCREG_PMOVSSET_EL0, ArmISA::MISCREG_PMSELR, ArmISA::MISCREG_PMSELR_EL0, ArmISA::MISCREG_PMSWINC, ArmISA::MISCREG_PMSWINC_EL0, ArmISA::MISCREG_PMUSERENR, ArmISA::MISCREG_PMUSERENR_EL0, ArmISA::MISCREG_PMXEVCNTR, ArmISA::MISCREG_PMXEVCNTR_EL0, ArmISA::MISCREG_PMXEVTYPER, ArmISA::MISCREG_PMXEVTYPER_EL0, ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR, ArmISA::MISCREG_PRRR, ArmISA::MISCREG_PRRR_MAIR0, ArmISA::MISCREG_PRRR_MAIR0_NS, ArmISA::MISCREG_PRRR_MAIR0_S, ArmISA::MISCREG_PRRR_NS, ArmISA::MISCREG_PRRR_S, ArmISA::MISCREG_RAMINDEX, ArmISA::MISCREG_RAZ, ArmISA::MISCREG_REVIDR, ArmISA::MISCREG_REVIDR_EL1, ArmISA::MISCREG_RMR, ArmISA::MISCREG_RMR_EL3, ArmISA::MISCREG_RVBAR_EL1, ArmISA::MISCREG_RVBAR_EL2, ArmISA::MISCREG_RVBAR_EL3, ArmISA::MISCREG_SCR, ArmISA::MISCREG_SCR_EL3, ArmISA::MISCREG_SCTLR, ArmISA::MISCREG_SCTLR_EL1, ArmISA::MISCREG_SCTLR_EL12, ArmISA::MISCREG_SCTLR_EL2, ArmISA::MISCREG_SCTLR_EL3, ArmISA::MISCREG_SCTLR_NS, ArmISA::MISCREG_SCTLR_RST, ArmISA::MISCREG_SCTLR_S, ArmISA::MISCREG_SDCR, ArmISA::MISCREG_SDER, ArmISA::MISCREG_SDER32_EL3, ArmISA::MISCREG_SEV_MAILBOX, ArmISA::MISCREG_SP_EL0, ArmISA::MISCREG_SP_EL1, ArmISA::MISCREG_SP_EL2, ArmISA::MISCREG_SPSEL, ArmISA::MISCREG_SPSR, ArmISA::MISCREG_SPSR_ABT, ArmISA::MISCREG_SPSR_ABT_AA64, ArmISA::MISCREG_SPSR_EL1, ArmISA::MISCREG_SPSR_EL12, ArmISA::MISCREG_SPSR_EL2, ArmISA::MISCREG_SPSR_EL3, ArmISA::MISCREG_SPSR_FIQ, ArmISA::MISCREG_SPSR_FIQ_AA64, ArmISA::MISCREG_SPSR_HYP, ArmISA::MISCREG_SPSR_IRQ, ArmISA::MISCREG_SPSR_IRQ_AA64, ArmISA::MISCREG_SPSR_MON, ArmISA::MISCREG_SPSR_SVC, ArmISA::MISCREG_SPSR_UND, ArmISA::MISCREG_SPSR_UND_AA64, ArmISA::MISCREG_TCMTR, ArmISA::MISCREG_TCR_EL1, ArmISA::MISCREG_TCR_EL12, ArmISA::MISCREG_TCR_EL2, ArmISA::MISCREG_TCR_EL3, ArmISA::MISCREG_TEECR, ArmISA::MISCREG_TEECR32_EL1, ArmISA::MISCREG_TEEHBR, ArmISA::MISCREG_TEEHBR32_EL1, ArmISA::MISCREG_TLBI_ALLE1, ArmISA::MISCREG_TLBI_ALLE1IS, ArmISA::MISCREG_TLBI_ALLE2, ArmISA::MISCREG_TLBI_ALLE2IS, ArmISA::MISCREG_TLBI_ALLE3, ArmISA::MISCREG_TLBI_ALLE3IS, ArmISA::MISCREG_TLBI_ASIDE1_Xt, ArmISA::MISCREG_TLBI_ASIDE1IS_Xt, ArmISA::MISCREG_TLBI_IPAS2E1_Xt, ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt, ArmISA::MISCREG_TLBI_IPAS2LE1_Xt, ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt, ArmISA::MISCREG_TLBI_VAAE1_Xt, ArmISA::MISCREG_TLBI_VAAE1IS_Xt, ArmISA::MISCREG_TLBI_VAALE1_Xt, ArmISA::MISCREG_TLBI_VAALE1IS_Xt, ArmISA::MISCREG_TLBI_VAE1_Xt, ArmISA::MISCREG_TLBI_VAE1IS_Xt, ArmISA::MISCREG_TLBI_VAE2_Xt, ArmISA::MISCREG_TLBI_VAE2IS_Xt, ArmISA::MISCREG_TLBI_VAE3_Xt, ArmISA::MISCREG_TLBI_VAE3IS_Xt, ArmISA::MISCREG_TLBI_VALE1_Xt, ArmISA::MISCREG_TLBI_VALE1IS_Xt, ArmISA::MISCREG_TLBI_VALE2_Xt, ArmISA::MISCREG_TLBI_VALE2IS_Xt, ArmISA::MISCREG_TLBI_VALE3_Xt, ArmISA::MISCREG_TLBI_VALE3IS_Xt, ArmISA::MISCREG_TLBI_VMALLE1, ArmISA::MISCREG_TLBI_VMALLE1IS, ArmISA::MISCREG_TLBI_VMALLS12E1, ArmISA::MISCREG_TLBI_VMALLS12E1IS, ArmISA::MISCREG_TLBIALL, ArmISA::MISCREG_TLBIALLH, ArmISA::MISCREG_TLBIALLHIS, ArmISA::MISCREG_TLBIALLIS, ArmISA::MISCREG_TLBIALLNSNH, ArmISA::MISCREG_TLBIALLNSNHIS, ArmISA::MISCREG_TLBIASID, ArmISA::MISCREG_TLBIASIDIS, ArmISA::MISCREG_TLBIIPAS2, ArmISA::MISCREG_TLBIIPAS2IS, ArmISA::MISCREG_TLBIIPAS2L, ArmISA::MISCREG_TLBIIPAS2LIS, ArmISA::MISCREG_TLBIMVA, ArmISA::MISCREG_TLBIMVAA, ArmISA::MISCREG_TLBIMVAAIS, ArmISA::MISCREG_TLBIMVAAL, ArmISA::MISCREG_TLBIMVAALIS, ArmISA::MISCREG_TLBIMVAH, ArmISA::MISCREG_TLBIMVAHIS, ArmISA::MISCREG_TLBIMVAIS, ArmISA::MISCREG_TLBIMVAL, ArmISA::MISCREG_TLBIMVALH, ArmISA::MISCREG_TLBIMVALHIS, ArmISA::MISCREG_TLBIMVALIS, ArmISA::MISCREG_TLBTR, ArmISA::MISCREG_TPIDR_EL0, ArmISA::MISCREG_TPIDR_EL1, ArmISA::MISCREG_TPIDR_EL2, ArmISA::MISCREG_TPIDR_EL3, ArmISA::MISCREG_TPIDRPRW, ArmISA::MISCREG_TPIDRPRW_NS, ArmISA::MISCREG_TPIDRPRW_S, ArmISA::MISCREG_TPIDRRO_EL0, ArmISA::MISCREG_TPIDRURO, ArmISA::MISCREG_TPIDRURO_NS, ArmISA::MISCREG_TPIDRURO_S, ArmISA::MISCREG_TPIDRURW, ArmISA::MISCREG_TPIDRURW_NS, ArmISA::MISCREG_TPIDRURW_S, ArmISA::MISCREG_TTBCR, ArmISA::MISCREG_TTBCR_NS, ArmISA::MISCREG_TTBCR_S, ArmISA::MISCREG_TTBR0, ArmISA::MISCREG_TTBR0_EL1, ArmISA::MISCREG_TTBR0_EL12, ArmISA::MISCREG_TTBR0_EL2, ArmISA::MISCREG_TTBR0_EL3, ArmISA::MISCREG_TTBR0_NS, ArmISA::MISCREG_TTBR0_S, ArmISA::MISCREG_TTBR1, ArmISA::MISCREG_TTBR1_EL1, ArmISA::MISCREG_TTBR1_EL12, ArmISA::MISCREG_TTBR1_EL2, ArmISA::MISCREG_TTBR1_NS, ArmISA::MISCREG_TTBR1_S, ArmISA::MISCREG_UNKNOWN, ArmISA::MISCREG_VBAR, ArmISA::MISCREG_VBAR_EL1, ArmISA::MISCREG_VBAR_EL12, ArmISA::MISCREG_VBAR_EL2, ArmISA::MISCREG_VBAR_EL3, ArmISA::MISCREG_VBAR_NS, ArmISA::MISCREG_VBAR_S, ArmISA::MISCREG_VDISR_EL2, ArmISA::MISCREG_VMPIDR, ArmISA::MISCREG_VMPIDR_EL2, ArmISA::MISCREG_VPIDR, ArmISA::MISCREG_VPIDR_EL2, ArmISA::MISCREG_VSESR_EL2, ArmISA::MISCREG_VSTCR_EL2, ArmISA::MISCREG_VSTTBR_EL2, ArmISA::MISCREG_VTCR, ArmISA::MISCREG_VTCR_EL2, ArmISA::MISCREG_VTTBR, ArmISA::MISCREG_VTTBR_EL2, ArmISA::MISCREG_ZCR_EL1, ArmISA::MISCREG_ZCR_EL12, ArmISA::MISCREG_ZCR_EL2, ArmISA::MISCREG_ZCR_EL3, ArmISA::ISA::MiscRegLUTEntryInitializer::mon(), ArmISA::ISA::MiscRegLUTEntryInitializer::monE2H(), ArmISA::ISA::MiscRegLUTEntryInitializer::monNonSecure(), ArmISA::ISA::MiscRegLUTEntryInitializer::monNonSecureWrite(), ArmISA::ISA::MiscRegLUTEntryInitializer::monSecureWrite(), ArmISA::ISA::MiscRegLUTEntryInitializer::mutex(), ArmISA::ISA::MiscRegLUTEntryInitializer::privSecureWrite(), ArmISA::ISA::MiscRegLUTEntryInitializer::reads(), ArmISA::ISA::MiscRegLUTEntryInitializer::res0(), system, ArmISA::ISA::MiscRegLUTEntryInitializer::unimplemented(), ArmISA::ISA::MiscRegLUTEntryInitializer::unverifiable(), ArmISA::ISA::MiscRegLUTEntryInitializer::warnNotFail(), and ArmISA::ISA::MiscRegLUTEntryInitializer::writes().

Referenced by ISA().

initID32()

void ArmISA::ISA::initID32 ( const ArmISAParams &  p )

protected

Definition at line 319 of file isa.cc.

References haveCrypto, highestELIs64, insertBits(), ArmISA::MISCREG_ID_ISAR0, ArmISA::MISCREG_ID_ISAR1, ArmISA::MISCREG_ID_ISAR2, ArmISA::MISCREG_ID_ISAR3, ArmISA::MISCREG_ID_ISAR4, ArmISA::MISCREG_ID_ISAR5, ArmISA::MISCREG_ID_ISAR6, ArmISA::MISCREG_ID_MMFR0, ArmISA::MISCREG_ID_MMFR1, ArmISA::MISCREG_ID_MMFR2, ArmISA::MISCREG_ID_MMFR3, ArmISA::MISCREG_ID_MMFR4, ArmISA::MISCREG_MIDR, ArmISA::MISCREG_MIDR_EL1, ArmISA::MISCREG_VPIDR, miscRegs, and MipsISA::p.

Referenced by clear().

initID64()

void ArmISA::ISA::initID64 ( const ArmISAParams &  p )

protected

Definition at line 357 of file isa.cc.

References ArmISA::encodePhysAddrRange64(), haveCrypto, haveLargeAsid64, haveLSE, havePAN, haveSecEL2, haveSecurity, haveSVE, haveTME, haveVHE, haveVirtualization, insertBits(), ArmISA::MISCREG_ID_AA64AFR0_EL1, ArmISA::MISCREG_ID_AA64AFR1_EL1, ArmISA::MISCREG_ID_AA64DFR0_EL1, ArmISA::MISCREG_ID_AA64DFR1_EL1, ArmISA::MISCREG_ID_AA64ISAR0_EL1, ArmISA::MISCREG_ID_AA64ISAR1_EL1, ArmISA::MISCREG_ID_AA64MMFR0_EL1, ArmISA::MISCREG_ID_AA64MMFR1_EL1, ArmISA::MISCREG_ID_AA64MMFR2_EL1, ArmISA::MISCREG_ID_AA64PFR0_EL1, ArmISA::MISCREG_ID_AA64ZFR0_EL1, ArmISA::MISCREG_ID_DFR0, ArmISA::MISCREG_ID_DFR0_EL1, ArmISA::MISCREG_ZCR_EL1, ArmISA::MISCREG_ZCR_EL2, ArmISA::MISCREG_ZCR_EL3, miscRegs, MipsISA::p, physAddrRange, sveVL, and ULL.

Referenced by clear().

InitReg()

const MiscRegLUTEntryInitializer ArmISA::ISA::InitReg ( uint32_t  reg )

inlineprotected

Definition at line 450 of file isa.hh.

References lookUpMiscReg, ArmISA::miscRegInfo, and X86ISA::reg.

Referenced by initializeMiscRegMetadata().

inUserMode()

bool ArmISA::ISA::inUserMode ( ) const

inlineoverridevirtual

Implements BaseISA.

Definition at line 897 of file isa.hh.

References ArmISA::inUserMode(), ArmISA::MISCREG_CPSR, and miscRegs.

PARAMS()

ArmISA::ISA::PARAMS

(

ArmISA

)

readMiscReg()

RegVal ArmISA::ISA::readMiscReg

(

int

misc_reg

)

Definition at line 509 of file isa.cc.

References System::cacheLineSize(), ArmISA::CCREG_C, ArmISA::CCREG_NZ, ArmISA::CCREG_V, ArmISA::daif, DPRINTF, ArmISA::EL3, ArmISA::ELIs32(), ArmISA::FpscrExcMask, ArmISA::FpscrQcMask, ThreadContext::getCpuPtr(), ArmSystem::getGenericTimer(), getGenericTimer(), getGICv3CPUInterface(), BaseCPU::getInterruptController(), ThreadContext::getSystemPtr(), gicv3CpuInterface, haveSecEL2, haveSecurity, haveSVE, haveVirtualization, iGbReg::TxdOp::ic(), ArmISA::INTREG_SP0, ArmISA::INTREG_SP1, ArmISA::INTREG_SP2, ArmISA::isSecure(), ArmISA::mask, ArmISA::MISCREG_ACTLR, ArmISA::MISCREG_AIDR, ArmISA::MISCREG_CCSIDR, ArmISA::MISCREG_CLIDR, ArmISA::MISCREG_CNTFRQ, ArmISA::MISCREG_CNTFRQ_EL0, ArmISA::MISCREG_CNTVOFF, ArmISA::MISCREG_CNTVOFF_EL2, ArmISA::MISCREG_CPACR, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_CPSR_Q, ArmISA::MISCREG_CTR, ArmISA::MISCREG_CTR_EL0, ArmISA::MISCREG_CURRENTEL, ArmISA::MISCREG_DAIF, ArmISA::MISCREG_DBGDIDR, ArmISA::MISCREG_DBGDSCRint, ArmISA::MISCREG_DCZID_EL0, ArmISA::MISCREG_DFAR_S, ArmISA::MISCREG_FPCR, ArmISA::MISCREG_FPSCR, ArmISA::MISCREG_FPSCR_EXC, ArmISA::MISCREG_FPSCR_QC, ArmISA::MISCREG_FPSR, ArmISA::MISCREG_HCPTR, ArmISA::MISCREG_HCR, ArmISA::MISCREG_HCR2, ArmISA::MISCREG_HCR_EL2, ArmISA::MISCREG_HDFAR, ArmISA::MISCREG_HIFAR, ArmISA::MISCREG_ICC_AP0R0, ArmISA::MISCREG_ICC_IGRPEN1_EL3, ArmISA::MISCREG_ICC_PMR_EL1, ArmISA::MISCREG_ICH_AP0R0_EL2, ArmISA::MISCREG_ICH_LR15_EL2, ArmISA::MISCREG_ICH_LRC15, ArmISA::MISCREG_ID_AA64PFR0_EL1, ArmISA::MISCREG_ID_AA64PFR1_EL1, ArmISA::MISCREG_ID_AFR0, ArmISA::MISCREG_ID_PFR0, ArmISA::MISCREG_ID_PFR1, ArmISA::MISCREG_IFAR_S, ArmISA::MISCREG_IMPLEMENTED, ArmISA::MISCREG_ISR, ArmISA::MISCREG_ISR_EL1, ArmISA::MISCREG_JIDR, ArmISA::MISCREG_JMCR, ArmISA::MISCREG_JOSCR, ArmISA::MISCREG_L2CTLR, ArmISA::MISCREG_MIDR, ArmISA::MISCREG_MPIDR, ArmISA::MISCREG_MPIDR_EL1, ArmISA::MISCREG_NSACR, ArmISA::MISCREG_NZCV, ArmISA::MISCREG_PAN, ArmISA::MISCREG_PMCR, ArmISA::MISCREG_PMEVCNTR0_EL0, ArmISA::MISCREG_PMEVTYPER5_EL0, ArmISA::MISCREG_PMINTENSET_EL1, ArmISA::MISCREG_PMOVSSET, ArmISA::MISCREG_PMOVSSET_EL0, ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR, ArmISA::MISCREG_REVIDR, ArmISA::MISCREG_SCR, ArmISA::MISCREG_SCR_EL3, ArmISA::MISCREG_SP_EL0, ArmISA::MISCREG_SP_EL1, ArmISA::MISCREG_SP_EL2, ArmISA::MISCREG_SPSEL, ArmISA::MISCREG_TCMTR, ArmISA::MISCREG_VMPIDR, ArmISA::MISCREG_VMPIDR_EL2, ArmISA::MISCREG_VPIDR, ArmISA::MISCREG_WARN_NOT_FAIL, ArmISA::miscRegInfo, ArmISA::miscRegName, miscRegs, ArmISA::MODE_HYP, ArmISA::MODE_MON, panic, MipsISA::pc, ThreadContext::pcState(), pmu, ThreadContext::readCCReg(), ThreadContext::readIntReg(), ArmISA::BaseISADevice::readMiscReg(), readMiscRegNoEffect(), ArmISA::readMPIDR(), redirectRegVHE(), System::Threads::size(), system, BaseISA::tc, ThreadContext::threadId(), System::threads, ArmISA::unflattenMiscReg(), X86ISA::val, warn, and warn_once.

Referenced by assert32(), assert64(), and setMiscReg().

readMiscRegNoEffect()

RegVal ArmISA::ISA::readMiscRegNoEffect

(

int

misc_reg

)

const

Definition at line 485 of file isa.cc.

References DPRINTF, getMiscIndices(), lookUpMiscReg, ArmISA::mask, ArmISA::miscRegName, miscRegs, ArmISA::NumMiscRegs, X86ISA::reg, and X86ISA::val.

Referenced by addressTranslation(), Gicv3CPUInterface::bpr1(), Gicv3CPUInterface::currEL(), Gicv3CPUInterface::dropPriority(), Gicv3CPUInterface::eoiMaintenanceInterruptStatus(), flattenMiscIndex(), getExecutingAsid(), Gicv3CPUInterface::getHCREL2FMO(), Gicv3CPUInterface::getHCREL2IMO(), Gicv3CPUInterface::getHPPIR1(), Gicv3CPUInterface::getHPPVILR(), Gicv3CPUInterface::groupEnabled(), Gicv3CPUInterface::groupPriorityMask(), Gicv3CPUInterface::highestActiveGroup(), Gicv3CPUInterface::highestActivePriority(), Gicv3CPUInterface::hppiCanPreempt(), Gicv3CPUInterface::hppviCanPreempt(), Gicv3CPUInterface::inSecureState(), Gicv3CPUInterface::isAA64(), Gicv3CPUInterface::isEL3OrMon(), Gicv3CPUInterface::isEOISplitMode(), Gicv3CPUInterface::isSecureBelowEL3(), Gicv3CPUInterface::maintenanceInterruptStatus(), Gicv3CPUInterface::readBankedMiscReg(), Gicv3CPUInterface::readMiscReg(), readMiscReg(), redirectRegVHE(), Gicv3CPUInterface::setMiscReg(), setMiscReg(), Gicv3CPUInterface::virtualActivateIRQ(), Gicv3CPUInterface::virtualDeactivateIRQ(), Gicv3CPUInterface::virtualDropPriority(), Gicv3CPUInterface::virtualFindActive(), Gicv3CPUInterface::virtualGroupPriorityMask(), Gicv3CPUInterface::virtualHighestActivePriority(), Gicv3CPUInterface::virtualIncrementEOICount(), Gicv3CPUInterface::virtualIsEOISplitMode(), and Gicv3CPUInterface::virtualUpdate().

redirectRegVHE()

int ArmISA::ISA::redirectRegVHE ( ThreadContext *  tc, int  misc_reg  )

inline

Returns the enconcing equivalent when VHE is implemented and HCR_EL2.E2H is enabled and executing at EL2.

Definition at line 753 of file isa.hh.

References ArmISA::currEL(), ArmISA::EL2, haveSecEL2, ArmISA::MISCREG_AFSR0_EL1, ArmISA::MISCREG_AFSR0_EL2, ArmISA::MISCREG_AFSR1_EL1, ArmISA::MISCREG_AFSR1_EL2, ArmISA::MISCREG_AMAIR_EL1, ArmISA::MISCREG_AMAIR_EL2, ArmISA::MISCREG_CNTHCTL_EL2, ArmISA::MISCREG_CNTHP_CTL_EL2, ArmISA::MISCREG_CNTHP_CVAL_EL2, ArmISA::MISCREG_CNTHP_TVAL_EL2, ArmISA::MISCREG_CNTHPS_CTL_EL2, ArmISA::MISCREG_CNTHPS_CVAL_EL2, ArmISA::MISCREG_CNTHPS_TVAL_EL2, ArmISA::MISCREG_CNTHV_CTL_EL2, ArmISA::MISCREG_CNTHV_CVAL_EL2, ArmISA::MISCREG_CNTHV_TVAL_EL2, ArmISA::MISCREG_CNTHVS_CTL_EL2, ArmISA::MISCREG_CNTHVS_CVAL_EL2, ArmISA::MISCREG_CNTHVS_TVAL_EL2, ArmISA::MISCREG_CNTKCTL_EL1, ArmISA::MISCREG_CNTP_CTL_EL0, ArmISA::MISCREG_CNTP_CVAL_EL0, ArmISA::MISCREG_CNTP_TVAL_EL0, ArmISA::MISCREG_CNTV_CTL_EL0, ArmISA::MISCREG_CNTV_CVAL_EL0, ArmISA::MISCREG_CNTV_TVAL_EL0, ArmISA::MISCREG_CONTEXTIDR_EL1, ArmISA::MISCREG_CONTEXTIDR_EL2, ArmISA::MISCREG_CPACR_EL1, ArmISA::MISCREG_CPTR_EL2, ArmISA::MISCREG_ELR_EL1, ArmISA::MISCREG_ELR_EL2, ArmISA::MISCREG_ESR_EL1, ArmISA::MISCREG_ESR_EL2, ArmISA::MISCREG_FAR_EL1, ArmISA::MISCREG_FAR_EL2, ArmISA::MISCREG_HCR_EL2, ArmISA::MISCREG_MAIR_EL1, ArmISA::MISCREG_MAIR_EL2, ArmISA::MISCREG_SCR_EL3, ArmISA::MISCREG_SCTLR_EL1, ArmISA::MISCREG_SCTLR_EL2, ArmISA::MISCREG_SPSR_EL1, ArmISA::MISCREG_SPSR_EL2, ArmISA::MISCREG_TCR_EL1, ArmISA::MISCREG_TCR_EL2, ArmISA::MISCREG_TTBR0_EL1, ArmISA::MISCREG_TTBR0_EL2, ArmISA::MISCREG_TTBR1_EL1, ArmISA::MISCREG_TTBR1_EL2, ArmISA::MISCREG_VBAR_EL1, ArmISA::MISCREG_VBAR_EL2, readMiscRegNoEffect(), and BaseISA::tc.

Referenced by readMiscReg(), and setMiscReg().

serialize()

void ArmISA::ISA::serialize ( CheckpointOut &  cp ) const

overridevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters

cp	Checkpoint state

Implements Serializable.

Definition at line 2360 of file isa.cc.

References DPRINTF, ArmISA::miscRegName, miscRegs, ArmISA::NUM_PHYS_MISCREGS, and SERIALIZE_MAPPING.

setMiscReg()

void ArmISA::ISA::setMiscReg	(	int	misc_reg,
		RegVal	val
	)

Definition at line 833 of file isa.cc.

References addressTranslation(), addressTranslation64(), Loader::Arm, ArmISA::asid, assert32(), assert64(), bits(), ArmISA::TLBIOp::broadcast(), ArmISA::CCREG_C, ArmISA::CCREG_NZ, ArmISA::CCREG_V, ArmISA::CpsrMaskQ, ArmISA::MMU::D_TLBS, ArmISA::daif, DPRINTF, ArmISA::el, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, ArmISA::ELIs32(), ArmISA::FpscrExcMask, ArmISA::FpscrQcMask, ThreadContext::getCheckerCpuPtr(), getCurSveVecLenInBits(), ThreadContext::getDecoderPtr(), getGenericTimer(), getGICv3CPUInterface(), ArmISA::getMMUPtr(), haveLargeAsid64, haveLPAE, havePAN, haveSecurity, haveSVE, haveVirtualization, highestELIs64, ArmISA::TLB::HypMode, ArmISA::INTREG_SP0, ArmISA::INTREG_SP1, ArmISA::INTREG_SP2, ArmISA::MMU::invalidateMiscReg(), ArmISA::isSecure(), ArmISA::mask, mbits(), ArmISA::MISCREG_ACTLR, ArmISA::MISCREG_AMAIR0, ArmISA::MISCREG_AMAIR1, ArmISA::MISCREG_AT_S12E0R_Xt, ArmISA::MISCREG_AT_S12E0W_Xt, ArmISA::MISCREG_AT_S12E1R_Xt, ArmISA::MISCREG_AT_S12E1W_Xt, ArmISA::MISCREG_AT_S1E0R_Xt, ArmISA::MISCREG_AT_S1E0W_Xt, ArmISA::MISCREG_AT_S1E1R_Xt, ArmISA::MISCREG_AT_S1E1W_Xt, ArmISA::MISCREG_AT_S1E2R_Xt, ArmISA::MISCREG_AT_S1E2W_Xt, ArmISA::MISCREG_AT_S1E3R_Xt, ArmISA::MISCREG_AT_S1E3W_Xt, ArmISA::MISCREG_ATS12NSOPR, ArmISA::MISCREG_ATS12NSOPW, ArmISA::MISCREG_ATS12NSOUR, ArmISA::MISCREG_ATS12NSOUW, ArmISA::MISCREG_ATS1CPR, ArmISA::MISCREG_ATS1CPW, ArmISA::MISCREG_ATS1CUR, ArmISA::MISCREG_ATS1CUW, ArmISA::MISCREG_ATS1HR, ArmISA::MISCREG_ATS1HW, ArmISA::MISCREG_CNTFRQ, ArmISA::MISCREG_CNTFRQ_EL0, ArmISA::MISCREG_CNTVOFF, ArmISA::MISCREG_CNTVOFF_EL2, ArmISA::MISCREG_CONTEXTIDR, ArmISA::MISCREG_CPACR, ArmISA::MISCREG_CPACR_EL1, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_CPSR_Q, ArmISA::MISCREG_CPTR_EL2, ArmISA::MISCREG_CPTR_EL3, ArmISA::MISCREG_CSSELR, ArmISA::MISCREG_CURRENTEL, ArmISA::MISCREG_DACR, ArmISA::MISCREG_DAIF, ArmISA::MISCREG_DBGBCR0, ArmISA::MISCREG_DBGBCR0_EL1, ArmISA::MISCREG_DBGBCR1, ArmISA::MISCREG_DBGBCR10, ArmISA::MISCREG_DBGBCR10_EL1, ArmISA::MISCREG_DBGBCR11, ArmISA::MISCREG_DBGBCR11_EL1, ArmISA::MISCREG_DBGBCR12, ArmISA::MISCREG_DBGBCR12_EL1, ArmISA::MISCREG_DBGBCR13, ArmISA::MISCREG_DBGBCR13_EL1, ArmISA::MISCREG_DBGBCR14, ArmISA::MISCREG_DBGBCR14_EL1, ArmISA::MISCREG_DBGBCR15, ArmISA::MISCREG_DBGBCR15_EL1, ArmISA::MISCREG_DBGBCR1_EL1, ArmISA::MISCREG_DBGBCR2, ArmISA::MISCREG_DBGBCR2_EL1, ArmISA::MISCREG_DBGBCR3, ArmISA::MISCREG_DBGBCR3_EL1, ArmISA::MISCREG_DBGBCR4, ArmISA::MISCREG_DBGBCR4_EL1, ArmISA::MISCREG_DBGBCR5, ArmISA::MISCREG_DBGBCR5_EL1, ArmISA::MISCREG_DBGBCR6, ArmISA::MISCREG_DBGBCR6_EL1, ArmISA::MISCREG_DBGBCR7, ArmISA::MISCREG_DBGBCR7_EL1, ArmISA::MISCREG_DBGBCR8, ArmISA::MISCREG_DBGBCR8_EL1, ArmISA::MISCREG_DBGBCR9, ArmISA::MISCREG_DBGBCR9_EL1, ArmISA::MISCREG_DBGDSCRext, ArmISA::MISCREG_DBGDSCRint, ArmISA::MISCREG_DBGOSLAR, ArmISA::MISCREG_DBGOSLSR, ArmISA::MISCREG_DBGWCR0, ArmISA::MISCREG_DBGWCR0_EL1, ArmISA::MISCREG_DBGWCR1, ArmISA::MISCREG_DBGWCR10, ArmISA::MISCREG_DBGWCR10_EL1, ArmISA::MISCREG_DBGWCR11, ArmISA::MISCREG_DBGWCR11_EL1, ArmISA::MISCREG_DBGWCR12, ArmISA::MISCREG_DBGWCR12_EL1, ArmISA::MISCREG_DBGWCR13, ArmISA::MISCREG_DBGWCR13_EL1, ArmISA::MISCREG_DBGWCR14, ArmISA::MISCREG_DBGWCR14_EL1, ArmISA::MISCREG_DBGWCR15, ArmISA::MISCREG_DBGWCR15_EL1, ArmISA::MISCREG_DBGWCR1_EL1, ArmISA::MISCREG_DBGWCR2, ArmISA::MISCREG_DBGWCR2_EL1, ArmISA::MISCREG_DBGWCR3, ArmISA::MISCREG_DBGWCR3_EL1, ArmISA::MISCREG_DBGWCR4, ArmISA::MISCREG_DBGWCR4_EL1, ArmISA::MISCREG_DBGWCR5, ArmISA::MISCREG_DBGWCR5_EL1, ArmISA::MISCREG_DBGWCR6, ArmISA::MISCREG_DBGWCR6_EL1, ArmISA::MISCREG_DBGWCR7, ArmISA::MISCREG_DBGWCR7_EL1, ArmISA::MISCREG_DBGWCR8, ArmISA::MISCREG_DBGWCR8_EL1, ArmISA::MISCREG_DBGWCR9, ArmISA::MISCREG_DBGWCR9_EL1, ArmISA::MISCREG_DC_ZVA_Xt, ArmISA::MISCREG_DFAR_S, ArmISA::MISCREG_DFSR, ArmISA::MISCREG_DTLBIALL, ArmISA::MISCREG_DTLBIASID, ArmISA::MISCREG_DTLBIMVA, ArmISA::MISCREG_FPCR, ArmISA::MISCREG_FPEXC, ArmISA::MISCREG_FPSCR, ArmISA::MISCREG_FPSCR_EXC, ArmISA::MISCREG_FPSCR_QC, ArmISA::MISCREG_FPSID, ArmISA::MISCREG_FPSR, ArmISA::MISCREG_HCPTR, ArmISA::MISCREG_HCR, ArmISA::MISCREG_HCR2, ArmISA::MISCREG_HCR_EL2, ArmISA::MISCREG_HDCR, ArmISA::MISCREG_HDFAR, ArmISA::MISCREG_HIFAR, ArmISA::MISCREG_HSCTLR, ArmISA::MISCREG_HSTR, ArmISA::MISCREG_ICC_AP0R0, ArmISA::MISCREG_ICC_IGRPEN1_EL3, ArmISA::MISCREG_ICC_PMR_EL1, ArmISA::MISCREG_ICH_AP0R0_EL2, ArmISA::MISCREG_ICH_LR15_EL2, ArmISA::MISCREG_ICH_LRC15, ArmISA::MISCREG_ID_AA64AFR0_EL1, ArmISA::MISCREG_ID_AA64AFR1_EL1, ArmISA::MISCREG_ID_AA64DFR0_EL1, ArmISA::MISCREG_ID_AA64DFR1_EL1, ArmISA::MISCREG_ID_AA64ISAR0_EL1, ArmISA::MISCREG_ID_AA64ISAR1_EL1, ArmISA::MISCREG_ID_AA64MMFR0_EL1, ArmISA::MISCREG_ID_AA64MMFR1_EL1, ArmISA::MISCREG_ID_AA64MMFR2_EL1, ArmISA::MISCREG_ID_AA64PFR0_EL1, ArmISA::MISCREG_ID_AA64PFR1_EL1, ArmISA::MISCREG_ID_DFR0, ArmISA::MISCREG_ID_ISAR0, ArmISA::MISCREG_ID_ISAR1, ArmISA::MISCREG_ID_ISAR2, ArmISA::MISCREG_ID_ISAR3, ArmISA::MISCREG_ID_ISAR4, ArmISA::MISCREG_ID_ISAR5, ArmISA::MISCREG_ID_MMFR0, ArmISA::MISCREG_ID_MMFR1, ArmISA::MISCREG_ID_MMFR2, ArmISA::MISCREG_ID_MMFR3, ArmISA::MISCREG_ID_MMFR4, ArmISA::MISCREG_ID_PFR0, ArmISA::MISCREG_ID_PFR1, ArmISA::MISCREG_IFAR_S, ArmISA::MISCREG_IFSR, ArmISA::MISCREG_IMPLEMENTED, ArmISA::MISCREG_ITLBIALL, ArmISA::MISCREG_ITLBIASID, ArmISA::MISCREG_ITLBIMVA, ArmISA::MISCREG_L2CTLR, ArmISA::MISCREG_MAIR0, ArmISA::MISCREG_MAIR1, ArmISA::MISCREG_MDCR_EL2, ArmISA::MISCREG_MDCR_EL3, ArmISA::MISCREG_MDSCR_EL1, ArmISA::MISCREG_MIDR, ArmISA::MISCREG_MPIDR, ArmISA::MISCREG_MVFR0, ArmISA::MISCREG_MVFR1, ArmISA::MISCREG_NMRR, ArmISA::MISCREG_NSACR, ArmISA::MISCREG_NZCV, ArmISA::MISCREG_OSLAR_EL1, ArmISA::MISCREG_OSLSR_EL1, ArmISA::MISCREG_PAN, ArmISA::MISCREG_PMCR, ArmISA::MISCREG_PMEVCNTR0_EL0, ArmISA::MISCREG_PMEVTYPER5_EL0, ArmISA::MISCREG_PMINTENSET_EL1, ArmISA::MISCREG_PMOVSSET, ArmISA::MISCREG_PMOVSSET_EL0, ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR, ArmISA::MISCREG_PRRR, ArmISA::MISCREG_SCR, ArmISA::MISCREG_SCR_EL3, ArmISA::MISCREG_SCTLR, ArmISA::MISCREG_SCTLR_EL1, ArmISA::MISCREG_SCTLR_EL2, ArmISA::MISCREG_SCTLR_EL3, ArmISA::MISCREG_SCTLR_NS, ArmISA::MISCREG_SCTLR_S, ArmISA::MISCREG_SDCR, ArmISA::MISCREG_SP_EL0, ArmISA::MISCREG_SP_EL1, ArmISA::MISCREG_SP_EL2, ArmISA::MISCREG_SPSEL, ArmISA::MISCREG_SPSR_EL1, ArmISA::MISCREG_SPSR_EL2, ArmISA::MISCREG_SPSR_EL3, ArmISA::MISCREG_TCR_EL1, ArmISA::MISCREG_TCR_EL2, ArmISA::MISCREG_TCR_EL3, ArmISA::MISCREG_TLBI_ALLE1, ArmISA::MISCREG_TLBI_ALLE1IS, ArmISA::MISCREG_TLBI_ALLE2, ArmISA::MISCREG_TLBI_ALLE2IS, ArmISA::MISCREG_TLBI_ALLE3, ArmISA::MISCREG_TLBI_ALLE3IS, ArmISA::MISCREG_TLBI_ASIDE1_Xt, ArmISA::MISCREG_TLBI_ASIDE1IS_Xt, ArmISA::MISCREG_TLBI_IPAS2E1_Xt, ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt, ArmISA::MISCREG_TLBI_IPAS2LE1_Xt, ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt, ArmISA::MISCREG_TLBI_VAAE1_Xt, ArmISA::MISCREG_TLBI_VAAE1IS_Xt, ArmISA::MISCREG_TLBI_VAALE1_Xt, ArmISA::MISCREG_TLBI_VAALE1IS_Xt, ArmISA::MISCREG_TLBI_VAE1_Xt, ArmISA::MISCREG_TLBI_VAE1IS_Xt, ArmISA::MISCREG_TLBI_VAE2_Xt, ArmISA::MISCREG_TLBI_VAE2IS_Xt, ArmISA::MISCREG_TLBI_VAE3_Xt, ArmISA::MISCREG_TLBI_VAE3IS_Xt, ArmISA::MISCREG_TLBI_VALE1_Xt, ArmISA::MISCREG_TLBI_VALE1IS_Xt, ArmISA::MISCREG_TLBI_VALE2_Xt, ArmISA::MISCREG_TLBI_VALE2IS_Xt, ArmISA::MISCREG_TLBI_VALE3_Xt, ArmISA::MISCREG_TLBI_VALE3IS_Xt, ArmISA::MISCREG_TLBI_VMALLE1, ArmISA::MISCREG_TLBI_VMALLE1IS, ArmISA::MISCREG_TLBI_VMALLS12E1, ArmISA::MISCREG_TLBI_VMALLS12E1IS, ArmISA::MISCREG_TLBIALL, ArmISA::MISCREG_TLBIALLH, ArmISA::MISCREG_TLBIALLHIS, ArmISA::MISCREG_TLBIALLIS, ArmISA::MISCREG_TLBIALLNSNH, ArmISA::MISCREG_TLBIALLNSNHIS, ArmISA::MISCREG_TLBIASID, ArmISA::MISCREG_TLBIASIDIS, ArmISA::MISCREG_TLBIIPAS2, ArmISA::MISCREG_TLBIIPAS2IS, ArmISA::MISCREG_TLBIIPAS2L, ArmISA::MISCREG_TLBIIPAS2LIS, ArmISA::MISCREG_TLBIMVA, ArmISA::MISCREG_TLBIMVAA, ArmISA::MISCREG_TLBIMVAAIS, ArmISA::MISCREG_TLBIMVAAL, ArmISA::MISCREG_TLBIMVAALIS, ArmISA::MISCREG_TLBIMVAH, ArmISA::MISCREG_TLBIMVAHIS, ArmISA::MISCREG_TLBIMVAIS, ArmISA::MISCREG_TLBIMVAL, ArmISA::MISCREG_TLBIMVALH, ArmISA::MISCREG_TLBIMVALHIS, ArmISA::MISCREG_TLBIMVALIS, ArmISA::MISCREG_TLBTR, ArmISA::MISCREG_TTBCR, ArmISA::MISCREG_TTBR0, ArmISA::MISCREG_TTBR0_EL1, ArmISA::MISCREG_TTBR0_EL2, ArmISA::MISCREG_TTBR0_EL3, ArmISA::MISCREG_TTBR1, ArmISA::MISCREG_TTBR1_EL1, ArmISA::MISCREG_TTBR1_EL2, ArmISA::MISCREG_VTTBR, ArmISA::MISCREG_WARN_NOT_FAIL, ArmISA::MISCREG_ZCR_EL1, ArmISA::MISCREG_ZCR_EL2, ArmISA::MISCREG_ZCR_EL3, ArmISA::miscRegInfo, ArmISA::miscRegName, miscRegs, ArmISA::MODE_MON, ArmISA::pan, panic, MipsISA::pc, ThreadContext::pcState(), ThreadContext::pcStateNoRecord(), pmu, MipsISA::r, BaseTLB::Read, ThreadContext::readMiscReg(), readMiscReg(), ThreadContext::readMiscRegNoEffect(), readMiscRegNoEffect(), redirectRegVHE(), ArmISA::TLB::S12E0Tran, ArmISA::TLB::S12E1Tran, ArmISA::TLB::S1CTran, ArmISA::TLB::S1E0Tran, ArmISA::TLB::S1E1Tran, ArmISA::TLB::S1E2Tran, ArmISA::TLB::S1E3Tran, ArmISA::TLB::S1S2NsTran, selfDebug, ArmISA::SelfDebug::setbSDD(), ThreadContext::setCCReg(), ArmISA::SelfDebug::setDebugMask(), ArmISA::SelfDebug::setenableTDETGE(), ThreadContext::setIntReg(), ArmISA::SelfDebug::setMDBGen(), ArmISA::SelfDebug::setMDSCRvals(), ArmISA::BaseISADevice::setMiscReg(), ThreadContext::setMiscReg(), setMiscRegNoEffect(), ArmISA::sp, BaseISA::tc, ArmISA::unflattenMiscReg(), ArmISA::SelfDebug::updateDBGBCR(), ArmISA::SelfDebug::updateDBGWCR(), ArmISA::SelfDebug::updateOSLock(), updateRegMap(), ArmISA::TLB::UserMode, ArmISA::v, X86ISA::val, warn, warn_once, and BaseTLB::Write.

setMiscRegNoEffect()

void ArmISA::ISA::setMiscRegNoEffect	(	int	misc_reg,
		RegVal	val
	)

Definition at line 811 of file isa.cc.

References bits(), DPRINTF, getMiscIndices(), lookUpMiscReg, ArmISA::miscRegName, miscRegs, ArmISA::NumMiscRegs, X86ISA::reg, ArmISA::v, and X86ISA::val.

Referenced by addressTranslation(), addressTranslation64(), Gicv3CPUInterface::dropPriority(), Gicv3CPUInterface::readMiscReg(), Gicv3CPUInterface::setBankedMiscReg(), Gicv3CPUInterface::setMiscReg(), setMiscReg(), Gicv3CPUInterface::virtualActivateIRQ(), Gicv3CPUInterface::virtualDeactivateIRQ(), Gicv3CPUInterface::virtualDropPriority(), and Gicv3CPUInterface::virtualIncrementEOICount().

setupThreadContext()

void ArmISA::ISA::setupThreadContext

(

)

Definition at line 457 of file isa.cc.

References ThreadContext::contextId(), Gicv3::getCPUInterface(), ArmSystem::getGIC(), gicv3CpuInterface, ArmISA::SelfDebug::init(), pmu, selfDebug, ArmISA::BaseISADevice::setThreadContext(), system, and BaseISA::tc.

Referenced by startup(), and takeOverFrom().

snsBankedIndex64()

int ArmISA::ISA::snsBankedIndex64 ( MiscRegIndex  reg, bool  ns  ) const

inline

Definition at line 821 of file isa.hh.

References haveSecurity, ArmISA::MISCREG_BANKED64, ArmISA::miscRegInfo, ArmISA::ns, and X86ISA::reg.

Referenced by flattenMiscIndex(), Gicv3CPUInterface::readBankedMiscReg(), and Gicv3CPUInterface::setBankedMiscReg().

startup()

void ArmISA::ISA::startup ( )

overridevirtual

startup() is the final initialization call before simulation.

All state is initialized (including unserialized state, if any, such as the curTick() value), so this is the appropriate place to schedule initial event(s) for objects that need them.

Reimplemented from SimObject.

Definition at line 440 of file isa.cc.

References afterStartup, haveTME, ThreadContext::setHtmCheckpointPtr(), setupThreadContext(), SimObject::startup(), and BaseISA::tc.

takeOverFrom()

void ArmISA::ISA::takeOverFrom ( ThreadContext *  new_tc, ThreadContext *  old_tc  )

overridevirtual

Reimplemented from BaseISA.

Definition at line 478 of file isa.cc.

References setupThreadContext(), and BaseISA::tc.

unserialize()

void ArmISA::ISA::unserialize ( CheckpointIn &  cp )

overridevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters

cp	Checkpoint state

Implements Serializable.

Definition at line 2367 of file isa.cc.

References DPRINTF, ArmISA::MISCREG_CPSR, ArmISA::miscRegName, miscRegs, ArmISA::NUM_PHYS_MISCREGS, UNSERIALIZE_MAPPING, and updateRegMap().

updateRegMap()

void ArmISA::ISA::updateRegMap ( CPSR  cpsr )

inlineprotected

Definition at line 461 of file isa.hh.

References ArmISA::IntReg64Map, ArmISA::IntRegAbtMap, ArmISA::IntRegFiqMap, ArmISA::IntRegHypMap, ArmISA::IntRegIrqMap, intRegMap, ArmISA::IntRegMonMap, ArmISA::IntRegSvcMap, ArmISA::IntRegUndMap, ArmISA::IntRegUsrMap, ArmISA::MODE_ABORT, ArmISA::MODE_FIQ, ArmISA::MODE_HYP, ArmISA::MODE_IRQ, ArmISA::MODE_MON, ArmISA::MODE_SVC, ArmISA::MODE_SYSTEM, ArmISA::MODE_UNDEFINED, ArmISA::MODE_USER, and panic.

Referenced by clear32(), clear64(), setMiscReg(), and unserialize().

vecRegRenameMode()

Enums::VecRegRenameMode ArmISA::ISA::vecRegRenameMode ( ) const

inline

Definition at line 881 of file isa.hh.

References _vecRegRenameMode.

zeroSveVecRegUpperPart()

void ArmISA::ISA::zeroSveVecRegUpperPart ( VecRegContainer &  vc, unsigned  eCount  )

static

Definition at line 2351 of file isa.cc.

References VecRegContainer< SIZE >::as(), and ArmISA::i.

Member Data Documentation

_decoderFlavor

const Enums::DecoderFlavor ArmISA::ISA::_decoderFlavor

protected

Definition at line 73 of file isa.hh.

Referenced by decoderFlavor().

_vecRegRenameMode

const Enums::VecRegRenameMode ArmISA::ISA::_vecRegRenameMode

protected

Definition at line 74 of file isa.hh.

Referenced by ISA(), and vecRegRenameMode().

afterStartup

bool ArmISA::ISA::afterStartup

protected

Definition at line 112 of file isa.hh.

Referenced by haveGICv3CpuIfc(), and startup().

dummyDevice

DummyISADevice ArmISA::ISA::dummyDevice

protected

Dummy device for to handle non-existing ISA devices.

Definition at line 77 of file isa.hh.

Referenced by ISA().

gicv3CpuInterface

std::unique_ptr<BaseISADevice> ArmISA::ISA::gicv3CpuInterface

protected

Definition at line 86 of file isa.hh.

Referenced by getGICv3CPUInterface(), haveGICv3CpuIfc(), readMiscReg(), and setupThreadContext().

haveCrypto

bool ArmISA::ISA::haveCrypto

protected

Definition at line 93 of file isa.hh.

Referenced by initID32(), initID64(), and ISA().

haveLargeAsid64

bool ArmISA::ISA::haveLargeAsid64

protected

Definition at line 94 of file isa.hh.

Referenced by initID64(), ISA(), and setMiscReg().

haveLPAE

bool ArmISA::ISA::haveLPAE

protected

Definition at line 91 of file isa.hh.

Referenced by addressTranslation(), clear32(), ISA(), and setMiscReg().

haveLSE

bool ArmISA::ISA::haveLSE

protected

Definition at line 97 of file isa.hh.

Referenced by initID64(), and ISA().

havePAN

bool ArmISA::ISA::havePAN

protected

Definition at line 99 of file isa.hh.

Referenced by initializeMiscRegMetadata(), initID64(), ISA(), and setMiscReg().

haveSecEL2

bool ArmISA::ISA::haveSecEL2

protected

Definition at line 100 of file isa.hh.

Referenced by initID64(), ISA(), readMiscReg(), and redirectRegVHE().

haveSecurity

bool ArmISA::ISA::haveSecurity

protected

Definition at line 90 of file isa.hh.

Referenced by clear32(), clear64(), flattenMiscIndex(), getCurSveVecLenInBits(), getMiscIndices(), initializeMiscRegMetadata(), initID64(), ISA(), readMiscReg(), setMiscReg(), and snsBankedIndex64().

haveSVE

bool ArmISA::ISA::haveSVE

protected

Definition at line 96 of file isa.hh.

Referenced by initID64(), ISA(), readMiscReg(), and setMiscReg().

haveTME

bool ArmISA::ISA::haveTME

protected

Definition at line 101 of file isa.hh.

Referenced by initID64(), ISA(), and startup().

haveVHE

bool ArmISA::ISA::haveVHE

protected

Definition at line 98 of file isa.hh.

Referenced by initID64(), and ISA().

haveVirtualization

bool ArmISA::ISA::haveVirtualization

protected

Definition at line 92 of file isa.hh.

Referenced by clear64(), getCurSveVecLenInBits(), initID64(), ISA(), readMiscReg(), and setMiscReg().

highestELIs64

bool ArmISA::ISA::highestELIs64

protected

Definition at line 89 of file isa.hh.

Referenced by flattenMiscIndex(), getMiscIndices(), initializeMiscRegMetadata(), initID32(), ISA(), and setMiscReg().

impdefAsNop

bool ArmISA::ISA::impdefAsNop

protected

If true, accesses to IMPLEMENTATION DEFINED registers are treated as NOP hence not causing UNDEFINED INSTRUCTION.

Definition at line 110 of file isa.hh.

Referenced by initializeMiscRegMetadata().

intRegMap

const IntRegIndex* ArmISA::ISA::intRegMap

protected

Definition at line 458 of file isa.hh.

Referenced by flattenIntIndex(), and updateRegMap().

lookUpMiscReg

std::vector< struct ISA::MiscRegLUTEntry > ArmISA::ISA::lookUpMiscReg

staticprotected

Metadata table accessible via the value of the register.

Definition at line 139 of file isa.hh.

Referenced by getMiscIndices(), InitReg(), readMiscRegNoEffect(), and setMiscRegNoEffect().

miscRegs

RegVal ArmISA::ISA::miscRegs[NumMiscRegs]

protected

Definition at line 457 of file isa.hh.

Referenced by clear(), clear32(), clear64(), flattenIntIndex(), flattenMiscIndex(), getCurSveVecLenInBits(), getMiscIndices(), initID32(), initID64(), inUserMode(), ISA(), readMiscReg(), readMiscRegNoEffect(), serialize(), setMiscReg(), setMiscRegNoEffect(), and unserialize().

physAddrRange

uint8_t ArmISA::ISA::physAddrRange

protected

Definition at line 95 of file isa.hh.

Referenced by initID64(), and ISA().

pmu

BaseISADevice* ArmISA::ISA::pmu

protected

Definition at line 80 of file isa.hh.

Referenced by ISA(), readMiscReg(), setMiscReg(), and setupThreadContext().

selfDebug

SelfDebug* ArmISA::ISA::selfDebug

protected

Definition at line 114 of file isa.hh.

Referenced by getSelfDebug(), ISA(), setMiscReg(), and setupThreadContext().

sveVL

unsigned ArmISA::ISA::sveVL

protected

SVE vector length in quadwords.

Definition at line 104 of file isa.hh.

Referenced by getCurSveVecLenInBits(), getCurSveVecLenInBitsAtReset(), initID64(), and ISA().

system

ArmSystem* ArmISA::ISA::system

protected

Definition at line 70 of file isa.hh.

Referenced by clear(), clear32(), clear64(), getGenericTimer(), initializeMiscRegMetadata(), ISA(), readMiscReg(), and setupThreadContext().

timer

std::unique_ptr<BaseISADevice> ArmISA::ISA::timer

protected

Definition at line 83 of file isa.hh.

Referenced by getGenericTimer().

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The documentation for this class was generated from the following files:

• arch/arm/isa.hh
• arch/arm/isa.cc
• arch/arm/miscregs.cc