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133 #include <sys/signal.h>
149 #include "blobs/gdb_xml_aarch64_core.hh"
150 #include "blobs/gdb_xml_aarch64_fpu.hh"
151 #include "blobs/gdb_xml_aarch64_target.hh"
152 #include "blobs/gdb_xml_arm_core.hh"
153 #include "blobs/gdb_xml_arm_target.hh"
154 #include "blobs/gdb_xml_arm_vfpv3.hh"
158 #include "debug/GDBAcc.hh"
159 #include "debug/GDBMisc.hh"
169 using namespace ArmISA;
176 auto req = std::make_shared<Request>(
addr, 64, 0x40, -1, 0, 0);
191 :
BaseRemoteGDB(_system, _port), regCache32(this), regCache64(this)
204 DPRINTF(GDBAcc,
"acc: %#x mapping is invalid\n",
va);
209 DPRINTF(GDBAcc,
"acc: %#x mapping is valid\n",
va);
221 DPRINTF(GDBAcc,
"getRegs in remotegdb \n");
223 for (
int i = 0;
i < 31; ++
i)
244 DPRINTF(GDBAcc,
"setRegs in remotegdb \n");
246 for (
int i = 0;
i < 31; ++
i)
273 DPRINTF(GDBAcc,
"getRegs in remotegdb \n");
294 for (
int i = 0;
i < 32;
i++)
303 DPRINTF(GDBAcc,
"setRegs in remotegdb \n");
321 pc_state.set(
r.gpr[15]);
333 #define GDB_XML(x, s) \
334 { x, std::string(reinterpret_cast<const char *>(Blobs::s), \
336 static const std::map<std::string, std::string> annexMap32{
337 GDB_XML(
"target.xml", gdb_xml_arm_target),
338 GDB_XML(
"arm-core.xml", gdb_xml_arm_core),
339 GDB_XML(
"arm-vfpv3.xml", gdb_xml_arm_vfpv3),
341 static const std::map<std::string, std::string> annexMap64{
342 GDB_XML(
"target.xml", gdb_xml_aarch64_target),
343 GDB_XML(
"aarch64-core.xml", gdb_xml_aarch64_core),
344 GDB_XML(
"aarch64-fpu.xml", gdb_xml_aarch64_fpu),
348 auto it = annexMap.find(annex);
349 if (it == annexMap.end())
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
constexpr decltype(nullptr) NoFault
void setRegs(ThreadContext *) const
Set the ThreadContext's registers from the values in the raw buffer.
constexpr unsigned NumVecElemPerNeonVecReg
static void output(const char *filename)
virtual BaseMMU * getMMUPtr()=0
RemoteGDB(System *_system, int _port)
const Entry * lookup(Addr vaddr)
Lookup function.
bool inAArch64(ThreadContext *tc)
static bool tryTranslate(ThreadContext *tc, Addr addr)
Concrete subclasses of this abstract class represent how the register values are transmitted on the w...
void setRegs(ThreadContext *) const
Set the ThreadContext's registers from the values in the raw buffer.
Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
This class takes an arbitrary memory region (address/length pair) and generates a series of appropria...
virtual const TheISA::VecRegContainer & readVecReg(const RegId ®) const =0
BaseGdbRegCache * gdbRegs()
bool done() const
Are we done? That is, did the last call to next() advance past the end of the region?
ThreadContext is the external interface to all thread state for anything outside of the CPU.
EmulationPageTable * pTable
bool acc(Addr addr, size_t len)
void getRegs(ThreadContext *)
Fill the raw buffer from the registers in the ThreadContext.
virtual TheISA::VecRegContainer & getWritableVecReg(const RegId ®)=0
virtual TheISA::PCState pcState() const =0
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
AArch64GdbRegCache regCache64
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
virtual RegVal readIntReg(RegIndex reg_idx) const =0
virtual Process * getProcessPtr()=0
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
@ VecRegClass
Vector Register.
AArch32GdbRegCache regCache32
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
const int NumVecV8ArchRegs
bool getXferFeaturesRead(const std::string &annex, std::string &output)
Get an XML target description.
ThreadContext * context()
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
struct gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::GEM5_PACKED r
void getRegs(ThreadContext *)
Fill the raw buffer from the registers in the ThreadContext.
VecElem v[NumVecV8ArchRegs *NumVecElemPerNeonVecReg]
Register ID: describe an architectural register with its class and index.
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
Generated on Tue Sep 21 2021 12:24:39 for gem5 by doxygen 1.8.17