O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buffers between stages. More...

#include <cpu.hh>

Inheritance diagram for gem5::o3::CPU:

Classes
struct	CPUStats

Public Types
enum	Status { Running, Idle, Halted, Blocked, SwitchedOut }

enum	StageIdx { FetchIdx, DecodeIdx, RenameIdx, IEWIdx, CommitIdx, NumStages }
	Enum to give each stage a specific index, so when calling activateStage() or deactivateStage(), they can specify which stage is being activated/deactivated. More...

typedef std::list< DynInstPtr >::iterator	ListIt

using	LSQRequest = LSQ::LSQRequest

Public Types inherited from gem5::ClockedObject
using	Params = ClockedObjectParams
	Parameters of ClockedObject. More...

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Public Member Functions
	CPU (const O3CPUParams &params)
	Constructs a CPU with the given parameters. More...

void	regProbePoints () override
	Register probe points. More...

void	demapPage (Addr vaddr, uint64_t asn)

void	tick ()
	Ticks CPU, calling tick() on each stage, and checking the overall activity to see if the CPU should deschedule itself. More...

void	init () override
	Initialize the CPU. More...

void	startup () override
	startup() is the final initialization call before simulation. More...

int	numActiveThreads ()
	Returns the Number of Active Threads in the CPU. More...

void	activateThread (ThreadID tid)
	Add Thread to Active Threads List. More...

void	deactivateThread (ThreadID tid)
	Remove Thread from Active Threads List. More...

void	insertThread (ThreadID tid)
	Setup CPU to insert a thread's context. More...

void	removeThread (ThreadID tid)
	Remove all of a thread's context from CPU. More...

Counter	totalInsts () const override
	Count the Total Instructions Committed in the CPU. More...

Counter	totalOps () const override
	Count the Total Ops (including micro ops) committed in the CPU. More...

void	activateContext (ThreadID tid) override
	Add Thread to Active Threads List. More...

void	suspendContext (ThreadID tid) override
	Remove Thread from Active Threads List. More...

void	haltContext (ThreadID tid) override
	Remove Thread from Active Threads List && Remove Thread Context from CPU. More...

void	updateThreadPriority ()
	Update The Order In Which We Process Threads. More...

bool	isDraining () const
	Is the CPU draining? More...

void	serializeThread (CheckpointOut &cp, ThreadID tid) const override
	Serialize a single thread. More...

void	unserializeThread (CheckpointIn &cp, ThreadID tid) override
	Unserialize one thread. More...

void	addThreadToExitingList (ThreadID tid)
	Insert tid to the list of threads trying to exit. More...

bool	isThreadExiting (ThreadID tid) const
	Is the thread trying to exit? More...

void	scheduleThreadExitEvent (ThreadID tid)
	If a thread is trying to exit and its corresponding trap event has been completed, schedule an event to terminate the thread. More...

void	exitThreads ()
	Terminate all threads that are ready to exit. More...

DrainState	drain () override
	Starts draining the CPU's pipeline of all instructions in order to stop all memory accesses. More...

void	drainResume () override
	Resumes execution after a drain. More...

void	commitDrained (ThreadID tid)
	Commit has reached a safe point to drain a thread. More...

void	switchOut () override
	Switches out this CPU. More...

void	takeOverFrom (BaseCPU *oldCPU) override
	Takes over from another CPU. More...

void	verifyMemoryMode () const override
	Verify that the system is in a memory mode supported by the CPU. More...

InstSeqNum	getAndIncrementInstSeq ()
	Get the current instruction sequence number, and increment it. More...

void	trap (const Fault &fault, ThreadID tid, const StaticInstPtr &inst)
	Traps to handle given fault. More...

void	setVectorsAsReady (ThreadID tid)
	Mark vector fields in scoreboard as ready right after switching vector mode, since software may read vectors at this time. More...

void	switchRenameMode (ThreadID tid, UnifiedFreeList *freelist)
	Check if a change in renaming is needed for vector registers. More...

Fault	getInterrupts ()
	Returns the Fault for any valid interrupt. More...

void	processInterrupts (const Fault &interrupt)
	Processes any an interrupt fault. More...

void	halt ()
	Halts the CPU. More...

RegVal	readMiscRegNoEffect (int misc_reg, ThreadID tid) const
	Register accessors. More...

RegVal	readMiscReg (int misc_reg, ThreadID tid)
	Reads a misc. More...

void	setMiscRegNoEffect (int misc_reg, RegVal val, ThreadID tid)
	Sets a miscellaneous register. More...

void	setMiscReg (int misc_reg, RegVal val, ThreadID tid)
	Sets a misc. More...

RegVal	readIntReg (PhysRegIdPtr phys_reg)

RegVal	readFloatReg (PhysRegIdPtr phys_reg)

const TheISA::VecRegContainer &	readVecReg (PhysRegIdPtr reg_idx) const

TheISA::VecRegContainer &	getWritableVecReg (PhysRegIdPtr reg_idx)
	Read physical vector register for modification. More...

enums::VecRegRenameMode	vecRenameMode () const
	Returns current vector renaming mode. More...

void	vecRenameMode (enums::VecRegRenameMode vec_mode)
	Sets the current vector renaming mode. More...

const TheISA::VecElem &	readVecElem (PhysRegIdPtr reg_idx) const

const TheISA::VecPredRegContainer &	readVecPredReg (PhysRegIdPtr reg_idx) const

TheISA::VecPredRegContainer &	getWritableVecPredReg (PhysRegIdPtr reg_idx)

RegVal	readCCReg (PhysRegIdPtr phys_reg)

void	setIntReg (PhysRegIdPtr phys_reg, RegVal val)

void	setFloatReg (PhysRegIdPtr phys_reg, RegVal val)

void	setVecReg (PhysRegIdPtr reg_idx, const TheISA::VecRegContainer &val)

void	setVecElem (PhysRegIdPtr reg_idx, const TheISA::VecElem &val)

void	setVecPredReg (PhysRegIdPtr reg_idx, const TheISA::VecPredRegContainer &val)

void	setCCReg (PhysRegIdPtr phys_reg, RegVal val)

RegVal	readArchIntReg (int reg_idx, ThreadID tid)

RegVal	readArchFloatReg (int reg_idx, ThreadID tid)

const TheISA::VecRegContainer &	readArchVecReg (int reg_idx, ThreadID tid) const

TheISA::VecRegContainer &	getWritableArchVecReg (int reg_idx, ThreadID tid)
	Read architectural vector register for modification. More...

const TheISA::VecElem &	readArchVecElem (const RegIndex &reg_idx, const ElemIndex &ldx, ThreadID tid) const

const TheISA::VecPredRegContainer &	readArchVecPredReg (int reg_idx, ThreadID tid) const

TheISA::VecPredRegContainer &	getWritableArchVecPredReg (int reg_idx, ThreadID tid)

RegVal	readArchCCReg (int reg_idx, ThreadID tid)

void	setArchIntReg (int reg_idx, RegVal val, ThreadID tid)
	Architectural register accessors. More...

void	setArchFloatReg (int reg_idx, RegVal val, ThreadID tid)

void	setArchVecPredReg (int reg_idx, const TheISA::VecPredRegContainer &val, ThreadID tid)

void	setArchVecReg (int reg_idx, const TheISA::VecRegContainer &val, ThreadID tid)

void	setArchVecElem (const RegIndex &reg_idx, const ElemIndex &ldx, const TheISA::VecElem &val, ThreadID tid)

void	setArchCCReg (int reg_idx, RegVal val, ThreadID tid)

void	pcState (const TheISA::PCState &newPCState, ThreadID tid)
	Sets the commit PC state of a specific thread. More...

TheISA::PCState	pcState (ThreadID tid)
	Reads the commit PC state of a specific thread. More...

Addr	instAddr (ThreadID tid)
	Reads the commit PC of a specific thread. More...

MicroPC	microPC (ThreadID tid)
	Reads the commit micro PC of a specific thread. More...

Addr	nextInstAddr (ThreadID tid)
	Reads the next PC of a specific thread. More...

void	squashFromTC (ThreadID tid)
	Initiates a squash of all in-flight instructions for a given thread. More...

ListIt	addInst (const DynInstPtr &inst)
	Function to add instruction onto the head of the list of the instructions. More...

void	instDone (ThreadID tid, const DynInstPtr &inst)
	Function to tell the CPU that an instruction has completed. More...

void	removeFrontInst (const DynInstPtr &inst)
	Remove an instruction from the front end of the list. More...

void	removeInstsNotInROB (ThreadID tid)
	Remove all instructions that are not currently in the ROB. More...

void	removeInstsUntil (const InstSeqNum &seq_num, ThreadID tid)
	Remove all instructions younger than the given sequence number. More...

void	squashInstIt (const ListIt &instIt, ThreadID tid)
	Removes the instruction pointed to by the iterator. More...

void	cleanUpRemovedInsts ()
	Cleans up all instructions on the remove list. More...

void	dumpInsts ()
	Debug function to print all instructions on the list. More...

void	activityThisCycle ()
	Records that there was time buffer activity this cycle. More...

void	activateStage (const StageIdx idx)
	Changes a stage's status to active within the activity recorder. More...

void	deactivateStage (const StageIdx idx)
	Changes a stage's status to inactive within the activity recorder. More...

void	wakeCPU ()
	Wakes the CPU, rescheduling the CPU if it's not already active. More...

virtual void	wakeup (ThreadID tid) override

ThreadID	getFreeTid ()
	Gets a free thread id. More...

gem5::ThreadContext *	tcBase (ThreadID tid)
	Returns a pointer to a thread context. More...

Fault	pushRequest (const DynInstPtr &inst, bool isLoad, uint8_t data, unsigned int size, Addr addr, Request::Flags flags, uint64_t res, AtomicOpFunctorPtr amo_op=nullptr, const std::vector< bool > &byte_enable=std::vector< bool >())
	CPU pushRequest function, forwards request to LSQ. More...

Fault	read (LSQRequest *req, int load_idx)
	CPU read function, forwards read to LSQ. More...

Fault	write (LSQRequest req, uint8_t data, int store_idx)
	CPU write function, forwards write to LSQ. More...

Port &	getInstPort () override
	Used by the fetch unit to get a hold of the instruction port. More...

Port &	getDataPort () override
	Get the dcache port (used to find block size for translations). More...

void	htmSendAbortSignal (ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause)

Public Member Functions inherited from gem5::BaseCPU
int	cpuId () const
	Reads this CPU's ID. More...

uint32_t	socketId () const
	Reads this CPU's Socket ID. More...

RequestorID	dataRequestorId () const
	Reads this CPU's unique data requestor ID. More...

RequestorID	instRequestorId () const
	Reads this CPU's unique instruction requestor ID. More...

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port on this CPU. More...

uint32_t	taskId () const
	Get cpu task id. More...

void	taskId (uint32_t id)
	Set cpu task id. More...

uint32_t	getPid () const

void	setPid (uint32_t pid)

void	workItemBegin ()

void	workItemEnd ()

Tick	instCount ()

BaseInterrupts *	getInterruptController (ThreadID tid)

void	postInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupts (ThreadID tid)

bool	checkInterrupts (ThreadID tid) const

Trace::InstTracer *	getTracer ()
	Provide access to the tracer pointer. More...

int	findContext (ThreadContext *tc)
	Given a Thread Context pointer return the thread num. More...

virtual ThreadContext *	getContext (int tn)
	Given a thread num get tho thread context for it. More...

unsigned	numContexts ()
	Get the number of thread contexts available. More...

ThreadID	contextToThread (ContextID cid)
	Convert ContextID to threadID. More...

	PARAMS (BaseCPU)

	BaseCPU (const Params &params, bool is_checker=false)

virtual	~BaseCPU ()

void	regStats () override
	Callback to set stat parameters. More...

void	registerThreadContexts ()

void	deschedulePowerGatingEvent ()

void	schedulePowerGatingEvent ()

void	flushTLBs ()
	Flush all TLBs in the CPU. More...

bool	switchedOut () const
	Determine if the CPU is switched out. More...

unsigned int	cacheLineSize () const
	Get the cache line size of the system. More...

void	serialize (CheckpointOut &cp) const override
	Serialize this object to the given output stream. More...

void	unserialize (CheckpointIn &cp) override
	Reconstruct the state of this object from a checkpoint. More...

void	scheduleInstStop (ThreadID tid, Counter insts, const char *cause)
	Schedule an event that exits the simulation loops after a predefined number of instructions. More...

uint64_t	getCurrentInstCount (ThreadID tid)
	Get the number of instructions executed by the specified thread on this CPU. More...

void	traceFunctions (Addr pc)

void	armMonitor (ThreadID tid, Addr address)

bool	mwait (ThreadID tid, PacketPtr pkt)

void	mwaitAtomic (ThreadID tid, ThreadContext tc, BaseMMU mmu)

AddressMonitor *	getCpuAddrMonitor (ThreadID tid)

virtual void	probeInstCommit (const StaticInstPtr &inst, Addr pc)
	Helper method to trigger PMU probes for a committed instruction. More...

Public Member Functions inherited from gem5::ClockedObject
	ClockedObject (const ClockedObjectParams &p)

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue. More...

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group. More...

virtual	~Group ()

virtual void	resetStats ()
	Callback to reset stats. More...

virtual void	preDumpStats ()
	Callback before stats are dumped. More...

void	addStat (statistics::Info *info)
	Register a stat with this group. More...

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block. More...

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block. More...

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Public Member Functions inherited from gem5::Clocked
void	updateClockPeriod ()
	Update the tick to the current tick. More...

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge. More...

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Public Attributes
BaseMMU *	mmu

Status	_status
	Overall CPU status. More...

ProbePointArg< PacketPtr > *	ppInstAccessComplete

ProbePointArg< std::pair< DynInstPtr, PacketPtr > > *	ppDataAccessComplete

int	instcount
	Count of total number of dynamic instructions in flight. More...

std::list< DynInstPtr >	instList
	List of all the instructions in flight. More...

std::queue< ListIt >	removeList
	List of all the instructions that will be removed at the end of this cycle. More...

bool	removeInstsThisCycle
	Records if instructions need to be removed this cycle due to being retired or squashed. More...

TimeBuffer< TimeStruct >	timeBuffer
	The main time buffer to do backwards communication. More...

TimeBuffer< FetchStruct >	fetchQueue
	The fetch stage's instruction queue. More...

TimeBuffer< DecodeStruct >	decodeQueue
	The decode stage's instruction queue. More...

TimeBuffer< RenameStruct >	renameQueue
	The rename stage's instruction queue. More...

TimeBuffer< IEWStruct >	iewQueue
	The IEW stage's instruction queue. More...

InstSeqNum	globalSeqNum
	The global sequence number counter. More...

gem5::Checker< DynInstPtr > *	checker
	Pointer to the checker, which can dynamically verify instruction results at run time. More...

System *	system
	Pointer to the system. More...

std::vector< ThreadState * >	thread
	Pointers to all of the threads in the CPU. More...

std::list< int >	cpuWaitList
	Threads Scheduled to Enter CPU. More...

Cycles	lastRunningCycle
	The cycle that the CPU was last running, used for statistics. More...

Tick	lastActivatedCycle
	The cycle that the CPU was last activated by a new thread. More...

std::map< ThreadID, unsigned >	threadMap
	Mapping for system thread id to cpu id. More...

std::vector< ThreadID >	tids
	Available thread ids in the cpu. More...

gem5::o3::CPU::CPUStats	cpuStats

Public Attributes inherited from gem5::BaseCPU
ThreadID	numThreads
	Number of threads we're actually simulating (<= SMT_MAX_THREADS). More...

System *	system

gem5::BaseCPU::BaseCPUStats	baseStats

Cycles	syscallRetryLatency

Public Attributes inherited from gem5::ClockedObject
PowerState *	powerState

Protected Attributes
Fetch	fetch
	The fetch stage. More...

Decode	decode
	The decode stage. More...

Rename	rename
	The dispatch stage. More...

IEW	iew
	The issue/execute/writeback stages. More...

Commit	commit
	The commit stage. More...

enums::VecRegRenameMode	vecMode
	The rename mode of the vector registers. More...

PhysRegFile	regFile
	The register file. More...

UnifiedFreeList	freeList
	The free list. More...

UnifiedRenameMap	renameMap [MaxThreads]
	The rename map. More...

UnifiedRenameMap	commitRenameMap [MaxThreads]
	The commit rename map. More...

ROB	rob
	The re-order buffer. More...

std::list< ThreadID >	activeThreads
	Active Threads List. More...

std::unordered_map< ThreadID, bool >	exitingThreads
	This is a list of threads that are trying to exit. More...

Scoreboard	scoreboard
	Integer Register Scoreboard. More...

std::vector< TheISA::ISA * >	isa

Protected Attributes inherited from gem5::BaseCPU
Tick	instCnt
	Instruction count used for SPARC misc register. More...

int	_cpuId

const uint32_t	_socketId
	Each cpu will have a socket ID that corresponds to its physical location in the system. More...

RequestorID	_instRequestorId
	instruction side request id that must be placed in all requests More...

RequestorID	_dataRequestorId
	data side request id that must be placed in all requests More...

uint32_t	_taskId
	An intrenal representation of a task identifier within gem5. More...

uint32_t	_pid
	The current OS process ID that is executing on this processor. More...

bool	_switchedOut
	Is the CPU switched out or active? More...

const unsigned int	_cacheLineSize
	Cache the cache line size that we get from the system. More...

std::vector< BaseInterrupts * >	interrupts

std::vector< ThreadContext * >	threadContexts

Trace::InstTracer *	tracer

Cycles	previousCycle

CPUState	previousState

const Cycles	pwrGatingLatency

const bool	powerGatingOnIdle

EventFunctionWrapper	enterPwrGatingEvent

probing::PMUUPtr	ppRetiredInsts
	Instruction commit probe point. More...

probing::PMUUPtr	ppRetiredInstsPC

probing::PMUUPtr	ppRetiredLoads
	Retired load instructions. More...

probing::PMUUPtr	ppRetiredStores
	Retired store instructions. More...

probing::PMUUPtr	ppRetiredBranches
	Retired branches (any type) More...

probing::PMUUPtr	ppAllCycles
	CPU cycle counter even if any thread Context is suspended. More...

probing::PMUUPtr	ppActiveCycles
	CPU cycle counter, only counts if any thread contexts is active. More...

ProbePointArg< bool > *	ppSleeping
	ProbePoint that signals transitions of threadContexts sets. More...

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Private Member Functions
void	scheduleTickEvent (Cycles delay)
	Schedule tick event, regardless of its current state. More...

void	unscheduleTickEvent ()
	Unschedule tick event, regardless of its current state. More...

bool	tryDrain ()
	Check if the pipeline has drained and signal drain done. More...

void	drainSanityCheck () const
	Perform sanity checks after a drain. More...

bool	isCpuDrained () const
	Check if a system is in a drained state. More...

Private Attributes
EventFunctionWrapper	tickEvent
	The tick event used for scheduling CPU ticks. More...

EventFunctionWrapper	threadExitEvent
	The exit event used for terminating all ready-to-exit threads. More...

ActivityRecorder	activityRec
	The activity recorder; used to tell if the CPU has any activity remaining or if it can go to idle and deschedule itself. More...

Friends
class	ThreadContext

Additional Inherited Members
Static Public Member Functions inherited from gem5::BaseCPU
static int	numSimulatedCPUs ()

static Counter	numSimulatedInsts ()

static Counter	numSimulatedOps ()

Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it. More...

Static Public Attributes inherited from gem5::BaseCPU
static const uint32_t	invldPid = std::numeric_limits<uint32_t>::max()
	Invalid or unknown Pid. More...

Protected Types inherited from gem5::BaseCPU
enum	CPUState { CPU_STATE_ON, CPU_STATE_SLEEP, CPU_STATE_WAKEUP }

Protected Member Functions inherited from gem5::BaseCPU
void	updateCycleCounters (CPUState state)
	base method keeping track of cycle progression More...

void	enterPwrGating ()

probing::PMUUPtr	pmuProbePoint (const char *name)
	Helper method to instantiate probe points belonging to this object. More...

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Member Functions inherited from gem5::Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters. More...

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance. More...

void	resetClock () const
	Reset the object's clock using the current global tick value. More...

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...

Static Protected Attributes inherited from gem5::BaseCPU
static std::unique_ptr< GlobalStats >	globalStats
	Pointer to the global stat structure. More...

Detailed Description

O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buffers between stages.

The tick() function for the CPU is defined here.

Definition at line 95 of file cpu.hh.

Member Typedef Documentation

◆ ListIt

typedef std::list<DynInstPtr>::iterator gem5::o3::CPU::ListIt

Definition at line 98 of file cpu.hh.

◆ LSQRequest

using gem5::o3::CPU::LSQRequest = LSQ::LSQRequest

Definition at line 113 of file cpu.hh.

Member Enumeration Documentation

◆ StageIdx

enum gem5::o3::CPU::StageIdx

Enum to give each stage a specific index, so when calling activateStage() or deactivateStage(), they can specify which stage is being activated/deactivated.

Enumerator
FetchIdx
DecodeIdx
RenameIdx
IEWIdx
CommitIdx
NumStages

Definition at line 535 of file cpu.hh.

◆ Status

enum gem5::o3::CPU::Status

Enumerator
Running
Idle
Halted
Blocked
SwitchedOut

Definition at line 103 of file cpu.hh.

Constructor & Destructor Documentation

◆ CPU()

gem5::o3::CPU::CPU ( const O3CPUParams & params )

Constructs a CPU with the given parameters.

Definition at line 73 of file cpu.cc.

References tick().

Member Function Documentation

◆ activateContext()

void gem5::o3::CPU::activateContext ( ThreadID tid )

overridevirtual

Add Thread to Active Threads List.

Reimplemented from gem5::BaseCPU.

Definition at line 656 of file cpu.cc.

References _status, gem5::BaseCPU::activateContext(), activateThread(), gem5::ActivityRecorder::activity(), activityRec, cpuStats, gem5::Clocked::curCycle(), gem5::curTick(), gem5::Drained, gem5::Drainable::drainState(), fetch, lastActivatedCycle, lastRunningCycle, gem5::o3::CPU::CPUStats::quiesceCycles, Running, scheduleTickEvent(), gem5::BaseCPU::switchedOut(), and gem5::o3::Fetch::wakeFromQuiesce().

Referenced by gem5::o3::ThreadContext::activate(), drain(), and insertThread().

◆ activateStage()

void gem5::o3::CPU::activateStage ( const StageIdx idx )

inline

Changes a stage's status to active within the activity recorder.

Definition at line 572 of file cpu.hh.

References gem5::ActivityRecorder::activateStage(), and activityRec.

Referenced by gem5::o3::IEW::activateStage(), gem5::o3::IEW::startupStage(), gem5::o3::Commit::startupStage(), gem5::o3::Fetch::switchToActive(), gem5::o3::Fetch::updateFetchStatus(), gem5::o3::Decode::updateStatus(), gem5::o3::Commit::updateStatus(), and gem5::o3::Rename::updateStatus().

◆ activateThread()

void gem5::o3::CPU::activateThread ( ThreadID tid )

Add Thread to Active Threads List.

Definition at line 592 of file cpu.cc.

References activeThreads, DPRINTF, and gem5::BaseCPU::switchedOut().

Referenced by activateContext(), and drainResume().

◆ activityThisCycle()

void gem5::o3::CPU::activityThisCycle ( )

inline

Records that there was time buffer activity this cycle.

Definition at line 569 of file cpu.hh.

References gem5::ActivityRecorder::activity(), and activityRec.

Referenced by gem5::o3::IEW::activityThisCycle(), gem5::o3::LSQUnit::completeStore(), gem5::o3::IEW::executeInsts(), gem5::o3::Fetch::finishTranslation(), gem5::o3::InstructionQueue::scheduleReadyInsts(), gem5::o3::Commit::squashFromSquashAfter(), gem5::o3::Commit::squashFromTC(), gem5::o3::Commit::squashFromTrap(), gem5::o3::Commit::startupStage(), gem5::o3::IEW::takeOverFrom(), gem5::o3::Decode::tick(), gem5::o3::Rename::tick(), gem5::o3::Commit::tick(), gem5::o3::IEW::tick(), and gem5::o3::Fetch::tick().

◆ addInst()

CPU::ListIt gem5::o3::CPU::addInst ( const DynInstPtr & inst )

Function to add instruction onto the head of the list of the instructions.

Used when new instructions are fetched.

Definition at line 1412 of file cpu.cc.

References instList.

Referenced by gem5::o3::Fetch::buildInst().

◆ addThreadToExitingList()

void gem5::o3::CPU::addThreadToExitingList ( ThreadID tid )

Insert tid to the list of threads trying to exit.

Definition at line 1656 of file cpu.cc.

References DPRINTF, exitingThreads, gem5::ThreadContext::Halted, gem5::ArmISA::status, and tcBase().

Referenced by gem5::o3::ThreadContext::halt().

◆ cleanUpRemovedInsts()

void gem5::o3::CPU::cleanUpRemovedInsts ( )

Cleans up all instructions on the remove list.

Definition at line 1544 of file cpu.cc.

References DPRINTF, instList, removeInstsThisCycle, and removeList.

Referenced by tick().

◆ commitDrained()

void gem5::o3::CPU::commitDrained ( ThreadID tid )

Commit has reached a safe point to drain a thread.

Commit calls this method to inform the pipeline that it has reached a point where it is not executed microcode and is about to squash uncommitted instructions to fully drain the pipeline.

Definition at line 1046 of file cpu.cc.

References gem5::o3::Fetch::drainStall(), and fetch.

Referenced by gem5::o3::Commit::commitInsts().

◆ deactivateStage()

void gem5::o3::CPU::deactivateStage ( const StageIdx idx )

inline

Changes a stage's status to inactive within the activity recorder.

Definition at line 576 of file cpu.hh.

References activityRec, and gem5::ActivityRecorder::deactivateStage().

Referenced by gem5::o3::IEW::deactivateStage(), gem5::o3::Fetch::switchToInactive(), gem5::o3::Fetch::updateFetchStatus(), gem5::o3::Decode::updateStatus(), gem5::o3::Commit::updateStatus(), and gem5::o3::Rename::updateStatus().

◆ deactivateThread()

void gem5::o3::CPU::deactivateThread ( ThreadID tid )

Remove Thread from Active Threads List.

Definition at line 608 of file cpu.cc.

References activeThreads, commit, gem5::o3::Commit::deactivateThread(), gem5::o3::Fetch::deactivateThread(), DPRINTF, gem5::o3::Commit::executingHtmTransaction(), fetch, and gem5::BaseCPU::switchedOut().

Referenced by haltContext(), and suspendContext().

◆ demapPage()

void gem5::o3::CPU::demapPage	(	Addr	vaddr,
		uint64_t	asn
	)

inline

Definition at line 180 of file cpu.hh.

References gem5::BaseMMU::demapPage(), mmu, and gem5::MipsISA::vaddr.

Referenced by gem5::o3::DynInst::demapPage().

◆ drain()

DrainState gem5::o3::CPU::drain ( )

overridevirtual

Starts draining the CPU's pipeline of all instructions in order to stop all memory accesses.

Implements gem5::Drainable.

Definition at line 921 of file cpu.cc.

References activateContext(), gem5::ActivityRecorder::activity(), activityRec, commit, decodeQueue, gem5::EventManager::deschedule(), gem5::BaseCPU::deschedulePowerGatingEvent(), DPRINTF, gem5::o3::Commit::drain(), gem5::Drained, gem5::Draining, drainSanityCheck(), fetchQueue, gem5::ArmISA::i, iewQueue, isCpuDrained(), renameQueue, gem5::Event::scheduled(), gem5::ThreadContext::Suspended, gem5::BaseCPU::switchedOut(), gem5::ArmISA::t, gem5::BaseCPU::threadContexts, tickEvent, timeBuffer, and wakeCPU().

◆ drainResume()

void gem5::o3::CPU::drainResume ( )

overridevirtual

Resumes execution after a drain.

Reimplemented from gem5::Drainable.

Definition at line 1049 of file cpu.cc.

References _status, activateThread(), gem5::ThreadContext::Active, commit, DPRINTF, gem5::o3::Commit::drainResume(), gem5::o3::Fetch::drainResume(), fetch, gem5::ArmISA::i, Idle, gem5::Clocked::nextCycle(), Running, gem5::EventManager::schedule(), gem5::Event::scheduled(), gem5::BaseCPU::schedulePowerGatingEvent(), gem5::ArmISA::status, gem5::BaseCPU::switchedOut(), thread, tickEvent, and verifyMemoryMode().

◆ drainSanityCheck()

void gem5::o3::CPU::drainSanityCheck ( ) const

private

Perform sanity checks after a drain.

This method is called from drain() when it has determined that the CPU is fully drained when gem5 is compiled with the NDEBUG macro undefined. The intention of this method is to do more extensive tests than the isDrained() method to weed out any draining bugs.

Definition at line 998 of file cpu.cc.

References commit, decode, gem5::o3::Decode::drainSanityCheck(), gem5::o3::IEW::drainSanityCheck(), gem5::o3::Rename::drainSanityCheck(), gem5::o3::Commit::drainSanityCheck(), gem5::o3::Fetch::drainSanityCheck(), fetch, iew, isCpuDrained(), and rename.

Referenced by drain().

◆ dumpInsts()

void gem5::o3::CPU::dumpInsts ( )

Debug function to print all instructions on the list.

Definition at line 1568 of file cpu.cc.

References gem5::cprintf(), and instList.

Referenced by gem5::o3::DynInst::DynInst().

◆ exitThreads()

void gem5::o3::CPU::exitThreads ( )

Terminate all threads that are ready to exit.

Definition at line 1701 of file cpu.cc.

References DPRINTF, exitingThreads, haltContext(), gem5::ThreadContext::Halted, gem5::ThreadContext::setStatus(), and tcBase().

◆ getAndIncrementInstSeq()

InstSeqNum gem5::o3::CPU::getAndIncrementInstSeq ( )

inline

Get the current instruction sequence number, and increment it.

Definition at line 278 of file cpu.hh.

References globalSeqNum.

Referenced by gem5::o3::Fetch::buildInst().

◆ getDataPort()

Port& gem5::o3::CPU::getDataPort ( )

inlineoverridevirtual

Get the dcache port (used to find block size for translations).

Implements gem5::BaseCPU.

Definition at line 658 of file cpu.hh.

References gem5::o3::LSQ::getDataPort(), iew, and gem5::o3::IEW::ldstQueue.

◆ getFreeTid()

ThreadID gem5::o3::CPU::getFreeTid ( )

Gets a free thread id.

Use if thread ids change across system.

Definition at line 1627 of file cpu.cc.

References gem5::InvalidThreadID, gem5::BaseCPU::numThreads, and tids.

◆ getInstPort()

Port& gem5::o3::CPU::getInstPort ( )

inlineoverridevirtual

Used by the fetch unit to get a hold of the instruction port.

Implements gem5::BaseCPU.

Definition at line 651 of file cpu.hh.

References fetch, and gem5::o3::Fetch::getInstPort().

Referenced by gem5::o3::Fetch::takeOverFrom().

◆ getInterrupts()

Fault gem5::o3::CPU::getInterrupts ( )

Returns the Fault for any valid interrupt.

Definition at line 879 of file cpu.cc.

References gem5::BaseCPU::interrupts.

Referenced by gem5::o3::Commit::handleInterrupt(), and gem5::o3::Commit::propagateInterrupt().

◆ getWritableArchVecPredReg()

TheISA::VecPredRegContainer & gem5::o3::CPU::getWritableArchVecPredReg	(	int	reg_idx,
		ThreadID	tid
	)

Definition at line 1300 of file cpu.cc.

References commitRenameMap, getWritableVecPredReg(), gem5::o3::UnifiedRenameMap::lookup(), and gem5::VecPredRegClass.

Referenced by gem5::o3::ThreadContext::getWritableVecPredRegFlat().

◆ getWritableArchVecReg()

TheISA::VecRegContainer & gem5::o3::CPU::getWritableArchVecReg	(	int	reg_idx,
		ThreadID	tid
	)

Read architectural vector register for modification.

Definition at line 1275 of file cpu.cc.

References commitRenameMap, getWritableVecReg(), gem5::o3::UnifiedRenameMap::lookup(), and gem5::VecRegClass.

Referenced by gem5::o3::ThreadContext::getWritableVecRegFlat().

◆ getWritableVecPredReg()

TheISA::VecPredRegContainer & gem5::o3::CPU::getWritableVecPredReg ( PhysRegIdPtr reg_idx )

Definition at line 1190 of file cpu.cc.

References cpuStats, gem5::o3::PhysRegFile::getWritableVecPredReg(), regFile, and gem5::o3::CPU::CPUStats::vecPredRegfileWrites.

Referenced by getWritableArchVecPredReg(), and gem5::o3::DynInst::getWritableVecPredRegOperand().

◆ getWritableVecReg()

TheISA::VecRegContainer & gem5::o3::CPU::getWritableVecReg ( PhysRegIdPtr reg_idx )

Read physical vector register for modification.

Definition at line 1169 of file cpu.cc.

References cpuStats, gem5::o3::PhysRegFile::getWritableVecReg(), regFile, and gem5::o3::CPU::CPUStats::vecRegfileWrites.

Referenced by getWritableArchVecReg(), and gem5::o3::DynInst::getWritableVecRegOperand().

◆ halt()

void gem5::o3::CPU::halt ( )

inline

Halts the CPU.

Definition at line 305 of file cpu.hh.

References panic.

◆ haltContext()

void gem5::o3::CPU::haltContext ( ThreadID tid )

overridevirtual

Remove Thread from Active Threads List && Remove Thread Context from CPU.

Reimplemented from gem5::BaseCPU.

Definition at line 714 of file cpu.cc.

References _status, activeThreads, gem5::BaseCPU::CPU_STATE_SLEEP, gem5::Clocked::curCycle(), deactivateThread(), DPRINTF, Idle, lastRunningCycle, removeThread(), gem5::Event::scheduled(), gem5::BaseCPU::switchedOut(), tickEvent, unscheduleTickEvent(), and gem5::BaseCPU::updateCycleCounters().

Referenced by exitThreads().

◆ htmSendAbortSignal()

void gem5::o3::CPU::htmSendAbortSignal	(	ThreadID	tid,
		uint64_t	htm_uid,
		HtmFailureFaultCause	cause
	)

◆ init()

void gem5::o3::CPU::init ( )

overridevirtual

Initialize the CPU.

Reimplemented from gem5::BaseCPU.

Definition at line 560 of file cpu.cc.

References commit, gem5::BaseCPU::init(), gem5::BaseCPU::numThreads, gem5::o3::Commit::setThreads(), and thread.

◆ insertThread()

void gem5::o3::CPU::insertThread ( ThreadID tid )

Setup CPU to insert a thread's context.

Definition at line 736 of file cpu.cc.

References activateContext(), gem5::ThreadContext::Active, gem5::CCRegClass, commit, DPRINTF, gem5::FloatRegClass, freeList, gem5::FullSystem, gem5::o3::UnifiedFreeList::getCCReg(), gem5::o3::UnifiedFreeList::getFloatReg(), gem5::o3::UnifiedFreeList::getIntReg(), gem5::IntRegClass, isa, gem5::ThreadContext::pcState(), pcState(), renameMap, gem5::o3::ROB::resetEntries(), gem5::o3::Commit::rob, scoreboard, gem5::o3::UnifiedRenameMap::setEntry(), gem5::o3::Scoreboard::setReg(), gem5::ThreadContext::setStatus(), system, tcBase(), and gem5::System::threads.

◆ instAddr()

Addr gem5::o3::CPU::instAddr ( ThreadID tid )

Reads the commit PC of a specific thread.

Definition at line 1387 of file cpu.cc.

References commit, and gem5::o3::Commit::instAddr().

Referenced by gem5::o3::ThreadContext::instAddr().

◆ instDone()

void gem5::o3::CPU::instDone	(	ThreadID	tid,
		const DynInstPtr &	inst
	)

Function to tell the CPU that an instruction has completed.

Definition at line 1420 of file cpu.cc.

References gem5::o3::CPU::CPUStats::committedInsts, gem5::o3::CPU::CPUStats::committedOps, cpuStats, gem5::BaseCPU::probeInstCommit(), and thread.

Referenced by gem5::o3::Commit::updateComInstStats().

◆ isCpuDrained()

bool gem5::o3::CPU::isCpuDrained ( ) const

private

Check if a system is in a drained state.

Definition at line 1009 of file cpu.cc.

References commit, decode, DPRINTF, fetch, iew, instList, gem5::o3::Decode::isDrained(), gem5::o3::IEW::isDrained(), gem5::o3::Rename::isDrained(), gem5::o3::Commit::isDrained(), gem5::o3::Fetch::isDrained(), removeList, and rename.

Referenced by drain(), drainSanityCheck(), and tryDrain().

◆ isDraining()

bool gem5::o3::CPU::isDraining ( ) const

inline

Is the CPU draining?

Definition at line 232 of file cpu.hh.

References gem5::Draining, and gem5::Drainable::drainState().

Referenced by gem5::o3::Fetch::checkStall(), gem5::o3::Fetch::drainStall(), and gem5::o3::ThreadContext::suspend().

◆ isThreadExiting()

bool gem5::o3::CPU::isThreadExiting ( ThreadID tid ) const

Is the thread trying to exit?

Definition at line 1675 of file cpu.cc.

References exitingThreads.

Referenced by gem5::o3::Commit::commit(), and gem5::o3::ROB::doSquash().

◆ microPC()

MicroPC gem5::o3::CPU::microPC ( ThreadID tid )

Reads the commit micro PC of a specific thread.

Definition at line 1399 of file cpu.cc.

References commit, and gem5::o3::Commit::microPC().

Referenced by gem5::o3::ThreadContext::microPC().

◆ nextInstAddr()

Addr gem5::o3::CPU::nextInstAddr ( ThreadID tid )

Reads the next PC of a specific thread.

Definition at line 1393 of file cpu.cc.

References commit, and gem5::o3::Commit::nextInstAddr().

Referenced by gem5::o3::ThreadContext::nextInstAddr().

◆ numActiveThreads()

int gem5::o3::CPU::numActiveThreads ( )

inline

Returns the Number of Active Threads in the CPU.

Definition at line 196 of file cpu.hh.

References activeThreads.

◆ pcState() [1/2]

void gem5::o3::CPU::pcState	(	const TheISA::PCState &	newPCState,
		ThreadID	tid
	)

Sets the commit PC state of a specific thread.

Definition at line 1381 of file cpu.cc.

References commit, gem5::o3::Commit::pcState(), and gem5::X86ISA::val.

Referenced by gem5::o3::Fetch::clearStates(), insertThread(), gem5::o3::ThreadContext::pcState(), gem5::o3::ThreadContext::pcStateNoRecord(), gem5::o3::Fetch::resetStage(), and switchRenameMode().

◆ pcState() [2/2]

TheISA::PCState gem5::o3::CPU::pcState ( ThreadID tid )

Reads the commit PC state of a specific thread.

Definition at line 1375 of file cpu.cc.

References commit, and gem5::o3::Commit::pcState().

◆ processInterrupts()

void gem5::o3::CPU::processInterrupts ( const Fault & interrupt )

Processes any an interrupt fault.

Definition at line 886 of file cpu.cc.

References DPRINTF, gem5::BaseCPU::interrupts, gem5::NoFault, and trap().

Referenced by gem5::o3::Commit::handleInterrupt().

◆ pushRequest()

Fault gem5::o3::CPU::pushRequest	(	const DynInstPtr &	inst,
		bool	isLoad,
		uint8_t *	data,
		unsigned int	size,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res,
		AtomicOpFunctorPtr	amo_op = `nullptr`,
		const std::vector< bool > &	byte_enable = `std::vector<bool>()`
	)

inline

CPU pushRequest function, forwards request to LSQ.

Definition at line 626 of file cpu.hh.

References gem5::X86ISA::addr, data, iew, gem5::o3::IEW::ldstQueue, and gem5::o3::LSQ::pushRequest().

Referenced by gem5::o3::DynInst::initiateHtmCmd(), gem5::o3::DynInst::initiateMemAMO(), gem5::o3::DynInst::initiateMemRead(), and gem5::o3::DynInst::writeMem().

◆ read()

Fault gem5::o3::CPU::read	(	LSQRequest *	req,
		int	load_idx
	)

inline

CPU read function, forwards read to LSQ.

Definition at line 638 of file cpu.hh.

References iew, gem5::o3::IEW::ldstQueue, and gem5::o3::LSQ::read().

Referenced by gem5::o3::LSQ::pushRequest().

◆ readArchCCReg()

RegVal gem5::o3::CPU::readArchCCReg	(	int	reg_idx,
		ThreadID	tid
	)

Definition at line 1308 of file cpu.cc.

References gem5::CCRegClass, gem5::o3::CPU::CPUStats::ccRegfileReads, commitRenameMap, cpuStats, gem5::o3::UnifiedRenameMap::lookup(), gem5::o3::PhysRegFile::readCCReg(), and regFile.

Referenced by gem5::o3::ThreadContext::readCCRegFlat().

◆ readArchFloatReg()

RegVal gem5::o3::CPU::readArchFloatReg	(	int	reg_idx,
		ThreadID	tid
	)

Definition at line 1257 of file cpu.cc.

References commitRenameMap, cpuStats, gem5::FloatRegClass, gem5::o3::CPU::CPUStats::fpRegfileReads, gem5::o3::UnifiedRenameMap::lookup(), gem5::o3::PhysRegFile::readFloatReg(), and regFile.

Referenced by gem5::o3::ThreadContext::readFloatRegFlat().

◆ readArchIntReg()

RegVal gem5::o3::CPU::readArchIntReg	(	int	reg_idx,
		ThreadID	tid
	)

Definition at line 1247 of file cpu.cc.

References commitRenameMap, cpuStats, gem5::IntRegClass, gem5::o3::CPU::CPUStats::intRegfileReads, gem5::o3::UnifiedRenameMap::lookup(), gem5::o3::PhysRegFile::readIntReg(), and regFile.

Referenced by gem5::o3::ThreadContext::readIntRegFlat().

◆ readArchVecElem()

const TheISA::VecElem & gem5::o3::CPU::readArchVecElem	(	const RegIndex &	reg_idx,
		const ElemIndex &	ldx,
		ThreadID	tid
	)		const

Definition at line 1283 of file cpu.cc.

References commitRenameMap, gem5::o3::UnifiedRenameMap::lookup(), readVecElem(), and gem5::VecElemClass.

Referenced by gem5::o3::ThreadContext::readVecElemFlat().

◆ readArchVecPredReg()

const TheISA::VecPredRegContainer & gem5::o3::CPU::readArchVecPredReg	(	int	reg_idx,
		ThreadID	tid
	)		const

Definition at line 1292 of file cpu.cc.

References commitRenameMap, gem5::o3::UnifiedRenameMap::lookup(), readVecPredReg(), and gem5::VecPredRegClass.

Referenced by gem5::o3::ThreadContext::readVecPredRegFlat().

◆ readArchVecReg()

const TheISA::VecRegContainer & gem5::o3::CPU::readArchVecReg	(	int	reg_idx,
		ThreadID	tid
	)		const

Definition at line 1267 of file cpu.cc.

References commitRenameMap, gem5::o3::UnifiedRenameMap::lookup(), readVecReg(), and gem5::VecRegClass.

Referenced by gem5::o3::ThreadContext::readVecRegFlat().

◆ readCCReg()

RegVal gem5::o3::CPU::readCCReg ( PhysRegIdPtr phys_reg )

Definition at line 1197 of file cpu.cc.

References gem5::o3::CPU::CPUStats::ccRegfileReads, cpuStats, gem5::o3::PhysRegFile::readCCReg(), and regFile.

Referenced by gem5::o3::DynInst::readCCRegOperand().

◆ readFloatReg()

RegVal gem5::o3::CPU::readFloatReg ( PhysRegIdPtr phys_reg )

Definition at line 1155 of file cpu.cc.

References cpuStats, gem5::o3::CPU::CPUStats::fpRegfileReads, gem5::o3::PhysRegFile::readFloatReg(), and regFile.

Referenced by gem5::o3::DynInst::readFloatRegOperandBits().

◆ readIntReg()

RegVal gem5::o3::CPU::readIntReg ( PhysRegIdPtr phys_reg )

Definition at line 1148 of file cpu.cc.

References cpuStats, gem5::o3::CPU::CPUStats::intRegfileReads, gem5::o3::PhysRegFile::readIntReg(), and regFile.

Referenced by gem5::o3::DynInst::readIntRegOperand().

◆ readMiscReg()

RegVal gem5::o3::CPU::readMiscReg	(	int	misc_reg,
		ThreadID	tid
	)

Reads a misc.

register, including any side effects the read might have as defined by the architecture.

Definition at line 1128 of file cpu.cc.

References cpuStats, isa, and gem5::o3::CPU::CPUStats::miscRegfileReads.

Referenced by gem5::o3::ThreadContext::readMiscReg(), gem5::o3::DynInst::readMiscReg(), and gem5::o3::DynInst::readMiscRegOperand().

◆ readMiscRegNoEffect()

RegVal gem5::o3::CPU::readMiscRegNoEffect	(	int	misc_reg,
		ThreadID	tid
	)		const

Register accessors.

Index refers to the physical register index. Reads a miscellaneous register.

Definition at line 1122 of file cpu.cc.

References isa.

Referenced by gem5::o3::ThreadContext::readMiscRegNoEffect().

◆ readVecElem()

const TheISA::VecElem & gem5::o3::CPU::readVecElem ( PhysRegIdPtr reg_idx ) const

Definition at line 1176 of file cpu.cc.

References cpuStats, gem5::o3::PhysRegFile::readVecElem(), regFile, and gem5::o3::CPU::CPUStats::vecRegfileReads.

Referenced by readArchVecElem(), and gem5::o3::DynInst::readVecElemOperand().

◆ readVecPredReg()

const TheISA::VecPredRegContainer & gem5::o3::CPU::readVecPredReg ( PhysRegIdPtr reg_idx ) const

Definition at line 1183 of file cpu.cc.

References cpuStats, gem5::o3::PhysRegFile::readVecPredReg(), regFile, and gem5::o3::CPU::CPUStats::vecPredRegfileReads.

Referenced by readArchVecPredReg(), and gem5::o3::DynInst::readVecPredRegOperand().

◆ readVecReg()

const TheISA::VecRegContainer & gem5::o3::CPU::readVecReg ( PhysRegIdPtr reg_idx ) const

Definition at line 1162 of file cpu.cc.

References cpuStats, gem5::o3::PhysRegFile::readVecReg(), regFile, and gem5::o3::CPU::CPUStats::vecRegfileReads.

Referenced by readArchVecReg(), and gem5::o3::DynInst::readVecRegOperand().

◆ regProbePoints()

void gem5::o3::CPU::regProbePoints ( )

overridevirtual

Register probe points.

Reimplemented from gem5::BaseCPU.

Definition at line 358 of file cpu.cc.

References commit, fetch, gem5::SimObject::getProbeManager(), iew, ppDataAccessComplete, ppInstAccessComplete, gem5::o3::Rename::regProbePoints(), gem5::o3::IEW::regProbePoints(), gem5::o3::Commit::regProbePoints(), gem5::o3::Fetch::regProbePoints(), gem5::BaseCPU::regProbePoints(), and rename.

◆ removeFrontInst()

void gem5::o3::CPU::removeFrontInst ( const DynInstPtr & inst )

Remove an instruction from the front end of the list.

There's no restriction on location of the instruction.

Definition at line 1439 of file cpu.cc.

References DPRINTF, removeInstsThisCycle, and removeList.

Referenced by gem5::o3::ROB::retireHead().

◆ removeInstsNotInROB()

void gem5::o3::CPU::removeInstsNotInROB ( ThreadID tid )

Remove all instructions that are not currently in the ROB.

There's also an option to not squash delay slot instructions.

Definition at line 1452 of file cpu.cc.

References DPRINTF, instList, gem5::o3::ROB::isEmpty(), gem5::o3::ROB::readTailInst(), removeInstsThisCycle, rob, and squashInstIt().

Referenced by gem5::o3::Fetch::squash().

◆ removeInstsUntil()

void gem5::o3::CPU::removeInstsUntil	(	const InstSeqNum &	seq_num,
		ThreadID	tid
	)

Remove all instructions younger than the given sequence number.

Definition at line 1496 of file cpu.cc.

References DPRINTF, instList, removeInstsThisCycle, and squashInstIt().

Referenced by gem5::o3::Decode::squash(), and gem5::o3::Fetch::squashFromDecode().

◆ removeThread()

void gem5::o3::CPU::removeThread ( ThreadID tid )

Remove all of a thread's context from CPU.

Definition at line 785 of file cpu.cc.

References gem5::o3::Decode::clearStates(), gem5::o3::IEW::clearStates(), gem5::o3::Rename::clearStates(), gem5::o3::Commit::clearStates(), gem5::o3::Fetch::clearStates(), commit, decode, decodeQueue, DPRINTF, fetch, fetchQueue, gem5::o3::InstructionQueue::getCount(), gem5::o3::LSQ::getCount(), gem5::ArmISA::i, iew, iewQueue, gem5::o3::IEW::instQueue, gem5::o3::ROB::isEmpty(), gem5::o3::IEW::ldstQueue, rename, renameQueue, gem5::o3::Commit::rob, and timeBuffer.

Referenced by haltContext().

◆ scheduleThreadExitEvent()

void gem5::o3::CPU::scheduleThreadExitEvent ( ThreadID tid )

If a thread is trying to exit and its corresponding trap event has been completed, schedule an event to terminate the thread.

Definition at line 1681 of file cpu.cc.

References exitingThreads, gem5::Clocked::nextCycle(), gem5::EventManager::schedule(), gem5::Event::scheduled(), and threadExitEvent.

Referenced by gem5::o3::Commit::commit().

◆ scheduleTickEvent()

void gem5::o3::CPU::scheduleTickEvent ( Cycles delay )

inlineprivate

Schedule tick event, regardless of its current state.

Definition at line 127 of file cpu.hh.

References gem5::Clocked::clockEdge(), gem5::EventManager::reschedule(), gem5::EventManager::schedule(), gem5::Event::scheduled(), gem5::Event::squashed(), and tickEvent.

Referenced by activateContext().

◆ serializeThread()

void gem5::o3::CPU::serializeThread	(	CheckpointOut &	cp,
		ThreadID	tid
	)		const

overridevirtual

Serialize a single thread.

Parameters

cp	The stream to serialize to.
tid	ID of the current thread.

Reimplemented from gem5::BaseCPU.

Definition at line 909 of file cpu.cc.

References thread.

◆ setArchCCReg()

void gem5::o3::CPU::setArchCCReg	(	int	reg_idx,
		RegVal	val,
		ThreadID	tid
	)

Definition at line 1365 of file cpu.cc.

References gem5::CCRegClass, gem5::o3::CPU::CPUStats::ccRegfileWrites, commitRenameMap, cpuStats, gem5::o3::UnifiedRenameMap::lookup(), regFile, gem5::o3::PhysRegFile::setCCReg(), and gem5::X86ISA::val.

Referenced by gem5::o3::ThreadContext::setCCRegFlat().

◆ setArchFloatReg()

void gem5::o3::CPU::setArchFloatReg	(	int	reg_idx,
		RegVal	val,
		ThreadID	tid
	)

Definition at line 1328 of file cpu.cc.

References commitRenameMap, cpuStats, gem5::FloatRegClass, gem5::o3::CPU::CPUStats::fpRegfileWrites, gem5::o3::UnifiedRenameMap::lookup(), regFile, gem5::o3::PhysRegFile::setFloatReg(), and gem5::X86ISA::val.

Referenced by gem5::o3::ThreadContext::setFloatRegFlat().

◆ setArchIntReg()

void gem5::o3::CPU::setArchIntReg	(	int	reg_idx,
		RegVal	val,
		ThreadID	tid
	)

Architectural register accessors.

Looks up in the commit rename table to obtain the true physical index of the architected register first, then accesses that physical register.

Definition at line 1318 of file cpu.cc.

References commitRenameMap, cpuStats, gem5::IntRegClass, gem5::o3::CPU::CPUStats::intRegfileWrites, gem5::o3::UnifiedRenameMap::lookup(), regFile, gem5::o3::PhysRegFile::setIntReg(), and gem5::X86ISA::val.

Referenced by gem5::o3::ThreadContext::setIntRegFlat().

◆ setArchVecElem()

void gem5::o3::CPU::setArchVecElem	(	const RegIndex &	reg_idx,
		const ElemIndex &	ldx,
		const TheISA::VecElem &	val,
		ThreadID	tid
	)

Definition at line 1347 of file cpu.cc.

References commitRenameMap, gem5::o3::UnifiedRenameMap::lookup(), setVecElem(), gem5::X86ISA::val, and gem5::VecElemClass.

Referenced by gem5::o3::ThreadContext::setVecElemFlat().

◆ setArchVecPredReg()

void gem5::o3::CPU::setArchVecPredReg	(	int	reg_idx,
		const TheISA::VecPredRegContainer &	val,
		ThreadID	tid
	)

Definition at line 1356 of file cpu.cc.

References commitRenameMap, gem5::o3::UnifiedRenameMap::lookup(), setVecPredReg(), gem5::X86ISA::val, and gem5::VecPredRegClass.

Referenced by gem5::o3::ThreadContext::setVecPredRegFlat().

◆ setArchVecReg()

void gem5::o3::CPU::setArchVecReg	(	int	reg_idx,
		const TheISA::VecRegContainer &	val,
		ThreadID	tid
	)

Definition at line 1338 of file cpu.cc.

References commitRenameMap, gem5::o3::UnifiedRenameMap::lookup(), setVecReg(), gem5::X86ISA::val, and gem5::VecRegClass.

Referenced by gem5::o3::ThreadContext::setVecRegFlat().

◆ setCCReg()

void gem5::o3::CPU::setCCReg	(	PhysRegIdPtr	phys_reg,
		RegVal	val
	)

Definition at line 1240 of file cpu.cc.

References gem5::o3::CPU::CPUStats::ccRegfileWrites, cpuStats, regFile, gem5::o3::PhysRegFile::setCCReg(), and gem5::X86ISA::val.

Referenced by gem5::o3::DynInst::setCCRegOperand().

◆ setFloatReg()

void gem5::o3::CPU::setFloatReg	(	PhysRegIdPtr	phys_reg,
		RegVal	val
	)

Definition at line 1211 of file cpu.cc.

References cpuStats, gem5::o3::CPU::CPUStats::fpRegfileWrites, regFile, gem5::o3::PhysRegFile::setFloatReg(), and gem5::X86ISA::val.

Referenced by gem5::o3::DynInst::setFloatRegOperandBits().

◆ setIntReg()

void gem5::o3::CPU::setIntReg	(	PhysRegIdPtr	phys_reg,
		RegVal	val
	)

Definition at line 1204 of file cpu.cc.

References cpuStats, gem5::o3::CPU::CPUStats::intRegfileWrites, regFile, gem5::o3::PhysRegFile::setIntReg(), and gem5::X86ISA::val.

Referenced by gem5::o3::DynInst::setIntRegOperand().

◆ setMiscReg()

void gem5::o3::CPU::setMiscReg	(	int	misc_reg,
		RegVal	val,
		ThreadID	tid
	)

Sets a misc.

register, including any side effects the write might have as defined by the architecture.

Definition at line 1141 of file cpu.cc.

References cpuStats, isa, gem5::o3::CPU::CPUStats::miscRegfileWrites, and gem5::X86ISA::val.

Referenced by gem5::o3::ThreadContext::setMiscReg(), and gem5::o3::DynInst::updateMiscRegs().

◆ setMiscRegNoEffect()

void gem5::o3::CPU::setMiscRegNoEffect	(	int	misc_reg,
		RegVal	val,
		ThreadID	tid
	)

Sets a miscellaneous register.

Definition at line 1135 of file cpu.cc.

References isa, and gem5::X86ISA::val.

Referenced by gem5::o3::ThreadContext::setMiscRegNoEffect().

◆ setVecElem()

void gem5::o3::CPU::setVecElem	(	PhysRegIdPtr	reg_idx,
		const TheISA::VecElem &	val
	)

Definition at line 1225 of file cpu.cc.

References cpuStats, regFile, gem5::o3::PhysRegFile::setVecElem(), gem5::X86ISA::val, and gem5::o3::CPU::CPUStats::vecRegfileWrites.

Referenced by setArchVecElem(), and gem5::o3::DynInst::setVecElemOperand().

◆ setVecPredReg()

void gem5::o3::CPU::setVecPredReg	(	PhysRegIdPtr	reg_idx,
		const TheISA::VecPredRegContainer &	val
	)

Definition at line 1232 of file cpu.cc.

References cpuStats, regFile, gem5::o3::PhysRegFile::setVecPredReg(), gem5::X86ISA::val, and gem5::o3::CPU::CPUStats::vecPredRegfileWrites.

Referenced by setArchVecPredReg(), and gem5::o3::DynInst::setVecPredRegOperand().

◆ setVecReg()

void gem5::o3::CPU::setVecReg	(	PhysRegIdPtr	reg_idx,
		const TheISA::VecRegContainer &	val
	)

Definition at line 1218 of file cpu.cc.

References cpuStats, regFile, gem5::o3::PhysRegFile::setVecReg(), gem5::X86ISA::val, and gem5::o3::CPU::CPUStats::vecRegfileWrites.

Referenced by setArchVecReg(), and gem5::o3::DynInst::setVecRegOperand().

◆ setVectorsAsReady()

void gem5::o3::CPU::setVectorsAsReady ( ThreadID tid )

Mark vector fields in scoreboard as ready right after switching vector mode, since software may read vectors at this time.

Definition at line 837 of file cpu.cc.

References commitRenameMap, gem5::ArmISA::e, isa, scoreboard, gem5::o3::Scoreboard::setReg(), gem5::ArmISA::v, gem5::VecElemClass, vecMode, and gem5::VecRegClass.

Referenced by switchRenameMode().

◆ squashFromTC()

void gem5::o3::CPU::squashFromTC ( ThreadID tid )

Initiates a squash of all in-flight instructions for a given thread.

The source of the squash is an external update of state through the TC.

Definition at line 1405 of file cpu.cc.

References commit, gem5::o3::Commit::generateTCEvent(), and thread.

Referenced by gem5::o3::ThreadContext::conditionalSquash().

◆ squashInstIt()

void gem5::o3::CPU::squashInstIt	(	const ListIt &	instIt,
		ThreadID	tid
	)

Removes the instruction pointed to by the iterator.

Definition at line 1524 of file cpu.cc.

References DPRINTF, and removeList.

Referenced by removeInstsNotInROB(), and removeInstsUntil().

◆ startup()

void gem5::o3::CPU::startup ( )

overridevirtual

startup() is the final initialization call before simulation.

All state is initialized (including unserialized state, if any, such as the curTick() value), so this is the appropriate place to schedule initial event(s) for objects that need them.

Reimplemented from gem5::BaseCPU.

Definition at line 580 of file cpu.cc.

References commit, decode, fetch, iew, rename, gem5::BaseCPU::startup(), gem5::o3::Decode::startupStage(), gem5::o3::IEW::startupStage(), gem5::o3::Rename::startupStage(), gem5::o3::Commit::startupStage(), and gem5::o3::Fetch::startupStage().

◆ suspendContext()

void gem5::o3::CPU::suspendContext ( ThreadID tid )

overridevirtual

Remove Thread from Active Threads List.

Reimplemented from gem5::BaseCPU.

Definition at line 694 of file cpu.cc.

References _status, activeThreads, gem5::Clocked::curCycle(), deactivateThread(), DPRINTF, Idle, lastRunningCycle, gem5::BaseCPU::suspendContext(), gem5::BaseCPU::switchedOut(), and unscheduleTickEvent().

Referenced by gem5::o3::ThreadContext::suspend().

◆ switchOut()

void gem5::o3::CPU::switchOut ( )

overridevirtual

Switches out this CPU.

Reimplemented from gem5::BaseCPU.

Definition at line 1078 of file cpu.cc.

References _status, activityRec, checker, DPRINTF, gem5::ActivityRecorder::reset(), SwitchedOut, and gem5::BaseCPU::switchOut().

◆ switchRenameMode()

void gem5::o3::CPU::switchRenameMode	(	ThreadID	tid,
		UnifiedFreeList *	freelist
	)

Check if a change in renaming is needed for vector registers.

The vecMode variable is updated and propagated to rename maps.

Parameters

tid	ThreadID
freelist	list of free registers

Definition at line 860 of file cpu.cc.

References commitRenameMap, isa, gem5::MipsISA::pc, pcState(), renameMap, setVectorsAsReady(), gem5::o3::UnifiedRenameMap::switchFreeList(), gem5::o3::UnifiedRenameMap::switchMode(), thread, and vecMode.

Referenced by gem5::o3::Rename::doSquash().

◆ takeOverFrom()

void gem5::o3::CPU::takeOverFrom ( BaseCPU * oldCPU )

overridevirtual

Takes over from another CPU.

Reimplemented from gem5::BaseCPU.

Definition at line 1092 of file cpu.cc.

References _status, commit, gem5::Clocked::curCycle(), decode, fetch, globalSeqNum, Idle, iew, lastRunningCycle, rename, gem5::Event::scheduled(), gem5::o3::Decode::takeOverFrom(), gem5::o3::IEW::takeOverFrom(), gem5::o3::Rename::takeOverFrom(), gem5::o3::Commit::takeOverFrom(), gem5::o3::Fetch::takeOverFrom(), gem5::BaseCPU::takeOverFrom(), and tickEvent.

◆ tcBase()

gem5::ThreadContext* gem5::o3::CPU::tcBase ( ThreadID tid )

inline

Returns a pointer to a thread context.

Definition at line 590 of file cpu.hh.

References thread.

Referenced by addThreadToExitingList(), gem5::o3::Fetch::buildInst(), exitThreads(), gem5::o3::LSQUnit::getLatestHtmUid(), gem5::o3::LSQUnit::insertLoad(), insertThread(), gem5::o3::LSQUnit::read(), gem5::o3::LSQUnit::squash(), and gem5::o3::LSQUnit::writebackStores().

◆ tick()

void gem5::o3::CPU::tick ( )

Ticks CPU, calling tick() on each stage, and checking the overall activity to see if the CPU should deschedule itself.

Definition at line 502 of file cpu.cc.

References _status, gem5::ActivityRecorder::active(), activityRec, gem5::ActivityRecorder::advance(), gem5::BaseCPU::baseStats, cleanUpRemovedInsts(), gem5::Clocked::clockEdge(), commit, gem5::BaseCPU::CPU_STATE_ON, cpuStats, gem5::Clocked::curCycle(), decode, decodeQueue, DPRINTF, gem5::Drained, gem5::Drainable::drainState(), fetch, fetchQueue, gem5::FullSystem, Idle, iew, iewQueue, lastRunningCycle, gem5::BaseCPU::BaseCPUStats::numCycles, removeInstsThisCycle, rename, renameQueue, gem5::EventManager::schedule(), gem5::Event::scheduled(), SwitchedOut, gem5::BaseCPU::switchedOut(), gem5::o3::Decode::tick(), gem5::o3::Rename::tick(), gem5::o3::Commit::tick(), gem5::o3::IEW::tick(), gem5::o3::Fetch::tick(), tickEvent, timeBuffer, gem5::o3::CPU::CPUStats::timesIdled, tryDrain(), gem5::BaseCPU::updateCycleCounters(), and updateThreadPriority().

Referenced by CPU().

◆ totalInsts()

Counter gem5::o3::CPU::totalInsts ( ) const

overridevirtual

Count the Total Instructions Committed in the CPU.

Implements gem5::BaseCPU.

Definition at line 632 of file cpu.cc.

References gem5::ArmISA::i, thread, and gem5::statistics::total.

◆ totalOps()

Counter gem5::o3::CPU::totalOps ( ) const

overridevirtual

Count the Total Ops (including micro ops) committed in the CPU.

Implements gem5::BaseCPU.

Definition at line 644 of file cpu.cc.

References gem5::ArmISA::i, thread, and gem5::statistics::total.

◆ trap()

void gem5::o3::CPU::trap	(	const Fault &	fault,
		ThreadID	tid,
		const StaticInstPtr &	inst
	)

Traps to handle given fault.

Definition at line 902 of file cpu.cc.

References gem5::BaseCPU::threadContexts.

Referenced by gem5::o3::Commit::commitHead(), processInterrupts(), and gem5::o3::DynInst::trap().

◆ tryDrain()

bool gem5::o3::CPU::tryDrain ( )

private

Check if the pipeline has drained and signal drain done.

This method checks if a drain has been requested and if the CPU has drained successfully (i.e., there are no instructions in the pipeline). If the CPU has drained, it deschedules the tick event and signals the drain manager.

Returns: False if a drain hasn't been requested or the CPU hasn't drained, true otherwise.

Definition at line 983 of file cpu.cc.

References gem5::EventManager::deschedule(), DPRINTF, gem5::Draining, gem5::Drainable::drainState(), isCpuDrained(), gem5::Event::scheduled(), gem5::Drainable::signalDrainDone(), and tickEvent.

Referenced by tick().

◆ unscheduleTickEvent()

void gem5::o3::CPU::unscheduleTickEvent ( )

inlineprivate

Unschedule tick event, regardless of its current state.

Definition at line 136 of file cpu.hh.

References gem5::Event::scheduled(), gem5::Event::squash(), and tickEvent.

Referenced by haltContext(), and suspendContext().

◆ unserializeThread()

void gem5::o3::CPU::unserializeThread	(	CheckpointIn &	cp,
		ThreadID	tid
	)

overridevirtual

Unserialize one thread.

Parameters

cp	The checkpoint use.
tid	ID of the current thread.

Reimplemented from gem5::BaseCPU.

Definition at line 915 of file cpu.cc.

References thread.

◆ updateThreadPriority()

void gem5::o3::CPU::updateThreadPriority ( )

Update The Order In Which We Process Threads.

Definition at line 1640 of file cpu.cc.

References activeThreads.

Referenced by tick().

◆ vecRenameMode() [1/2]

enums::VecRegRenameMode gem5::o3::CPU::vecRenameMode ( ) const

inline

Returns current vector renaming mode.

Definition at line 337 of file cpu.hh.

References vecMode.

Referenced by gem5::o3::ThreadContext::copyArchRegs().

◆ vecRenameMode() [2/2]

void gem5::o3::CPU::vecRenameMode ( enums::VecRegRenameMode vec_mode )

inline

Sets the current vector renaming mode.

Definition at line 340 of file cpu.hh.

References vecMode.

◆ verifyMemoryMode()

void gem5::o3::CPU::verifyMemoryMode ( ) const

overridevirtual

Verify that the system is in a memory mode supported by the CPU.

Implementations are expected to query the system for the current memory mode and ensure that it is what the CPU model expects. If the check fails, the implementation should terminate the simulation using fatal().

Reimplemented from gem5::BaseCPU.

Definition at line 1113 of file cpu.cc.

References fatal, gem5::System::isTimingMode(), and system.

Referenced by drainResume().

◆ wakeCPU()

void gem5::o3::CPU::wakeCPU ( )

Wakes the CPU, rescheduling the CPU if it's not already active.

Definition at line 1594 of file cpu.cc.

References gem5::ActivityRecorder::active(), activityRec, gem5::BaseCPU::baseStats, gem5::Clocked::clockEdge(), cpuStats, gem5::Clocked::curCycle(), DPRINTF, gem5::o3::CPU::CPUStats::idleCycles, lastRunningCycle, gem5::BaseCPU::BaseCPUStats::numCycles, gem5::EventManager::schedule(), gem5::Event::scheduled(), and tickEvent.

Referenced by gem5::o3::InstructionQueue::cacheUnblocked(), gem5::o3::LSQUnit::completeStore(), drain(), gem5::o3::Fetch::finishTranslation(), gem5::o3::Fetch::processCacheCompletion(), gem5::o3::IEW::wakeCPU(), and wakeup().

◆ wakeup()

void gem5::o3::CPU::wakeup ( ThreadID tid )

overridevirtual

Implements gem5::BaseCPU.

Definition at line 1615 of file cpu.cc.

References DPRINTF, gem5::ArmISA::status, gem5::ThreadContext::Suspended, thread, gem5::BaseCPU::threadContexts, and wakeCPU().

Referenced by gem5::o3::LSQ::DcachePort::recvTimingSnoopReq().

◆ write()

Fault gem5::o3::CPU::write	(	LSQRequest *	req,
		uint8_t *	data,
		int	store_idx
	)

inline

CPU write function, forwards write to LSQ.

Definition at line 644 of file cpu.hh.

References data, iew, gem5::o3::IEW::ldstQueue, and gem5::o3::LSQ::write().

Referenced by gem5::o3::LSQ::pushRequest().

Friends And Related Function Documentation

◆ ThreadContext

friend class ThreadContext

friend

Definition at line 100 of file cpu.hh.

Member Data Documentation

◆ _status

Status gem5::o3::CPU::_status

Overall CPU status.

Definition at line 116 of file cpu.hh.

Referenced by activateContext(), drainResume(), haltContext(), suspendContext(), switchOut(), takeOverFrom(), and tick().

◆ activeThreads

std::list<ThreadID> gem5::o3::CPU::activeThreads

protected

Active Threads List.

Definition at line 516 of file cpu.hh.

Referenced by activateThread(), deactivateThread(), haltContext(), numActiveThreads(), suspendContext(), and updateThreadPriority().

◆ activityRec

ActivityRecorder gem5::o3::CPU::activityRec

private

The activity recorder; used to tell if the CPU has any activity remaining or if it can go to idle and deschedule itself.

Definition at line 565 of file cpu.hh.

Referenced by activateContext(), activateStage(), activityThisCycle(), deactivateStage(), drain(), switchOut(), tick(), and wakeCPU().

◆ checker

gem5::Checker<DynInstPtr>* gem5::o3::CPU::checker

Pointer to the checker, which can dynamically verify instruction results at run time.

This can be set to NULL if it is not being used.

Definition at line 602 of file cpu.hh.

Referenced by gem5::o3::Commit::commitHead(), gem5::o3::Commit::commitInsts(), gem5::o3::DynInst::completeAcc(), gem5::o3::LSQUnit::completeStore(), gem5::o3::Commit::handleInterrupt(), gem5::o3::LSQ::pushRequest(), gem5::o3::IEW::startupStage(), gem5::o3::LSQUnit::storePostSend(), and switchOut().

◆ commit

Commit gem5::o3::CPU::commit

protected

The commit stage.

Definition at line 495 of file cpu.hh.

Referenced by deactivateThread(), drain(), drainResume(), drainSanityCheck(), htmSendAbortSignal(), init(), insertThread(), instAddr(), isCpuDrained(), microPC(), nextInstAddr(), pcState(), regProbePoints(), removeThread(), squashFromTC(), startup(), takeOverFrom(), and tick().

◆ commitRenameMap

UnifiedRenameMap gem5::o3::CPU::commitRenameMap[MaxThreads]

protected

The commit rename map.

Definition at line 510 of file cpu.hh.

Referenced by getWritableArchVecPredReg(), getWritableArchVecReg(), readArchCCReg(), readArchFloatReg(), readArchIntReg(), readArchVecElem(), readArchVecPredReg(), readArchVecReg(), setArchCCReg(), setArchFloatReg(), setArchIntReg(), setArchVecElem(), setArchVecPredReg(), setArchVecReg(), setVectorsAsReady(), and switchRenameMode().

◆ cpuStats

gem5::o3::CPU::CPUStats gem5::o3::CPU::cpuStats

◆ cpuWaitList

std::list<int> gem5::o3::CPU::cpuWaitList

Threads Scheduled to Enter CPU.

Definition at line 611 of file cpu.hh.

◆ decode

Decode gem5::o3::CPU::decode

protected

The decode stage.

Definition at line 486 of file cpu.hh.

Referenced by drainSanityCheck(), isCpuDrained(), removeThread(), startup(), takeOverFrom(), and tick().

◆ decodeQueue

TimeBuffer<DecodeStruct> gem5::o3::CPU::decodeQueue

The decode stage's instruction queue.

Definition at line 552 of file cpu.hh.

Referenced by drain(), removeThread(), and tick().

◆ exitingThreads

std::unordered_map<ThreadID, bool> gem5::o3::CPU::exitingThreads

protected

This is a list of threads that are trying to exit.

Each thread id is mapped to a boolean value denoting whether the thread is ready to exit.

Definition at line 523 of file cpu.hh.

Referenced by addThreadToExitingList(), exitThreads(), isThreadExiting(), and scheduleThreadExitEvent().

◆ fetch

Fetch gem5::o3::CPU::fetch

protected

The fetch stage.

Definition at line 483 of file cpu.hh.

Referenced by activateContext(), commitDrained(), deactivateThread(), drainResume(), drainSanityCheck(), gem5::o3::ThreadContext::getDecoderPtr(), getInstPort(), isCpuDrained(), regProbePoints(), removeThread(), startup(), takeOverFrom(), and tick().

◆ fetchQueue

TimeBuffer<FetchStruct> gem5::o3::CPU::fetchQueue

The fetch stage's instruction queue.

Definition at line 549 of file cpu.hh.

Referenced by drain(), removeThread(), and tick().

◆ freeList

UnifiedFreeList gem5::o3::CPU::freeList

protected

The free list.

Definition at line 504 of file cpu.hh.

Referenced by insertThread().

◆ globalSeqNum

InstSeqNum gem5::o3::CPU::globalSeqNum

The global sequence number counter.

Definition at line 596 of file cpu.hh.

Referenced by getAndIncrementInstSeq(), and takeOverFrom().

◆ iew

IEW gem5::o3::CPU::iew

protected

The issue/execute/writeback stages.

Definition at line 492 of file cpu.hh.

Referenced by drainSanityCheck(), getDataPort(), htmSendAbortSignal(), isCpuDrained(), pushRequest(), read(), regProbePoints(), removeThread(), startup(), takeOverFrom(), tick(), and write().

◆ iewQueue

TimeBuffer<IEWStruct> gem5::o3::CPU::iewQueue

The IEW stage's instruction queue.

Definition at line 558 of file cpu.hh.

Referenced by drain(), removeThread(), and tick().

◆ instcount

int gem5::o3::CPU::instcount

Count of total number of dynamic instructions in flight.

Definition at line 458 of file cpu.hh.

Referenced by gem5::o3::DynInst::DynInst(), and gem5::o3::DynInst::~DynInst().

◆ instList

std::list<DynInstPtr> gem5::o3::CPU::instList

List of all the instructions in flight.

Definition at line 462 of file cpu.hh.

Referenced by addInst(), cleanUpRemovedInsts(), dumpInsts(), gem5::o3::Commit::handleInterrupt(), isCpuDrained(), removeInstsNotInROB(), and removeInstsUntil().

◆ isa

std::vector<TheISA::ISA *> gem5::o3::CPU::isa

protected

Definition at line 528 of file cpu.hh.

Referenced by gem5::o3::ThreadContext::clearArchRegs(), gem5::o3::ThreadContext::flattenRegId(), gem5::o3::ThreadContext::getIsaPtr(), insertThread(), readMiscReg(), readMiscRegNoEffect(), setMiscReg(), setMiscRegNoEffect(), setVectorsAsReady(), and switchRenameMode().

◆ lastActivatedCycle

Tick gem5::o3::CPU::lastActivatedCycle

The cycle that the CPU was last activated by a new thread.

Definition at line 617 of file cpu.hh.

Referenced by activateContext().

◆ lastRunningCycle

Cycles gem5::o3::CPU::lastRunningCycle

The cycle that the CPU was last running, used for statistics.

Definition at line 614 of file cpu.hh.

Referenced by activateContext(), haltContext(), suspendContext(), takeOverFrom(), tick(), and wakeCPU().

◆ mmu

BaseMMU* gem5::o3::CPU::mmu

Definition at line 112 of file cpu.hh.

Referenced by demapPage(), gem5::o3::Fetch::fetchCacheLine(), gem5::o3::ThreadContext::getMMUPtr(), gem5::o3::LSQUnit::getMMUPtr(), and gem5::o3::DynInst::mwaitAtomic().

◆ ppDataAccessComplete

ProbePointArg<std::pair<DynInstPtr, PacketPtr> >* gem5::o3::CPU::ppDataAccessComplete

Definition at line 174 of file cpu.hh.

Referenced by gem5::o3::LSQUnit::completeDataAccess(), and regProbePoints().

◆ ppInstAccessComplete

ProbePointArg<PacketPtr>* gem5::o3::CPU::ppInstAccessComplete

Definition at line 173 of file cpu.hh.

Referenced by gem5::o3::Fetch::processCacheCompletion(), and regProbePoints().

◆ regFile

PhysRegFile gem5::o3::CPU::regFile

protected

The register file.

Definition at line 501 of file cpu.hh.

Referenced by getWritableVecPredReg(), getWritableVecReg(), readArchCCReg(), readArchFloatReg(), readArchIntReg(), readCCReg(), readFloatReg(), readIntReg(), readVecElem(), readVecPredReg(), readVecReg(), setArchCCReg(), setArchFloatReg(), setArchIntReg(), setCCReg(), setFloatReg(), setIntReg(), setVecElem(), setVecPredReg(), and setVecReg().

◆ removeInstsThisCycle

bool gem5::o3::CPU::removeInstsThisCycle

Records if instructions need to be removed this cycle due to being retired or squashed.

Definition at line 479 of file cpu.hh.

Referenced by cleanUpRemovedInsts(), removeFrontInst(), removeInstsNotInROB(), removeInstsUntil(), and tick().

◆ removeList

std::queue<ListIt> gem5::o3::CPU::removeList

List of all the instructions that will be removed at the end of this cycle.

Definition at line 467 of file cpu.hh.

Referenced by cleanUpRemovedInsts(), isCpuDrained(), removeFrontInst(), and squashInstIt().

◆ rename

Rename gem5::o3::CPU::rename

protected

The dispatch stage.

Definition at line 489 of file cpu.hh.

Referenced by drainSanityCheck(), isCpuDrained(), regProbePoints(), removeThread(), startup(), takeOverFrom(), and tick().

◆ renameMap

UnifiedRenameMap gem5::o3::CPU::renameMap[MaxThreads]

protected

The rename map.

Definition at line 507 of file cpu.hh.

Referenced by insertThread(), and switchRenameMode().

◆ renameQueue

TimeBuffer<RenameStruct> gem5::o3::CPU::renameQueue

The rename stage's instruction queue.

Definition at line 555 of file cpu.hh.

Referenced by drain(), removeThread(), and tick().

◆ rob

ROB gem5::o3::CPU::rob

protected

The re-order buffer.

Definition at line 513 of file cpu.hh.

Referenced by removeInstsNotInROB().

◆ scoreboard

Scoreboard gem5::o3::CPU::scoreboard

protected

Integer Register Scoreboard.

Definition at line 526 of file cpu.hh.

Referenced by insertThread(), and setVectorsAsReady().

◆ system

System* gem5::o3::CPU::system

Pointer to the system.

Definition at line 605 of file cpu.hh.

Referenced by gem5::o3::Fetch::finishTranslation(), gem5::o3::ThreadContext::getSystemPtr(), insertThread(), and verifyMemoryMode().

◆ thread

std::vector<ThreadState *> gem5::o3::CPU::thread

Pointers to all of the threads in the CPU.

Definition at line 608 of file cpu.hh.

Referenced by gem5::o3::Fetch::buildInst(), gem5::o3::LSQUnit::checkSnoop(), drainResume(), gem5::o3::Fetch::fetchCacheLine(), htmSendAbortSignal(), init(), instDone(), serializeThread(), squashFromTC(), switchRenameMode(), tcBase(), totalInsts(), totalOps(), unserializeThread(), and wakeup().

◆ threadExitEvent

EventFunctionWrapper gem5::o3::CPU::threadExitEvent

private

The exit event used for terminating all ready-to-exit threads.

Definition at line 124 of file cpu.hh.

Referenced by scheduleThreadExitEvent().

◆ threadMap

std::map<ThreadID, unsigned> gem5::o3::CPU::threadMap

Mapping for system thread id to cpu id.

Definition at line 620 of file cpu.hh.

◆ tickEvent

EventFunctionWrapper gem5::o3::CPU::tickEvent

private

The tick event used for scheduling CPU ticks.

Definition at line 121 of file cpu.hh.

Referenced by drain(), drainResume(), haltContext(), scheduleTickEvent(), takeOverFrom(), tick(), tryDrain(), unscheduleTickEvent(), and wakeCPU().

◆ tids

std::vector<ThreadID> gem5::o3::CPU::tids

Available thread ids in the cpu.

Definition at line 623 of file cpu.hh.

Referenced by getFreeTid().

◆ timeBuffer

TimeBuffer<TimeStruct> gem5::o3::CPU::timeBuffer

The main time buffer to do backwards communication.

Definition at line 546 of file cpu.hh.

Referenced by drain(), removeThread(), and tick().

◆ vecMode

enums::VecRegRenameMode gem5::o3::CPU::vecMode

protected

The rename mode of the vector registers.

Definition at line 498 of file cpu.hh.

Referenced by setVectorsAsReady(), switchRenameMode(), and vecRenameMode().

The documentation for this class was generated from the following files:

cpu/o3/cpu.hh
cpu/o3/cpu.cc

Classes

Public Types

Public Member Functions

Public Attributes

Protected Attributes

Private Member Functions

Private Attributes

Friends

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ ListIt

◆ LSQRequest

Member Enumeration Documentation

◆ StageIdx

◆ Status

Constructor & Destructor Documentation

◆ CPU()

Member Function Documentation

◆ activateContext()

◆ activateStage()

◆ activateThread()

◆ activityThisCycle()

◆ addInst()

◆ addThreadToExitingList()

◆ cleanUpRemovedInsts()

◆ commitDrained()

◆ deactivateStage()

◆ deactivateThread()

◆ demapPage()

◆ drain()

◆ drainResume()

◆ drainSanityCheck()

◆ dumpInsts()

◆ exitThreads()

◆ getAndIncrementInstSeq()

◆ getDataPort()

◆ getFreeTid()

◆ getInstPort()

◆ getInterrupts()

◆ getWritableArchVecPredReg()

◆ getWritableArchVecReg()

◆ getWritableVecPredReg()

◆ getWritableVecReg()

◆ halt()

◆ haltContext()

◆ htmSendAbortSignal()

◆ init()

◆ insertThread()

◆ instAddr()

◆ instDone()

◆ isCpuDrained()

◆ isDraining()

◆ isThreadExiting()

◆ microPC()

◆ nextInstAddr()

◆ numActiveThreads()

◆ pcState() [1/2]

◆ pcState() [2/2]

◆ processInterrupts()

◆ pushRequest()

◆ read()

◆ readArchCCReg()

◆ readArchFloatReg()

◆ readArchIntReg()

◆ readArchVecElem()

◆ readArchVecPredReg()

◆ readArchVecReg()

◆ readCCReg()

◆ readFloatReg()

◆ readIntReg()

◆ readMiscReg()

◆ readMiscRegNoEffect()

◆ readVecElem()

◆ readVecPredReg()

◆ readVecReg()

◆ regProbePoints()

◆ removeFrontInst()

◆ removeInstsNotInROB()

◆ removeInstsUntil()