elastic_trace.hh

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/*
 * Copyright (c) 2013 - 2015 ARM Limited
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 *
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 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
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 * modified or unmodified, in source code or in binary form.
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 * met: redistributions of source code must retain the above copyright
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 * redistributions in binary form must reproduce the above copyright
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#ifndef __CPU_O3_PROBE_ELASTIC_TRACE_HH__
#define __CPU_O3_PROBE_ELASTIC_TRACE_HH__
 
#include <set>
#include <unordered_map>
#include <utility>
 
#include "base/statistics.hh"
#include "cpu/o3/dyn_inst_ptr.hh"
#include "cpu/reg_class.hh"
#include "mem/request.hh"
#include "params/ElasticTrace.hh"
#include "proto/inst_dep_record.pb.h"
#include "proto/packet.pb.h"
#include "proto/protoio.hh"
#include "sim/eventq.hh"
#include "sim/probe/probe.hh"
 
namespace gem5
{
 
namespace o3
{
 
class CPU;
 
class ElasticTrace : public ProbeListenerObject
{
 
  public:
    typedef typename std::pair<InstSeqNum, RegIndex> SeqNumRegPair;
 
    typedef ProtoMessage::InstDepRecord::RecordType RecordType;
    typedef ProtoMessage::InstDepRecord Record;
 
    ElasticTrace(const ElasticTraceParams &params);
 
    void regProbeListeners();
 
    void regEtraceListeners();
 
    void flushTraces();
 
    void fetchReqTrace(const RequestPtr &req);
 
    void recordExecTick(const DynInstConstPtr& dyn_inst);
 
    void recordToCommTick(const DynInstConstPtr& dyn_inst);
 
    void updateRegDep(const DynInstConstPtr& dyn_inst);
 
    void removeRegDepMapEntry(const SeqNumRegPair &inst_reg_pair);
 
    void addSquashedInst(const DynInstConstPtr& head_inst);
 
    void addCommittedInst(const DynInstConstPtr& head_inst);
 
    EventFunctionWrapper regEtraceListenersEvent;
 
  private:
    bool firstWin;
 
    RegIndex zeroReg;
 
    struct InstExecInfo
    {
        Tick executeTick;
        Tick toCommitTick;
        std::set<InstSeqNum> physRegDepSet;
        InstExecInfo()
          : executeTick(MaxTick),
            toCommitTick(MaxTick)
        { }
    };
 
    std::unordered_map<InstSeqNum, InstExecInfo*> tempStore;
 
    InstSeqNum lastClearedSeqNum;
 
    std::unordered_map<RegIndex, InstSeqNum> physRegDepMap;
 
    struct TraceInfo
    {
        /* Instruction sequence number. */
        InstSeqNum instNum;
        RecordType type;
        /* Tick when instruction was in execute stage. */
        Tick executeTick;
        /* Tick when instruction was marked ready and sent to commit stage. */
        Tick toCommitTick;
        /* Tick when instruction was committed. */
        Tick commitTick;
        /* If instruction was committed, as against squashed. */
        bool commit;
        /* List of order dependencies. */
        std::list<InstSeqNum> robDepList;
        /* List of physical register RAW dependencies. */
        std::list<InstSeqNum> physRegDepList;
        int64_t compDelay;
        /* Number of dependents. */
        uint32_t numDepts;
        /* The instruction PC for a load, store or non load/store. */
        Addr pc;
        /* Request flags in case of a load/store instruction */
        Request::FlagsType reqFlags;
        /* Request physical address in case of a load/store instruction */
        Addr physAddr;
        /* Request virtual address in case of a load/store instruction */
        Addr virtAddr;
        /* Request size in case of a load/store instruction */
        unsigned size;
        TraceInfo()
          : type(Record::INVALID)
        { }
        bool isLoad() const { return (type == Record::LOAD); }
        bool isStore() const { return (type == Record::STORE); }
        bool isComp() const { return (type == Record::COMP); }
        const std::string& typeToStr() const;
        Tick getExecuteTick() const;
    };
 
    std::vector<TraceInfo*> depTrace;
 
    std::unordered_map<InstSeqNum, TraceInfo*> traceInfoMap;
 
    typedef typename std::vector<TraceInfo*>::iterator depTraceItr;
 
    typedef typename std::reverse_iterator<depTraceItr> depTraceRevItr;
 
    uint32_t depWindowSize;
 
    ProtoOutputStream* dataTraceStream;
 
    ProtoOutputStream* instTraceStream;
 
    const InstSeqNum startTraceInst;
 
    bool allProbesReg;
 
    const bool traceVirtAddr;
 
    CPU *cpu;
 
    void addDepTraceRecord(const DynInstConstPtr& head_inst,
                           InstExecInfo* exec_info_ptr, bool commit);
 
    void clearTempStoreUntil(const DynInstConstPtr& head_inst);
 
    void compDelayRob(TraceInfo* past_record, TraceInfo* new_record);
 
    void compDelayPhysRegDep(TraceInfo* past_record, TraceInfo* new_record);
 
    void writeDepTrace(uint32_t num_to_write);
 
    void updateCommitOrderDep(TraceInfo* new_record, bool find_load_not_store);
 
    void updateIssueOrderDep(TraceInfo* new_record);
 
    void assignRobDep(TraceInfo* past_record, TraceInfo* new_record);
 
    bool hasStoreCommitted(TraceInfo* past_record, Tick execute_tick) const;
 
    bool hasLoadCompleted(TraceInfo* past_record, Tick execute_tick) const;
 
    bool hasLoadBeenSent(TraceInfo* past_record, Tick execute_tick) const;
 
    bool hasCompCompleted(TraceInfo* past_record, Tick execute_tick) const;
 
    struct ElasticTraceStats : public statistics::Group
    {
        ElasticTraceStats(statistics::Group *parent);
 
        statistics::Scalar numRegDep;
 
        statistics::Scalar numOrderDepStores;
 
        statistics::Scalar numIssueOrderDepLoads;
 
        statistics::Scalar numIssueOrderDepStores;
 
        statistics::Scalar numIssueOrderDepOther;
 
        statistics::Scalar numFilteredNodes;
 
        statistics::Scalar maxNumDependents;
 
        statistics::Scalar maxTempStoreSize;
 
        statistics::Scalar maxPhysRegDepMapSize;
    } stats;
 
};
 
} // namespace o3
} // namespace gem5
 
#endif//__CPU_O3_PROBE_ELASTIC_TRACE_HH__