O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buffers between stages. More...

#include <cpu.hh>

Inheritance diagram for gem5::o3::CPU:

Classes
struct	CPUStats

Public Types
enum	Status { Running, Idle, Halted, Blocked, SwitchedOut }

enum	StageIdx { FetchIdx, DecodeIdx, RenameIdx, IEWIdx, CommitIdx, NumStages }
	Enum to give each stage a specific index, so when calling activateStage() or deactivateStage(), they can specify which stage is being activated/deactivated. More...

typedef std::list< DynInstPtr >::iterator	ListIt

using	LSQRequest = LSQ::LSQRequest

Public Member Functions
	CPU (const O3CPUParams &params)
	Constructs a CPU with the given parameters. More...

void	regProbePoints () override
	Register probe points. More...

void	demapPage (Addr vaddr, uint64_t asn)

void	tick ()
	Ticks CPU, calling tick() on each stage, and checking the overall activity to see if the CPU should deschedule itself. More...

void	init () override
	Initialize the CPU. More...

void	startup () override

int	numActiveThreads ()
	Returns the Number of Active Threads in the CPU. More...

void	activateThread (ThreadID tid)
	Add Thread to Active Threads List. More...

void	deactivateThread (ThreadID tid)
	Remove Thread from Active Threads List. More...

void	insertThread (ThreadID tid)
	Setup CPU to insert a thread's context. More...

void	removeThread (ThreadID tid)
	Remove all of a thread's context from CPU. More...

Counter	totalInsts () const override
	Count the Total Instructions Committed in the CPU. More...

Counter	totalOps () const override
	Count the Total Ops (including micro ops) committed in the CPU. More...

void	activateContext (ThreadID tid) override
	Add Thread to Active Threads List. More...

void	suspendContext (ThreadID tid) override
	Remove Thread from Active Threads List. More...

void	haltContext (ThreadID tid) override
	Remove Thread from Active Threads List && Remove Thread Context from CPU. More...

void	updateThreadPriority ()
	Update The Order In Which We Process Threads. More...

bool	isDraining () const
	Is the CPU draining? More...

void	serializeThread (CheckpointOut &cp, ThreadID tid) const override

void	unserializeThread (CheckpointIn &cp, ThreadID tid) override

void	addThreadToExitingList (ThreadID tid)
	Insert tid to the list of threads trying to exit. More...

bool	isThreadExiting (ThreadID tid) const
	Is the thread trying to exit? More...

void	scheduleThreadExitEvent (ThreadID tid)
	If a thread is trying to exit and its corresponding trap event has been completed, schedule an event to terminate the thread. More...

void	exitThreads ()
	Terminate all threads that are ready to exit. More...

DrainState	drain () override
	Starts draining the CPU's pipeline of all instructions in order to stop all memory accesses. More...

void	drainResume () override
	Resumes execution after a drain. More...

void	commitDrained (ThreadID tid)
	Commit has reached a safe point to drain a thread. More...

void	switchOut () override
	Switches out this CPU. More...

void	takeOverFrom (BaseCPU *oldCPU) override
	Takes over from another CPU. More...

void	verifyMemoryMode () const override

InstSeqNum	getAndIncrementInstSeq ()
	Get the current instruction sequence number, and increment it. More...

void	trap (const Fault &fault, ThreadID tid, const StaticInstPtr &inst)
	Traps to handle given fault. More...

Fault	getInterrupts ()
	Returns the Fault for any valid interrupt. More...

void	processInterrupts (const Fault &interrupt)
	Processes any an interrupt fault. More...

void	halt ()
	Halts the CPU. More...

RegVal	readMiscRegNoEffect (int misc_reg, ThreadID tid) const
	Register accessors. More...

RegVal	readMiscReg (int misc_reg, ThreadID tid)
	Reads a misc. More...

void	setMiscRegNoEffect (int misc_reg, RegVal val, ThreadID tid)
	Sets a miscellaneous register. More...

void	setMiscReg (int misc_reg, RegVal val, ThreadID tid)
	Sets a misc. More...

RegVal	readIntReg (PhysRegIdPtr phys_reg)

RegVal	readFloatReg (PhysRegIdPtr phys_reg)

const TheISA::VecRegContainer &	readVecReg (PhysRegIdPtr reg_idx) const

TheISA::VecRegContainer &	getWritableVecReg (PhysRegIdPtr reg_idx)
	Read physical vector register for modification. More...

RegVal	readVecElem (PhysRegIdPtr reg_idx) const

const TheISA::VecPredRegContainer &	readVecPredReg (PhysRegIdPtr reg_idx) const

TheISA::VecPredRegContainer &	getWritableVecPredReg (PhysRegIdPtr reg_idx)

RegVal	readCCReg (PhysRegIdPtr phys_reg)

void	setIntReg (PhysRegIdPtr phys_reg, RegVal val)

void	setFloatReg (PhysRegIdPtr phys_reg, RegVal val)

void	setVecReg (PhysRegIdPtr reg_idx, const TheISA::VecRegContainer &val)

void	setVecElem (PhysRegIdPtr reg_idx, RegVal val)

void	setVecPredReg (PhysRegIdPtr reg_idx, const TheISA::VecPredRegContainer &val)

void	setCCReg (PhysRegIdPtr phys_reg, RegVal val)

RegVal	readArchIntReg (int reg_idx, ThreadID tid)

RegVal	readArchFloatReg (int reg_idx, ThreadID tid)

const TheISA::VecRegContainer &	readArchVecReg (int reg_idx, ThreadID tid) const

TheISA::VecRegContainer &	getWritableArchVecReg (int reg_idx, ThreadID tid)
	Read architectural vector register for modification. More...

RegVal	readArchVecElem (const RegIndex &reg_idx, const ElemIndex &ldx, ThreadID tid) const

const TheISA::VecPredRegContainer &	readArchVecPredReg (int reg_idx, ThreadID tid) const

TheISA::VecPredRegContainer &	getWritableArchVecPredReg (int reg_idx, ThreadID tid)

RegVal	readArchCCReg (int reg_idx, ThreadID tid)

void	setArchIntReg (int reg_idx, RegVal val, ThreadID tid)
	Architectural register accessors. More...

void	setArchFloatReg (int reg_idx, RegVal val, ThreadID tid)

void	setArchVecPredReg (int reg_idx, const TheISA::VecPredRegContainer &val, ThreadID tid)

void	setArchVecReg (int reg_idx, const TheISA::VecRegContainer &val, ThreadID tid)

void	setArchVecElem (const RegIndex &reg_idx, const ElemIndex &ldx, RegVal val, ThreadID tid)

void	setArchCCReg (int reg_idx, RegVal val, ThreadID tid)

void	pcState (const PCStateBase &new_pc_state, ThreadID tid)
	Sets the commit PC state of a specific thread. More...

const PCStateBase &	pcState (ThreadID tid)
	Reads the commit PC state of a specific thread. More...

void	squashFromTC (ThreadID tid)
	Initiates a squash of all in-flight instructions for a given thread. More...

ListIt	addInst (const DynInstPtr &inst)
	Function to add instruction onto the head of the list of the instructions. More...

void	instDone (ThreadID tid, const DynInstPtr &inst)
	Function to tell the CPU that an instruction has completed. More...

void	removeFrontInst (const DynInstPtr &inst)
	Remove an instruction from the front end of the list. More...

void	removeInstsNotInROB (ThreadID tid)
	Remove all instructions that are not currently in the ROB. More...

void	removeInstsUntil (const InstSeqNum &seq_num, ThreadID tid)
	Remove all instructions younger than the given sequence number. More...

void	squashInstIt (const ListIt &instIt, ThreadID tid)
	Removes the instruction pointed to by the iterator. More...

void	cleanUpRemovedInsts ()
	Cleans up all instructions on the remove list. More...

void	dumpInsts ()
	Debug function to print all instructions on the list. More...

void	activityThisCycle ()
	Records that there was time buffer activity this cycle. More...

void	activateStage (const StageIdx idx)
	Changes a stage's status to active within the activity recorder. More...

void	deactivateStage (const StageIdx idx)
	Changes a stage's status to inactive within the activity recorder. More...

void	wakeCPU ()
	Wakes the CPU, rescheduling the CPU if it's not already active. More...

virtual void	wakeup (ThreadID tid) override

ThreadID	getFreeTid ()
	Gets a free thread id. More...

gem5::ThreadContext *	tcBase (ThreadID tid)
	Returns a pointer to a thread context. More...

Fault	pushRequest (const DynInstPtr &inst, bool isLoad, uint8_t data, unsigned int size, Addr addr, Request::Flags flags, uint64_t res, AtomicOpFunctorPtr amo_op=nullptr, const std::vector< bool > &byte_enable=std::vector< bool >())
	CPU pushRequest function, forwards request to LSQ. More...

Port &	getInstPort () override
	Used by the fetch unit to get a hold of the instruction port. More...

Port &	getDataPort () override
	Get the dcache port (used to find block size for translations). More...

void	htmSendAbortSignal (ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause) override

Public Attributes
BaseMMU *	mmu

Status	_status
	Overall CPU status. More...

ProbePointArg< PacketPtr > *	ppInstAccessComplete

ProbePointArg< std::pair< DynInstPtr, PacketPtr > > *	ppDataAccessComplete

int	instcount
	Count of total number of dynamic instructions in flight. More...

std::list< DynInstPtr >	instList
	List of all the instructions in flight. More...

std::queue< ListIt >	removeList
	List of all the instructions that will be removed at the end of this cycle. More...

bool	removeInstsThisCycle
	Records if instructions need to be removed this cycle due to being retired or squashed. More...

TimeBuffer< TimeStruct >	timeBuffer
	The main time buffer to do backwards communication. More...

TimeBuffer< FetchStruct >	fetchQueue
	The fetch stage's instruction queue. More...

TimeBuffer< DecodeStruct >	decodeQueue
	The decode stage's instruction queue. More...

TimeBuffer< RenameStruct >	renameQueue
	The rename stage's instruction queue. More...

TimeBuffer< IEWStruct >	iewQueue
	The IEW stage's instruction queue. More...

InstSeqNum	globalSeqNum
	The global sequence number counter. More...

gem5::Checker< DynInstPtr > *	checker
	Pointer to the checker, which can dynamically verify instruction results at run time. More...

System *	system
	Pointer to the system. More...

std::vector< ThreadState * >	thread
	Pointers to all of the threads in the CPU. More...

std::list< int >	cpuWaitList
	Threads Scheduled to Enter CPU. More...

Cycles	lastRunningCycle
	The cycle that the CPU was last running, used for statistics. More...

Tick	lastActivatedCycle
	The cycle that the CPU was last activated by a new thread. More...

std::map< ThreadID, unsigned >	threadMap
	Mapping for system thread id to cpu id. More...

std::vector< ThreadID >	tids
	Available thread ids in the cpu. More...

gem5::o3::CPU::CPUStats	cpuStats

Protected Attributes
Fetch	fetch
	The fetch stage. More...

Decode	decode
	The decode stage. More...

Rename	rename
	The dispatch stage. More...

IEW	iew
	The issue/execute/writeback stages. More...

Commit	commit
	The commit stage. More...

PhysRegFile	regFile
	The register file. More...

UnifiedFreeList	freeList
	The free list. More...

UnifiedRenameMap	renameMap [MaxThreads]
	The rename map. More...

UnifiedRenameMap	commitRenameMap [MaxThreads]
	The commit rename map. More...

ROB	rob
	The re-order buffer. More...

std::list< ThreadID >	activeThreads
	Active Threads List. More...

std::unordered_map< ThreadID, bool >	exitingThreads
	This is a list of threads that are trying to exit. More...

Scoreboard	scoreboard
	Integer Register Scoreboard. More...

std::vector< TheISA::ISA * >	isa

Private Member Functions
void	scheduleTickEvent (Cycles delay)
	Schedule tick event, regardless of its current state. More...

void	unscheduleTickEvent ()
	Unschedule tick event, regardless of its current state. More...

bool	tryDrain ()
	Check if the pipeline has drained and signal drain done. More...

void	drainSanityCheck () const
	Perform sanity checks after a drain. More...

bool	isCpuDrained () const
	Check if a system is in a drained state. More...

Private Attributes
EventFunctionWrapper	tickEvent
	The tick event used for scheduling CPU ticks. More...

EventFunctionWrapper	threadExitEvent
	The exit event used for terminating all ready-to-exit threads. More...

ActivityRecorder	activityRec
	The activity recorder; used to tell if the CPU has any activity remaining or if it can go to idle and deschedule itself. More...

Friends
class	ThreadContext

Detailed Description

O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buffers between stages.

The tick() function for the CPU is defined here.

Definition at line 94 of file cpu.hh.

Member Typedef Documentation

◆ ListIt

typedef std::list<DynInstPtr>::iterator gem5::o3::CPU::ListIt

Definition at line 97 of file cpu.hh.

◆ LSQRequest

using gem5::o3::CPU::LSQRequest = LSQ::LSQRequest

Definition at line 112 of file cpu.hh.

Member Enumeration Documentation

◆ StageIdx

enum gem5::o3::CPU::StageIdx

Enum to give each stage a specific index, so when calling activateStage() or deactivateStage(), they can specify which stage is being activated/deactivated.

Enumerator
FetchIdx
DecodeIdx
RenameIdx
IEWIdx
CommitIdx
NumStages

Definition at line 505 of file cpu.hh.

◆ Status

enum gem5::o3::CPU::Status

Enumerator
Running
Idle
Halted
Blocked
SwitchedOut

Definition at line 102 of file cpu.hh.

Constructor & Destructor Documentation

◆ CPU()

gem5::o3::CPU::CPU ( const O3CPUParams & params )

Constructs a CPU with the given parameters.

Definition at line 73 of file cpu.cc.

References tick().

Member Function Documentation

◆ activateContext()

void gem5::o3::CPU::activateContext ( ThreadID tid )

override

Add Thread to Active Threads List.

Definition at line 640 of file cpu.cc.

References _status, activateThread(), gem5::ActivityRecorder::activity(), activityRec, cpuStats, gem5::curTick(), gem5::Drained, fetch, lastActivatedCycle, lastRunningCycle, gem5::o3::CPU::CPUStats::quiesceCycles, Running, scheduleTickEvent(), and gem5::o3::Fetch::wakeFromQuiesce().

Referenced by gem5::o3::ThreadContext::activate(), drain(), and insertThread().

◆ activateStage()

void gem5::o3::CPU::activateStage ( const StageIdx idx )

inline

Changes a stage's status to active within the activity recorder.

Definition at line 543 of file cpu.hh.

References gem5::ActivityRecorder::activateStage(), and activityRec.

Referenced by gem5::o3::IEW::activateStage(), gem5::o3::IEW::startupStage(), gem5::o3::Commit::startupStage(), gem5::o3::Fetch::switchToActive(), gem5::o3::Fetch::updateFetchStatus(), gem5::o3::Decode::updateStatus(), gem5::o3::Commit::updateStatus(), and gem5::o3::Rename::updateStatus().

◆ activateThread()

void gem5::o3::CPU::activateThread ( ThreadID tid )

Add Thread to Active Threads List.

Definition at line 576 of file cpu.cc.

References activeThreads, and DPRINTF.

Referenced by activateContext(), and drainResume().

◆ activityThisCycle()

void gem5::o3::CPU::activityThisCycle ( )

inline

Records that there was time buffer activity this cycle.

Definition at line 539 of file cpu.hh.

References gem5::ActivityRecorder::activity(), and activityRec.

Referenced by gem5::o3::IEW::activityThisCycle(), gem5::o3::LSQUnit::completeStore(), gem5::o3::IEW::executeInsts(), gem5::o3::Fetch::finishTranslation(), gem5::o3::InstructionQueue::scheduleReadyInsts(), gem5::o3::Commit::squashFromSquashAfter(), gem5::o3::Commit::squashFromTC(), gem5::o3::Commit::squashFromTrap(), gem5::o3::Commit::startupStage(), gem5::o3::IEW::takeOverFrom(), gem5::o3::Decode::tick(), gem5::o3::Rename::tick(), gem5::o3::Commit::tick(), gem5::o3::IEW::tick(), and gem5::o3::Fetch::tick().

◆ addInst()

CPU::ListIt gem5::o3::CPU::addInst ( const DynInstPtr & inst )

Function to add instruction onto the head of the list of the instructions.

Used when new instructions are fetched.

Definition at line 1330 of file cpu.cc.

References instList.

Referenced by gem5::o3::Fetch::buildInst().

◆ addThreadToExitingList()

void gem5::o3::CPU::addThreadToExitingList ( ThreadID tid )

Insert tid to the list of threads trying to exit.

Definition at line 1575 of file cpu.cc.

References DPRINTF, exitingThreads, gem5::ThreadContext::Halted, gem5::ArmISA::status, and tcBase().

Referenced by gem5::o3::ThreadContext::halt().

◆ cleanUpRemovedInsts()

void gem5::o3::CPU::cleanUpRemovedInsts ( )

Cleans up all instructions on the remove list.

Definition at line 1462 of file cpu.cc.

References DPRINTF, instList, removeInstsThisCycle, and removeList.

Referenced by tick().

◆ commitDrained()

void gem5::o3::CPU::commitDrained ( ThreadID tid )

Commit has reached a safe point to drain a thread.

Commit calls this method to inform the pipeline that it has reached a point where it is not executed microcode and is about to squash uncommitted instructions to fully drain the pipeline.

Definition at line 988 of file cpu.cc.

References gem5::o3::Fetch::drainStall(), and fetch.

Referenced by gem5::o3::Commit::commitInsts().

◆ deactivateStage()

void gem5::o3::CPU::deactivateStage ( const StageIdx idx )

inline

Changes a stage's status to inactive within the activity recorder.

Definition at line 550 of file cpu.hh.

References activityRec, and gem5::ActivityRecorder::deactivateStage().

Referenced by gem5::o3::IEW::deactivateStage(), gem5::o3::Fetch::switchToInactive(), gem5::o3::Fetch::updateFetchStatus(), gem5::o3::Decode::updateStatus(), gem5::o3::Commit::updateStatus(), and gem5::o3::Rename::updateStatus().

◆ deactivateThread()

void gem5::o3::CPU::deactivateThread ( ThreadID tid )

Remove Thread from Active Threads List.

Definition at line 592 of file cpu.cc.

References activeThreads, commit, gem5::o3::Commit::deactivateThread(), gem5::o3::Fetch::deactivateThread(), DPRINTF, gem5::o3::Commit::executingHtmTransaction(), and fetch.

Referenced by haltContext(), and suspendContext().

◆ demapPage()

void gem5::o3::CPU::demapPage	(	Addr	vaddr,
		uint64_t	asn
	)

inline

Definition at line 181 of file cpu.hh.

References gem5::BaseMMU::demapPage(), mmu, and gem5::MipsISA::vaddr.

Referenced by gem5::o3::DynInst::demapPage().

◆ drain()

DrainState gem5::o3::CPU::drain ( )

override

Starts draining the CPU's pipeline of all instructions in order to stop all memory accesses.

Definition at line 863 of file cpu.cc.

References activateContext(), gem5::ActivityRecorder::activity(), activityRec, commit, decodeQueue, DPRINTF, gem5::o3::Commit::drain(), gem5::Drained, gem5::Draining, drainSanityCheck(), fetchQueue, gem5::ArmISA::i, iewQueue, isCpuDrained(), renameQueue, gem5::Event::scheduled(), gem5::ThreadContext::Suspended, gem5::ArmISA::t, tickEvent, timeBuffer, and wakeCPU().

◆ drainResume()

void gem5::o3::CPU::drainResume ( )

override

Resumes execution after a drain.

Definition at line 991 of file cpu.cc.

References _status, activateThread(), gem5::ThreadContext::Active, commit, DPRINTF, gem5::o3::Commit::drainResume(), gem5::o3::Fetch::drainResume(), fetch, gem5::ArmISA::i, Idle, Running, gem5::Event::scheduled(), gem5::ArmISA::status, thread, tickEvent, and verifyMemoryMode().

◆ drainSanityCheck()

void gem5::o3::CPU::drainSanityCheck ( ) const

private

Perform sanity checks after a drain.

This method is called from drain() when it has determined that the CPU is fully drained when gem5 is compiled with the NDEBUG macro undefined. The intention of this method is to do more extensive tests than the isDrained() method to weed out any draining bugs.

Definition at line 940 of file cpu.cc.

References commit, decode, gem5::o3::Decode::drainSanityCheck(), gem5::o3::IEW::drainSanityCheck(), gem5::o3::Rename::drainSanityCheck(), gem5::o3::Commit::drainSanityCheck(), gem5::o3::Fetch::drainSanityCheck(), fetch, iew, isCpuDrained(), and rename.

Referenced by drain().

◆ dumpInsts()

void gem5::o3::CPU::dumpInsts ( )

Debug function to print all instructions on the list.

Definition at line 1486 of file cpu.cc.

References gem5::cprintf(), and instList.

Referenced by gem5::o3::DynInst::DynInst().

◆ exitThreads()

void gem5::o3::CPU::exitThreads ( )

Terminate all threads that are ready to exit.

Definition at line 1620 of file cpu.cc.

References DPRINTF, exitingThreads, haltContext(), gem5::ThreadContext::Halted, gem5::ThreadContext::setStatus(), and tcBase().

◆ getAndIncrementInstSeq()

InstSeqNum gem5::o3::CPU::getAndIncrementInstSeq ( )

inline

Get the current instruction sequence number, and increment it.

Definition at line 282 of file cpu.hh.

References globalSeqNum.

Referenced by gem5::o3::Fetch::buildInst().

◆ getDataPort()

Port& gem5::o3::CPU::getDataPort ( )

inlineoverride

Get the dcache port (used to find block size for translations).

Definition at line 622 of file cpu.hh.

References gem5::o3::LSQ::getDataPort(), iew, and gem5::o3::IEW::ldstQueue.

◆ getFreeTid()

ThreadID gem5::o3::CPU::getFreeTid ( )

Gets a free thread id.

Use if thread ids change across system.

Definition at line 1546 of file cpu.cc.

References gem5::InvalidThreadID, and tids.

◆ getInstPort()

Port& gem5::o3::CPU::getInstPort ( )

inlineoverride

Used by the fetch unit to get a hold of the instruction port.

Definition at line 615 of file cpu.hh.

References fetch, and gem5::o3::Fetch::getInstPort().

Referenced by gem5::o3::Fetch::takeOverFrom().

◆ getInterrupts()

Fault gem5::o3::CPU::getInterrupts ( )

Returns the Fault for any valid interrupt.

Definition at line 821 of file cpu.cc.

Referenced by gem5::o3::Commit::handleInterrupt(), and gem5::o3::Commit::propagateInterrupt().

◆ getWritableArchVecPredReg()

TheISA::VecPredRegContainer & gem5::o3::CPU::getWritableArchVecPredReg	(	int	reg_idx,
		ThreadID	tid
	)

Definition at line 1240 of file cpu.cc.

References commitRenameMap, gem5::o3::PhysRegFile::getWritableVecPredReg(), gem5::o3::UnifiedRenameMap::lookup(), regFile, and gem5::VecPredRegClass.

Referenced by gem5::o3::ThreadContext::getWritableVecPredRegFlat().

◆ getWritableArchVecReg()

TheISA::VecRegContainer & gem5::o3::CPU::getWritableArchVecReg	(	int	reg_idx,
		ThreadID	tid
	)

Read architectural vector register for modification.

Definition at line 1215 of file cpu.cc.

References commitRenameMap, gem5::o3::PhysRegFile::getWritableVecReg(), gem5::o3::UnifiedRenameMap::lookup(), regFile, and gem5::VecRegClass.

Referenced by gem5::o3::ThreadContext::getWritableVecRegFlat().

◆ getWritableVecPredReg()

TheISA::VecPredRegContainer & gem5::o3::CPU::getWritableVecPredReg ( PhysRegIdPtr reg_idx )

Definition at line 1132 of file cpu.cc.

References cpuStats, gem5::o3::PhysRegFile::getWritableVecPredReg(), regFile, and gem5::o3::CPU::CPUStats::vecPredRegfileWrites.

Referenced by gem5::o3::DynInst::getWritableVecPredRegOperand().

◆ getWritableVecReg()

TheISA::VecRegContainer & gem5::o3::CPU::getWritableVecReg ( PhysRegIdPtr reg_idx )

Read physical vector register for modification.

Definition at line 1111 of file cpu.cc.

References cpuStats, gem5::o3::PhysRegFile::getWritableVecReg(), regFile, and gem5::o3::CPU::CPUStats::vecRegfileWrites.

Referenced by gem5::o3::DynInst::getWritableVecRegOperand().

◆ halt()

void gem5::o3::CPU::halt ( )

inline

Halts the CPU.

Definition at line 294 of file cpu.hh.

References panic.

◆ haltContext()

void gem5::o3::CPU::haltContext ( ThreadID tid )

override

Remove Thread from Active Threads List && Remove Thread Context from CPU.

Definition at line 698 of file cpu.cc.

References _status, activeThreads, deactivateThread(), DPRINTF, Idle, lastRunningCycle, removeThread(), gem5::Event::scheduled(), tickEvent, and unscheduleTickEvent().

Referenced by exitThreads().

◆ htmSendAbortSignal()

void gem5::o3::CPU::htmSendAbortSignal	(	ThreadID	tid,
		uint64_t	htm_uid,
		HtmFailureFaultCause	cause
	)

override

Definition at line 1643 of file cpu.cc.

References gem5::X86ISA::addr, commit, gem5::Packet::createRead(), gem5::Packet::dataStatic(), gem5::o3::LSQ::getDataPort(), gem5::Request::HTM_ABORT, iew, gem5::o3::IEW::ldstQueue, panic, gem5::Request::PHYSICAL, gem5::o3::Commit::resetHtmStartsStops(), gem5::o3::LSQ::resetHtmStartsStops(), gem5::RequestPort::sendTimingReq(), gem5::Packet::setHtmTransactional(), gem5::Request::STRICT_ORDER, and thread.

Referenced by gem5::o3::ThreadContext::htmAbortTransaction().

◆ init()

void gem5::o3::CPU::init ( )

override

Initialize the CPU.

Definition at line 546 of file cpu.cc.

References commit, gem5::statistics::init, gem5::o3::Commit::setThreads(), and thread.

◆ insertThread()

void gem5::o3::CPU::insertThread ( ThreadID tid )

Setup CPU to insert a thread's context.

Definition at line 720 of file cpu.cc.

References activateContext(), gem5::ThreadContext::Active, gem5::CCRegClass, commit, DPRINTF, gem5::FloatRegClass, freeList, gem5::FullSystem, gem5::o3::UnifiedFreeList::getCCReg(), gem5::o3::UnifiedFreeList::getFloatReg(), gem5::o3::UnifiedFreeList::getIntReg(), gem5::IntRegClass, isa, gem5::ThreadContext::pcState(), pcState(), renameMap, gem5::o3::ROB::resetEntries(), gem5::o3::Commit::rob, scoreboard, gem5::o3::UnifiedRenameMap::setEntry(), gem5::o3::Scoreboard::setReg(), gem5::ThreadContext::setStatus(), system, tcBase(), and gem5::System::threads.

◆ instDone()

void gem5::o3::CPU::instDone	(	ThreadID	tid,
		const DynInstPtr &	inst
	)

Function to tell the CPU that an instruction has completed.

Definition at line 1338 of file cpu.cc.

References gem5::o3::CPU::CPUStats::committedInsts, gem5::o3::CPU::CPUStats::committedOps, cpuStats, and thread.

Referenced by gem5::o3::Commit::updateComInstStats().

◆ isCpuDrained()

bool gem5::o3::CPU::isCpuDrained ( ) const

private

Check if a system is in a drained state.

Definition at line 951 of file cpu.cc.

References commit, decode, DPRINTF, fetch, iew, instList, gem5::o3::Decode::isDrained(), gem5::o3::IEW::isDrained(), gem5::o3::Rename::isDrained(), gem5::o3::Commit::isDrained(), gem5::o3::Fetch::isDrained(), removeList, and rename.

Referenced by drain(), drainSanityCheck(), and tryDrain().

◆ isDraining()

bool gem5::o3::CPU::isDraining ( ) const

inline

Is the CPU draining?

Definition at line 236 of file cpu.hh.

References gem5::Draining.

Referenced by gem5::o3::Fetch::checkStall(), gem5::o3::Fetch::drainStall(), and gem5::o3::ThreadContext::suspend().

◆ isThreadExiting()

bool gem5::o3::CPU::isThreadExiting ( ThreadID tid ) const

Is the thread trying to exit?

Definition at line 1594 of file cpu.cc.

References exitingThreads.

Referenced by gem5::o3::Commit::commit(), and gem5::o3::ROB::doSquash().

◆ numActiveThreads()

int gem5::o3::CPU::numActiveThreads ( )

inline

Returns the Number of Active Threads in the CPU.

Definition at line 198 of file cpu.hh.

References activeThreads.

◆ pcState() [1/2]

void gem5::o3::CPU::pcState	(	const PCStateBase &	new_pc_state,
		ThreadID	tid
	)

Sets the commit PC state of a specific thread.

Definition at line 1317 of file cpu.cc.

References commit, gem5::o3::Commit::pcState(), and gem5::X86ISA::val.

Referenced by gem5::o3::Fetch::clearStates(), insertThread(), gem5::o3::ThreadContext::pcState(), gem5::o3::ThreadContext::pcStateNoRecord(), and gem5::o3::Fetch::resetStage().

◆ pcState() [2/2]

const PCStateBase & gem5::o3::CPU::pcState ( ThreadID tid )

Reads the commit PC state of a specific thread.

Definition at line 1311 of file cpu.cc.

References commit, and gem5::o3::Commit::pcState().

◆ processInterrupts()

void gem5::o3::CPU::processInterrupts ( const Fault & interrupt )

Processes any an interrupt fault.

Definition at line 828 of file cpu.cc.

References DPRINTF, gem5::NoFault, and trap().

Referenced by gem5::o3::Commit::handleInterrupt().

◆ pushRequest()

Fault gem5::o3::CPU::pushRequest	(	const DynInstPtr &	inst,
		bool	isLoad,
		uint8_t *	data,
		unsigned int	size,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res,
		AtomicOpFunctorPtr	amo_op = `nullptr`,
		const std::vector< bool > &	byte_enable = `std::vector<bool>()`
	)

inline

CPU pushRequest function, forwards request to LSQ.

Definition at line 603 of file cpu.hh.

References gem5::X86ISA::addr, data, iew, gem5::o3::IEW::ldstQueue, and gem5::o3::LSQ::pushRequest().

Referenced by gem5::o3::DynInst::initiateHtmCmd(), gem5::o3::DynInst::initiateMemAMO(), gem5::o3::DynInst::initiateMemRead(), and gem5::o3::DynInst::writeMem().

◆ readArchCCReg()

RegVal gem5::o3::CPU::readArchCCReg	(	int	reg_idx,
		ThreadID	tid
	)

Definition at line 1248 of file cpu.cc.

References gem5::CCRegClass, commitRenameMap, gem5::o3::UnifiedRenameMap::lookup(), gem5::o3::PhysRegFile::readCCReg(), and regFile.

Referenced by gem5::o3::ThreadContext::readCCRegFlat().

◆ readArchFloatReg()

RegVal gem5::o3::CPU::readArchFloatReg	(	int	reg_idx,
		ThreadID	tid
	)

Definition at line 1198 of file cpu.cc.

References commitRenameMap, gem5::FloatRegClass, gem5::o3::UnifiedRenameMap::lookup(), gem5::o3::PhysRegFile::readFloatReg(), and regFile.

Referenced by gem5::o3::ThreadContext::readFloatRegFlat().

◆ readArchIntReg()

RegVal gem5::o3::CPU::readArchIntReg	(	int	reg_idx,
		ThreadID	tid
	)

Definition at line 1189 of file cpu.cc.

References commitRenameMap, gem5::IntRegClass, gem5::o3::UnifiedRenameMap::lookup(), gem5::o3::PhysRegFile::readIntReg(), and regFile.

Referenced by gem5::o3::ThreadContext::readIntRegFlat().

◆ readArchVecElem()

RegVal gem5::o3::CPU::readArchVecElem	(	const RegIndex &	reg_idx,
		const ElemIndex &	ldx,
		ThreadID	tid
	)		const

Definition at line 1223 of file cpu.cc.

References commitRenameMap, gem5::o3::UnifiedRenameMap::lookup(), gem5::o3::PhysRegFile::readVecElem(), regFile, and gem5::VecElemClass.

Referenced by gem5::o3::ThreadContext::readVecElemFlat().

◆ readArchVecPredReg()

const TheISA::VecPredRegContainer & gem5::o3::CPU::readArchVecPredReg	(	int	reg_idx,
		ThreadID	tid
	)		const

Definition at line 1232 of file cpu.cc.

References commitRenameMap, gem5::o3::UnifiedRenameMap::lookup(), gem5::o3::PhysRegFile::readVecPredReg(), regFile, and gem5::VecPredRegClass.

Referenced by gem5::o3::ThreadContext::readVecPredRegFlat().

◆ readArchVecReg()

const TheISA::VecRegContainer & gem5::o3::CPU::readArchVecReg	(	int	reg_idx,
		ThreadID	tid
	)		const

Definition at line 1207 of file cpu.cc.

References commitRenameMap, gem5::o3::UnifiedRenameMap::lookup(), gem5::o3::PhysRegFile::readVecReg(), regFile, and gem5::VecRegClass.

Referenced by gem5::o3::ThreadContext::readVecRegFlat().

◆ readCCReg()

RegVal gem5::o3::CPU::readCCReg ( PhysRegIdPtr phys_reg )

Definition at line 1139 of file cpu.cc.

References gem5::o3::CPU::CPUStats::ccRegfileReads, cpuStats, gem5::o3::PhysRegFile::readCCReg(), and regFile.

Referenced by gem5::o3::DynInst::forwardOldRegs(), and gem5::o3::DynInst::readCCRegOperand().

◆ readFloatReg()

RegVal gem5::o3::CPU::readFloatReg ( PhysRegIdPtr phys_reg )

Definition at line 1097 of file cpu.cc.

References cpuStats, gem5::o3::CPU::CPUStats::fpRegfileReads, gem5::o3::PhysRegFile::readFloatReg(), and regFile.

Referenced by gem5::o3::DynInst::forwardOldRegs(), and gem5::o3::DynInst::readFloatRegOperandBits().

◆ readIntReg()

RegVal gem5::o3::CPU::readIntReg ( PhysRegIdPtr phys_reg )

Definition at line 1090 of file cpu.cc.

References cpuStats, gem5::o3::CPU::CPUStats::intRegfileReads, gem5::o3::PhysRegFile::readIntReg(), and regFile.

Referenced by gem5::o3::DynInst::forwardOldRegs(), and gem5::o3::DynInst::readIntRegOperand().

◆ readMiscReg()

RegVal gem5::o3::CPU::readMiscReg	(	int	misc_reg,
		ThreadID	tid
	)

Reads a misc.

register, including any side effects the read might have as defined by the architecture.

Definition at line 1070 of file cpu.cc.

References cpuStats, isa, and gem5::o3::CPU::CPUStats::miscRegfileReads.

Referenced by gem5::o3::ThreadContext::readMiscReg(), gem5::o3::DynInst::readMiscReg(), and gem5::o3::DynInst::readMiscRegOperand().

◆ readMiscRegNoEffect()

RegVal gem5::o3::CPU::readMiscRegNoEffect	(	int	misc_reg,
		ThreadID	tid
	)		const

Register accessors.

Index refers to the physical register index. Reads a miscellaneous register.

Definition at line 1064 of file cpu.cc.

References isa.

Referenced by gem5::o3::ThreadContext::readMiscRegNoEffect().

◆ readVecElem()

RegVal gem5::o3::CPU::readVecElem ( PhysRegIdPtr reg_idx ) const

Definition at line 1118 of file cpu.cc.

References cpuStats, gem5::o3::PhysRegFile::readVecElem(), regFile, and gem5::o3::CPU::CPUStats::vecRegfileReads.

Referenced by gem5::o3::DynInst::forwardOldRegs(), and gem5::o3::DynInst::readVecElemOperand().

◆ readVecPredReg()

const TheISA::VecPredRegContainer & gem5::o3::CPU::readVecPredReg ( PhysRegIdPtr reg_idx ) const

Definition at line 1125 of file cpu.cc.

References cpuStats, gem5::o3::PhysRegFile::readVecPredReg(), regFile, and gem5::o3::CPU::CPUStats::vecPredRegfileReads.

Referenced by gem5::o3::DynInst::forwardOldRegs(), and gem5::o3::DynInst::readVecPredRegOperand().

◆ readVecReg()

const TheISA::VecRegContainer & gem5::o3::CPU::readVecReg ( PhysRegIdPtr reg_idx ) const

Definition at line 1104 of file cpu.cc.

References cpuStats, gem5::o3::PhysRegFile::readVecReg(), regFile, and gem5::o3::CPU::CPUStats::vecRegfileReads.

Referenced by gem5::o3::DynInst::forwardOldRegs(), and gem5::o3::DynInst::readVecRegOperand().

◆ regProbePoints()

void gem5::o3::CPU::regProbePoints ( )

override

Register probe points.

Definition at line 344 of file cpu.cc.

References commit, fetch, iew, ppDataAccessComplete, ppInstAccessComplete, gem5::o3::Rename::regProbePoints(), gem5::o3::IEW::regProbePoints(), gem5::o3::Commit::regProbePoints(), gem5::o3::Fetch::regProbePoints(), and rename.

◆ removeFrontInst()

void gem5::o3::CPU::removeFrontInst ( const DynInstPtr & inst )

Remove an instruction from the front end of the list.

There's no restriction on location of the instruction.

Definition at line 1357 of file cpu.cc.

References DPRINTF, removeInstsThisCycle, and removeList.

Referenced by gem5::o3::ROB::retireHead().

◆ removeInstsNotInROB()

void gem5::o3::CPU::removeInstsNotInROB ( ThreadID tid )

Remove all instructions that are not currently in the ROB.

There's also an option to not squash delay slot instructions.

Definition at line 1370 of file cpu.cc.

References DPRINTF, instList, gem5::o3::ROB::isEmpty(), gem5::o3::ROB::readTailInst(), removeInstsThisCycle, rob, and squashInstIt().

Referenced by gem5::o3::Fetch::squash().

◆ removeInstsUntil()

void gem5::o3::CPU::removeInstsUntil	(	const InstSeqNum &	seq_num,
		ThreadID	tid
	)

Remove all instructions younger than the given sequence number.

Definition at line 1414 of file cpu.cc.

References DPRINTF, instList, removeInstsThisCycle, and squashInstIt().

Referenced by gem5::o3::Decode::squash(), and gem5::o3::Fetch::squashFromDecode().

◆ removeThread()

void gem5::o3::CPU::removeThread ( ThreadID tid )

Remove all of a thread's context from CPU.

Definition at line 769 of file cpu.cc.

References gem5::o3::Decode::clearStates(), gem5::o3::IEW::clearStates(), gem5::o3::Rename::clearStates(), gem5::o3::Commit::clearStates(), gem5::o3::Fetch::clearStates(), commit, decode, decodeQueue, DPRINTF, fetch, fetchQueue, gem5::o3::InstructionQueue::getCount(), gem5::o3::LSQ::getCount(), gem5::ArmISA::i, iew, iewQueue, gem5::o3::IEW::instQueue, gem5::o3::ROB::isEmpty(), gem5::o3::IEW::ldstQueue, rename, renameQueue, gem5::o3::Commit::rob, and timeBuffer.

Referenced by haltContext().

◆ scheduleThreadExitEvent()

void gem5::o3::CPU::scheduleThreadExitEvent ( ThreadID tid )

If a thread is trying to exit and its corresponding trap event has been completed, schedule an event to terminate the thread.

Definition at line 1600 of file cpu.cc.

References exitingThreads, gem5::Event::scheduled(), and threadExitEvent.

Referenced by gem5::o3::Commit::commit().

◆ scheduleTickEvent()

void gem5::o3::CPU::scheduleTickEvent ( Cycles delay )

inlineprivate

Schedule tick event, regardless of its current state.

Definition at line 127 of file cpu.hh.

References gem5::Event::scheduled(), gem5::Event::squashed(), and tickEvent.

Referenced by activateContext().

◆ serializeThread()

void gem5::o3::CPU::serializeThread	(	CheckpointOut &	cp,
		ThreadID	tid
	)		const

override

Definition at line 851 of file cpu.cc.

References thread.

◆ setArchCCReg()

void gem5::o3::CPU::setArchCCReg	(	int	reg_idx,
		RegVal	val,
		ThreadID	tid
	)

Definition at line 1302 of file cpu.cc.

References gem5::CCRegClass, commitRenameMap, gem5::o3::UnifiedRenameMap::lookup(), regFile, gem5::o3::PhysRegFile::setCCReg(), and gem5::X86ISA::val.

Referenced by gem5::o3::ThreadContext::setCCRegFlat().

◆ setArchFloatReg()

void gem5::o3::CPU::setArchFloatReg	(	int	reg_idx,
		RegVal	val,
		ThreadID	tid
	)

Definition at line 1266 of file cpu.cc.

References commitRenameMap, gem5::FloatRegClass, gem5::o3::UnifiedRenameMap::lookup(), regFile, gem5::o3::PhysRegFile::setFloatReg(), and gem5::X86ISA::val.

Referenced by gem5::o3::ThreadContext::setFloatRegFlat().

◆ setArchIntReg()

void gem5::o3::CPU::setArchIntReg	(	int	reg_idx,
		RegVal	val,
		ThreadID	tid
	)

Architectural register accessors.

Looks up in the commit rename table to obtain the true physical index of the architected register first, then accesses that physical register.

Definition at line 1257 of file cpu.cc.

References commitRenameMap, gem5::IntRegClass, gem5::o3::UnifiedRenameMap::lookup(), regFile, gem5::o3::PhysRegFile::setIntReg(), and gem5::X86ISA::val.

Referenced by gem5::o3::ThreadContext::setIntRegFlat().

◆ setArchVecElem()

void gem5::o3::CPU::setArchVecElem	(	const RegIndex &	reg_idx,
		const ElemIndex &	ldx,
		RegVal	val,
		ThreadID	tid
	)

Definition at line 1284 of file cpu.cc.

References commitRenameMap, gem5::o3::UnifiedRenameMap::lookup(), regFile, gem5::o3::PhysRegFile::setVecElem(), gem5::X86ISA::val, and gem5::VecElemClass.

Referenced by gem5::o3::ThreadContext::setVecElemFlat().

◆ setArchVecPredReg()

void gem5::o3::CPU::setArchVecPredReg	(	int	reg_idx,
		const TheISA::VecPredRegContainer &	val,
		ThreadID	tid
	)

Definition at line 1293 of file cpu.cc.

References commitRenameMap, gem5::o3::UnifiedRenameMap::lookup(), regFile, gem5::o3::PhysRegFile::setVecPredReg(), gem5::X86ISA::val, and gem5::VecPredRegClass.

Referenced by gem5::o3::ThreadContext::setVecPredRegFlat().

◆ setArchVecReg()

void gem5::o3::CPU::setArchVecReg	(	int	reg_idx,
		const TheISA::VecRegContainer &	val,
		ThreadID	tid
	)

Definition at line 1275 of file cpu.cc.

References commitRenameMap, gem5::o3::UnifiedRenameMap::lookup(), regFile, gem5::o3::PhysRegFile::setVecReg(), gem5::X86ISA::val, and gem5::VecRegClass.

Referenced by gem5::o3::ThreadContext::setVecRegFlat().

◆ setCCReg()

void gem5::o3::CPU::setCCReg	(	PhysRegIdPtr	phys_reg,
		RegVal	val
	)

Definition at line 1182 of file cpu.cc.

References gem5::o3::CPU::CPUStats::ccRegfileWrites, cpuStats, regFile, gem5::o3::PhysRegFile::setCCReg(), and gem5::X86ISA::val.

Referenced by gem5::o3::DynInst::setCCRegOperand().

◆ setFloatReg()

void gem5::o3::CPU::setFloatReg	(	PhysRegIdPtr	phys_reg,
		RegVal	val
	)

Definition at line 1153 of file cpu.cc.

References cpuStats, gem5::o3::CPU::CPUStats::fpRegfileWrites, regFile, gem5::o3::PhysRegFile::setFloatReg(), and gem5::X86ISA::val.

Referenced by gem5::o3::DynInst::setFloatRegOperandBits().

◆ setIntReg()

void gem5::o3::CPU::setIntReg	(	PhysRegIdPtr	phys_reg,
		RegVal	val
	)

Definition at line 1146 of file cpu.cc.

References cpuStats, gem5::o3::CPU::CPUStats::intRegfileWrites, regFile, gem5::o3::PhysRegFile::setIntReg(), and gem5::X86ISA::val.

Referenced by gem5::o3::DynInst::setIntRegOperand().

◆ setMiscReg()

void gem5::o3::CPU::setMiscReg	(	int	misc_reg,
		RegVal	val,
		ThreadID	tid
	)

Sets a misc.

register, including any side effects the write might have as defined by the architecture.

Definition at line 1083 of file cpu.cc.

References cpuStats, isa, gem5::o3::CPU::CPUStats::miscRegfileWrites, and gem5::X86ISA::val.

Referenced by gem5::o3::ThreadContext::setMiscReg(), and gem5::o3::DynInst::updateMiscRegs().

◆ setMiscRegNoEffect()

void gem5::o3::CPU::setMiscRegNoEffect	(	int	misc_reg,
		RegVal	val,
		ThreadID	tid
	)

Sets a miscellaneous register.

Definition at line 1077 of file cpu.cc.

References isa, and gem5::X86ISA::val.

Referenced by gem5::o3::ThreadContext::setMiscRegNoEffect().

◆ setVecElem()

void gem5::o3::CPU::setVecElem	(	PhysRegIdPtr	reg_idx,
		RegVal	val
	)

Definition at line 1167 of file cpu.cc.

References cpuStats, regFile, gem5::o3::PhysRegFile::setVecElem(), gem5::X86ISA::val, and gem5::o3::CPU::CPUStats::vecRegfileWrites.

Referenced by gem5::o3::DynInst::setVecElemOperand().

◆ setVecPredReg()

void gem5::o3::CPU::setVecPredReg	(	PhysRegIdPtr	reg_idx,
		const TheISA::VecPredRegContainer &	val
	)

Definition at line 1174 of file cpu.cc.

References cpuStats, regFile, gem5::o3::PhysRegFile::setVecPredReg(), gem5::X86ISA::val, and gem5::o3::CPU::CPUStats::vecPredRegfileWrites.

Referenced by gem5::o3::DynInst::setVecPredRegOperand().

◆ setVecReg()

void gem5::o3::CPU::setVecReg	(	PhysRegIdPtr	reg_idx,
		const TheISA::VecRegContainer &	val
	)

Definition at line 1160 of file cpu.cc.

References cpuStats, regFile, gem5::o3::PhysRegFile::setVecReg(), gem5::X86ISA::val, and gem5::o3::CPU::CPUStats::vecRegfileWrites.

Referenced by gem5::o3::DynInst::setVecRegOperand().

◆ squashFromTC()

void gem5::o3::CPU::squashFromTC ( ThreadID tid )

Initiates a squash of all in-flight instructions for a given thread.

The source of the squash is an external update of state through the TC.

Definition at line 1323 of file cpu.cc.

References commit, gem5::o3::Commit::generateTCEvent(), and thread.

Referenced by gem5::o3::ThreadContext::conditionalSquash().

◆ squashInstIt()

void gem5::o3::CPU::squashInstIt	(	const ListIt &	instIt,
		ThreadID	tid
	)

Removes the instruction pointed to by the iterator.

Definition at line 1442 of file cpu.cc.

References DPRINTF, and removeList.

Referenced by removeInstsNotInROB(), and removeInstsUntil().

◆ startup()

void gem5::o3::CPU::startup ( )

override

Definition at line 564 of file cpu.cc.

References commit, decode, fetch, iew, rename, gem5::o3::Decode::startupStage(), gem5::o3::IEW::startupStage(), gem5::o3::Rename::startupStage(), gem5::o3::Commit::startupStage(), and gem5::o3::Fetch::startupStage().

◆ suspendContext()

void gem5::o3::CPU::suspendContext ( ThreadID tid )

override

Remove Thread from Active Threads List.

Definition at line 678 of file cpu.cc.

References _status, activeThreads, deactivateThread(), DPRINTF, Idle, lastRunningCycle, and unscheduleTickEvent().

Referenced by gem5::o3::ThreadContext::suspend().

◆ switchOut()

void gem5::o3::CPU::switchOut ( )

override

Switches out this CPU.

Definition at line 1020 of file cpu.cc.

References _status, activityRec, checker, DPRINTF, gem5::ActivityRecorder::reset(), and SwitchedOut.

◆ takeOverFrom()

void gem5::o3::CPU::takeOverFrom ( BaseCPU * oldCPU )

override

Takes over from another CPU.

Definition at line 1034 of file cpu.cc.

References _status, commit, decode, fetch, globalSeqNum, Idle, iew, lastRunningCycle, rename, gem5::Event::scheduled(), gem5::o3::Decode::takeOverFrom(), gem5::o3::IEW::takeOverFrom(), gem5::o3::Rename::takeOverFrom(), gem5::o3::Commit::takeOverFrom(), gem5::o3::Fetch::takeOverFrom(), gem5::takeOverFrom(), and tickEvent.

◆ tcBase()

gem5::ThreadContext* gem5::o3::CPU::tcBase ( ThreadID tid )

inline

Returns a pointer to a thread context.

Definition at line 566 of file cpu.hh.

References thread.

Referenced by addThreadToExitingList(), gem5::o3::Fetch::buildInst(), gem5::o3::Commit::clearStates(), exitThreads(), gem5::o3::LSQUnit::getLatestHtmUid(), gem5::o3::LSQUnit::insertLoad(), insertThread(), gem5::o3::LSQUnit::read(), gem5::o3::LSQUnit::squash(), and gem5::o3::LSQUnit::writebackStores().

◆ tick()

void gem5::o3::CPU::tick ( )

Ticks CPU, calling tick() on each stage, and checking the overall activity to see if the CPU should deschedule itself.

Definition at line 488 of file cpu.cc.

References _status, gem5::ActivityRecorder::active(), activityRec, gem5::ActivityRecorder::advance(), cleanUpRemovedInsts(), commit, cpuStats, decode, decodeQueue, DPRINTF, gem5::Drained, fetch, fetchQueue, gem5::FullSystem, Idle, iew, iewQueue, lastRunningCycle, removeInstsThisCycle, rename, renameQueue, gem5::Event::scheduled(), SwitchedOut, gem5::o3::Decode::tick(), gem5::o3::Rename::tick(), gem5::o3::Commit::tick(), gem5::o3::IEW::tick(), gem5::o3::Fetch::tick(), tickEvent, timeBuffer, gem5::o3::CPU::CPUStats::timesIdled, tryDrain(), and updateThreadPriority().

Referenced by CPU().

◆ totalInsts()

Counter gem5::o3::CPU::totalInsts ( ) const

override

Count the Total Instructions Committed in the CPU.

Definition at line 616 of file cpu.cc.

References gem5::ArmISA::i, thread, and gem5::statistics::total.

◆ totalOps()

Counter gem5::o3::CPU::totalOps ( ) const

override

Count the Total Ops (including micro ops) committed in the CPU.

Definition at line 628 of file cpu.cc.

References gem5::ArmISA::i, thread, and gem5::statistics::total.

◆ trap()

void gem5::o3::CPU::trap	(	const Fault &	fault,
		ThreadID	tid,
		const StaticInstPtr &	inst
	)

Traps to handle given fault.

Definition at line 844 of file cpu.cc.

Referenced by gem5::o3::Commit::commitHead(), processInterrupts(), and gem5::o3::DynInst::trap().

◆ tryDrain()

bool gem5::o3::CPU::tryDrain ( )

private

Check if the pipeline has drained and signal drain done.

This method checks if a drain has been requested and if the CPU has drained successfully (i.e., there are no instructions in the pipeline). If the CPU has drained, it deschedules the tick event and signals the drain manager.

Returns: False if a drain hasn't been requested or the CPU hasn't drained, true otherwise.

Definition at line 925 of file cpu.cc.

References DPRINTF, gem5::Draining, isCpuDrained(), gem5::Event::scheduled(), and tickEvent.

Referenced by tick().

◆ unscheduleTickEvent()

void gem5::o3::CPU::unscheduleTickEvent ( )

inlineprivate

Unschedule tick event, regardless of its current state.

Definition at line 137 of file cpu.hh.

References gem5::Event::scheduled(), gem5::Event::squash(), and tickEvent.

Referenced by haltContext(), and suspendContext().

◆ unserializeThread()

void gem5::o3::CPU::unserializeThread	(	CheckpointIn &	cp,
		ThreadID	tid
	)

override

Definition at line 857 of file cpu.cc.

References thread.

◆ updateThreadPriority()

void gem5::o3::CPU::updateThreadPriority ( )

Update The Order In Which We Process Threads.

Definition at line 1559 of file cpu.cc.

References activeThreads.

Referenced by tick().

◆ verifyMemoryMode()

void gem5::o3::CPU::verifyMemoryMode ( ) const

override

Definition at line 1055 of file cpu.cc.

References fatal, gem5::System::isTimingMode(), and system.

Referenced by drainResume().

◆ wakeCPU()

void gem5::o3::CPU::wakeCPU ( )

Wakes the CPU, rescheduling the CPU if it's not already active.

Definition at line 1513 of file cpu.cc.

References gem5::ActivityRecorder::active(), activityRec, cpuStats, DPRINTF, gem5::o3::CPU::CPUStats::idleCycles, lastRunningCycle, gem5::Event::scheduled(), and tickEvent.

Referenced by gem5::o3::InstructionQueue::cacheUnblocked(), gem5::o3::LSQUnit::completeStore(), drain(), gem5::o3::Fetch::finishTranslation(), gem5::o3::Fetch::processCacheCompletion(), gem5::o3::IEW::wakeCPU(), and wakeup().

◆ wakeup()

void gem5::o3::CPU::wakeup ( ThreadID tid )

overridevirtual

Definition at line 1534 of file cpu.cc.

References DPRINTF, gem5::ArmISA::status, gem5::ThreadContext::Suspended, thread, and wakeCPU().

Referenced by gem5::o3::LSQ::DcachePort::recvTimingSnoopReq().

Friends And Related Function Documentation

◆ ThreadContext

friend class ThreadContext

friend

Definition at line 99 of file cpu.hh.

Member Data Documentation

◆ _status

Status gem5::o3::CPU::_status

Overall CPU status.

Definition at line 115 of file cpu.hh.

Referenced by activateContext(), drainResume(), haltContext(), suspendContext(), switchOut(), takeOverFrom(), and tick().

◆ activeThreads

std::list<ThreadID> gem5::o3::CPU::activeThreads

protected

Active Threads List.

Definition at line 486 of file cpu.hh.

Referenced by activateThread(), deactivateThread(), haltContext(), numActiveThreads(), suspendContext(), and updateThreadPriority().

◆ activityRec

ActivityRecorder gem5::o3::CPU::activityRec

private

The activity recorder; used to tell if the CPU has any activity remaining or if it can go to idle and deschedule itself.

Definition at line 535 of file cpu.hh.

Referenced by activateContext(), activateStage(), activityThisCycle(), deactivateStage(), drain(), switchOut(), tick(), and wakeCPU().

◆ checker

gem5::Checker<DynInstPtr>* gem5::o3::CPU::checker

Pointer to the checker, which can dynamically verify instruction results at run time.

This can be set to NULL if it is not being used.

Definition at line 578 of file cpu.hh.

Referenced by gem5::o3::Commit::commitHead(), gem5::o3::Commit::commitInsts(), gem5::o3::DynInst::completeAcc(), gem5::o3::LSQUnit::completeStore(), gem5::o3::Commit::handleInterrupt(), gem5::o3::LSQ::pushRequest(), gem5::o3::IEW::startupStage(), gem5::o3::LSQUnit::storePostSend(), and switchOut().

◆ commit

Commit gem5::o3::CPU::commit

protected

The commit stage.

Definition at line 468 of file cpu.hh.

Referenced by deactivateThread(), drain(), drainResume(), drainSanityCheck(), htmSendAbortSignal(), init(), insertThread(), isCpuDrained(), pcState(), regProbePoints(), removeThread(), squashFromTC(), startup(), takeOverFrom(), and tick().

◆ commitRenameMap

UnifiedRenameMap gem5::o3::CPU::commitRenameMap[MaxThreads]

protected

The commit rename map.

Definition at line 480 of file cpu.hh.

Referenced by getWritableArchVecPredReg(), getWritableArchVecReg(), readArchCCReg(), readArchFloatReg(), readArchIntReg(), readArchVecElem(), readArchVecPredReg(), readArchVecReg(), setArchCCReg(), setArchFloatReg(), setArchIntReg(), setArchVecElem(), setArchVecPredReg(), and setArchVecReg().

◆ cpuStats

gem5::o3::CPU::CPUStats gem5::o3::CPU::cpuStats

◆ cpuWaitList

std::list<int> gem5::o3::CPU::cpuWaitList

Threads Scheduled to Enter CPU.

Definition at line 587 of file cpu.hh.

◆ decode

Decode gem5::o3::CPU::decode

protected

The decode stage.

Definition at line 459 of file cpu.hh.

Referenced by drainSanityCheck(), isCpuDrained(), removeThread(), startup(), takeOverFrom(), and tick().

◆ decodeQueue

TimeBuffer<DecodeStruct> gem5::o3::CPU::decodeQueue

The decode stage's instruction queue.

Definition at line 522 of file cpu.hh.

Referenced by drain(), removeThread(), and tick().

◆ exitingThreads

std::unordered_map<ThreadID, bool> gem5::o3::CPU::exitingThreads

protected

This is a list of threads that are trying to exit.

Each thread id is mapped to a boolean value denoting whether the thread is ready to exit.

Definition at line 493 of file cpu.hh.

Referenced by addThreadToExitingList(), exitThreads(), isThreadExiting(), and scheduleThreadExitEvent().

◆ fetch

Fetch gem5::o3::CPU::fetch

protected

The fetch stage.

Definition at line 456 of file cpu.hh.

Referenced by activateContext(), commitDrained(), deactivateThread(), drainResume(), drainSanityCheck(), gem5::o3::ThreadContext::getDecoderPtr(), getInstPort(), isCpuDrained(), regProbePoints(), removeThread(), startup(), takeOverFrom(), and tick().

◆ fetchQueue

TimeBuffer<FetchStruct> gem5::o3::CPU::fetchQueue

The fetch stage's instruction queue.

Definition at line 519 of file cpu.hh.

Referenced by drain(), removeThread(), and tick().

◆ freeList

UnifiedFreeList gem5::o3::CPU::freeList

protected

The free list.

Definition at line 474 of file cpu.hh.

Referenced by insertThread().

◆ globalSeqNum

InstSeqNum gem5::o3::CPU::globalSeqNum

The global sequence number counter.

Definition at line 572 of file cpu.hh.

Referenced by getAndIncrementInstSeq(), and takeOverFrom().

◆ iew

IEW gem5::o3::CPU::iew

protected

The issue/execute/writeback stages.

Definition at line 465 of file cpu.hh.

Referenced by drainSanityCheck(), getDataPort(), htmSendAbortSignal(), isCpuDrained(), pushRequest(), regProbePoints(), removeThread(), startup(), takeOverFrom(), and tick().

◆ iewQueue

TimeBuffer<IEWStruct> gem5::o3::CPU::iewQueue

The IEW stage's instruction queue.

Definition at line 528 of file cpu.hh.

Referenced by drain(), removeThread(), and tick().

◆ instcount

int gem5::o3::CPU::instcount

Count of total number of dynamic instructions in flight.

Definition at line 431 of file cpu.hh.

Referenced by gem5::o3::DynInst::DynInst(), and gem5::o3::DynInst::~DynInst().

◆ instList

std::list<DynInstPtr> gem5::o3::CPU::instList

List of all the instructions in flight.

Definition at line 435 of file cpu.hh.

Referenced by addInst(), cleanUpRemovedInsts(), dumpInsts(), gem5::o3::Commit::handleInterrupt(), isCpuDrained(), removeInstsNotInROB(), and removeInstsUntil().

◆ isa

std::vector<TheISA::ISA *> gem5::o3::CPU::isa

protected

Definition at line 498 of file cpu.hh.

Referenced by gem5::o3::ThreadContext::clearArchRegs(), gem5::o3::ThreadContext::flattenRegId(), gem5::o3::ThreadContext::getIsaPtr(), insertThread(), readMiscReg(), readMiscRegNoEffect(), setMiscReg(), and setMiscRegNoEffect().

◆ lastActivatedCycle

Tick gem5::o3::CPU::lastActivatedCycle

The cycle that the CPU was last activated by a new thread.

Definition at line 593 of file cpu.hh.

Referenced by activateContext().

◆ lastRunningCycle

Cycles gem5::o3::CPU::lastRunningCycle

The cycle that the CPU was last running, used for statistics.

Definition at line 590 of file cpu.hh.

Referenced by activateContext(), haltContext(), suspendContext(), takeOverFrom(), tick(), and wakeCPU().

◆ mmu

BaseMMU* gem5::o3::CPU::mmu

Definition at line 111 of file cpu.hh.

Referenced by demapPage(), gem5::o3::Fetch::fetchCacheLine(), gem5::o3::ThreadContext::getMMUPtr(), gem5::o3::LSQUnit::getMMUPtr(), and gem5::o3::DynInst::mwaitAtomic().

◆ ppDataAccessComplete

ProbePointArg<std::pair<DynInstPtr, PacketPtr> >* gem5::o3::CPU::ppDataAccessComplete

Definition at line 175 of file cpu.hh.

Referenced by gem5::o3::LSQUnit::completeDataAccess(), and regProbePoints().

◆ ppInstAccessComplete

ProbePointArg<PacketPtr>* gem5::o3::CPU::ppInstAccessComplete

Definition at line 174 of file cpu.hh.

Referenced by gem5::o3::Fetch::processCacheCompletion(), and regProbePoints().

◆ regFile

PhysRegFile gem5::o3::CPU::regFile

protected

The register file.

Definition at line 471 of file cpu.hh.

Referenced by getWritableArchVecPredReg(), getWritableArchVecReg(), getWritableVecPredReg(), getWritableVecReg(), readArchCCReg(), readArchFloatReg(), readArchIntReg(), readArchVecElem(), readArchVecPredReg(), readArchVecReg(), readCCReg(), readFloatReg(), readIntReg(), readVecElem(), readVecPredReg(), readVecReg(), setArchCCReg(), setArchFloatReg(), setArchIntReg(), setArchVecElem(), setArchVecPredReg(), setArchVecReg(), setCCReg(), setFloatReg(), setIntReg(), setVecElem(), setVecPredReg(), and setVecReg().

◆ removeInstsThisCycle

bool gem5::o3::CPU::removeInstsThisCycle

Records if instructions need to be removed this cycle due to being retired or squashed.

Definition at line 452 of file cpu.hh.

Referenced by cleanUpRemovedInsts(), removeFrontInst(), removeInstsNotInROB(), removeInstsUntil(), and tick().

◆ removeList

std::queue<ListIt> gem5::o3::CPU::removeList

List of all the instructions that will be removed at the end of this cycle.

Definition at line 440 of file cpu.hh.

Referenced by cleanUpRemovedInsts(), isCpuDrained(), removeFrontInst(), and squashInstIt().

◆ rename

Rename gem5::o3::CPU::rename

protected

The dispatch stage.

Definition at line 462 of file cpu.hh.

Referenced by drainSanityCheck(), isCpuDrained(), regProbePoints(), removeThread(), startup(), takeOverFrom(), and tick().

◆ renameMap

UnifiedRenameMap gem5::o3::CPU::renameMap[MaxThreads]

protected

The rename map.

Definition at line 477 of file cpu.hh.

Referenced by insertThread().

◆ renameQueue

TimeBuffer<RenameStruct> gem5::o3::CPU::renameQueue

The rename stage's instruction queue.

Definition at line 525 of file cpu.hh.

Referenced by drain(), removeThread(), and tick().

◆ rob

ROB gem5::o3::CPU::rob

protected

The re-order buffer.

Definition at line 483 of file cpu.hh.

Referenced by removeInstsNotInROB().

◆ scoreboard

Scoreboard gem5::o3::CPU::scoreboard

protected

Integer Register Scoreboard.

Definition at line 496 of file cpu.hh.

Referenced by insertThread().

◆ system

System* gem5::o3::CPU::system

Pointer to the system.

Definition at line 581 of file cpu.hh.

Referenced by gem5::o3::Fetch::finishTranslation(), gem5::o3::ThreadContext::getSystemPtr(), insertThread(), and verifyMemoryMode().

◆ thread

std::vector<ThreadState *> gem5::o3::CPU::thread

Pointers to all of the threads in the CPU.

Definition at line 584 of file cpu.hh.

Referenced by gem5::o3::Fetch::buildInst(), gem5::o3::LSQUnit::checkSnoop(), drainResume(), gem5::o3::Fetch::fetchCacheLine(), htmSendAbortSignal(), init(), instDone(), serializeThread(), squashFromTC(), tcBase(), totalInsts(), totalOps(), unserializeThread(), and wakeup().

◆ threadExitEvent

EventFunctionWrapper gem5::o3::CPU::threadExitEvent

private

The exit event used for terminating all ready-to-exit threads.

Definition at line 123 of file cpu.hh.

Referenced by scheduleThreadExitEvent().

◆ threadMap

std::map<ThreadID, unsigned> gem5::o3::CPU::threadMap

Mapping for system thread id to cpu id.

Definition at line 596 of file cpu.hh.

◆ tickEvent

EventFunctionWrapper gem5::o3::CPU::tickEvent

private

The tick event used for scheduling CPU ticks.

Definition at line 120 of file cpu.hh.

Referenced by drain(), drainResume(), haltContext(), scheduleTickEvent(), takeOverFrom(), tick(), tryDrain(), unscheduleTickEvent(), and wakeCPU().

◆ tids

std::vector<ThreadID> gem5::o3::CPU::tids

Available thread ids in the cpu.

Definition at line 599 of file cpu.hh.

Referenced by getFreeTid().

◆ timeBuffer

TimeBuffer<TimeStruct> gem5::o3::CPU::timeBuffer

The main time buffer to do backwards communication.

Definition at line 516 of file cpu.hh.

Referenced by drain(), removeThread(), and tick().

The documentation for this class was generated from the following files:

cpu/o3/cpu.hh
cpu/o3/cpu.cc

Classes

Public Types

Public Member Functions

Public Attributes

Protected Attributes

Private Member Functions

Private Attributes

Friends

Detailed Description

Member Typedef Documentation

◆ ListIt

◆ LSQRequest

Member Enumeration Documentation

◆ StageIdx

◆ Status

Constructor & Destructor Documentation

◆ CPU()

Member Function Documentation

◆ activateContext()

◆ activateStage()

◆ activateThread()

◆ activityThisCycle()

◆ addInst()

◆ addThreadToExitingList()

◆ cleanUpRemovedInsts()

◆ commitDrained()

◆ deactivateStage()

◆ deactivateThread()

◆ demapPage()

◆ drain()

◆ drainResume()

◆ drainSanityCheck()

◆ dumpInsts()

◆ exitThreads()

◆ getAndIncrementInstSeq()

◆ getDataPort()

◆ getFreeTid()

◆ getInstPort()

◆ getInterrupts()

◆ getWritableArchVecPredReg()

◆ getWritableArchVecReg()

◆ getWritableVecPredReg()

◆ getWritableVecReg()

◆ halt()

◆ haltContext()

◆ htmSendAbortSignal()

◆ init()

◆ insertThread()

◆ instDone()

◆ isCpuDrained()

◆ isDraining()

◆ isThreadExiting()

◆ numActiveThreads()

◆ pcState() [1/2]

◆ pcState() [2/2]

◆ processInterrupts()

◆ pushRequest()

◆ readArchCCReg()

◆ readArchFloatReg()

◆ readArchIntReg()

◆ readArchVecElem()

◆ readArchVecPredReg()

◆ readArchVecReg()

◆ readCCReg()

◆ readFloatReg()

◆ readIntReg()

◆ readMiscReg()

◆ readMiscRegNoEffect()

◆ readVecElem()

◆ readVecPredReg()

◆ readVecReg()

◆ regProbePoints()

◆ removeFrontInst()

◆ removeInstsNotInROB()

◆ removeInstsUntil()

◆ removeThread()

◆ scheduleThreadExitEvent()

◆ scheduleTickEvent()

◆ serializeThread()

◆ setArchCCReg()