rename_map.hh

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#ifndef __CPU_O3_RENAME_MAP_HH__
#define __CPU_O3_RENAME_MAP_HH__
 
#include <iostream>
#include <utility>
#include <vector>
 
#include "arch/generic/isa.hh"
#include "cpu/o3/free_list.hh"
#include "cpu/o3/regfile.hh"
#include "cpu/reg_class.hh"
 
namespace gem5
{
 
namespace o3
{
 
class SimpleRenameMap
{
  private:
    using Arch2PhysMap = std::vector<PhysRegIdPtr>;
    Arch2PhysMap map;
  public:
    using iterator = Arch2PhysMap::iterator;
    using const_iterator = Arch2PhysMap::const_iterator;
  private:
 
    SimpleFreeList *freeList;
 
    RegId zeroReg;
 
  public:
 
    SimpleRenameMap();
 
    void init(const RegClass &reg_class, SimpleFreeList *_freeList);
 
    typedef std::pair<PhysRegIdPtr, PhysRegIdPtr> RenameInfo;
 
    RenameInfo rename(const RegId& arch_reg);
 
    PhysRegIdPtr
    lookup(const RegId& arch_reg) const
    {
        assert(arch_reg.flatIndex() <= map.size());
        return map[arch_reg.flatIndex()];
    }
 
    void
    setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
    {
        assert(arch_reg.flatIndex() <= map.size());
        map[arch_reg.flatIndex()] = phys_reg;
    }
 
    unsigned numFreeEntries() const { return freeList->numFreeRegs(); }
 
    size_t numArchRegs() const { return map.size(); }
 
    iterator begin() { return map.begin(); }
    const_iterator begin() const { return map.begin(); }
    const_iterator cbegin() const { return map.cbegin(); }
    iterator end() { return map.end(); }
    const_iterator end() const { return map.end(); }
    const_iterator cend() const { return map.cend(); }
};
 
class UnifiedRenameMap
{
  private:
    SimpleRenameMap intMap;
 
    SimpleRenameMap floatMap;
 
    SimpleRenameMap ccMap;
 
    SimpleRenameMap vecMap;
 
    SimpleRenameMap vecElemMap;
 
    SimpleRenameMap predMap;
 
    PhysRegFile *regFile;
 
  public:
 
    typedef SimpleRenameMap::RenameInfo RenameInfo;
 
    UnifiedRenameMap() : regFile(nullptr) {};
 
    ~UnifiedRenameMap() {};
 
    void init(const BaseISA::RegClasses &regClasses,
              PhysRegFile *_regFile, UnifiedFreeList *freeList);
 
    RenameInfo
    rename(const RegId& arch_reg)
    {
        switch (arch_reg.classValue()) {
          case IntRegClass:
            return intMap.rename(arch_reg);
          case FloatRegClass:
            return floatMap.rename(arch_reg);
          case VecRegClass:
            return vecMap.rename(arch_reg);
          case VecElemClass:
            return vecElemMap.rename(arch_reg);
          case VecPredRegClass:
            return predMap.rename(arch_reg);
          case CCRegClass:
            return ccMap.rename(arch_reg);
          case MiscRegClass:
            {
                // misc regs aren't really renamed, just remapped
                PhysRegIdPtr phys_reg = lookup(arch_reg);
                // Set the new register to the previous one to keep the same
                // mapping throughout the execution.
                return RenameInfo(phys_reg, phys_reg);
            }
 
          default:
            panic("rename rename(): unknown reg class %s\n",
                  arch_reg.className());
        }
    }
 
    PhysRegIdPtr
    lookup(const RegId& arch_reg) const
    {
        switch (arch_reg.classValue()) {
          case IntRegClass:
            return intMap.lookup(arch_reg);
 
          case FloatRegClass:
            return  floatMap.lookup(arch_reg);
 
          case VecRegClass:
            return  vecMap.lookup(arch_reg);
 
          case VecElemClass:
            return  vecElemMap.lookup(arch_reg);
 
          case VecPredRegClass:
            return predMap.lookup(arch_reg);
 
          case CCRegClass:
            return ccMap.lookup(arch_reg);
 
          case MiscRegClass:
            // misc regs aren't really renamed, they keep the same
            // mapping throughout the execution.
            return regFile->getMiscRegId(arch_reg.flatIndex());
 
          default:
            panic("rename lookup(): unknown reg class %s\n",
                  arch_reg.className());
        }
    }
 
    void
    setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
    {
        assert(phys_reg->is(arch_reg.classValue()));
        switch (arch_reg.classValue()) {
          case IntRegClass:
            return intMap.setEntry(arch_reg, phys_reg);
 
          case FloatRegClass:
            return floatMap.setEntry(arch_reg, phys_reg);
 
          case VecRegClass:
            return vecMap.setEntry(arch_reg, phys_reg);
 
          case VecElemClass:
            return vecElemMap.setEntry(arch_reg, phys_reg);
 
          case VecPredRegClass:
            return predMap.setEntry(arch_reg, phys_reg);
 
          case CCRegClass:
            return ccMap.setEntry(arch_reg, phys_reg);
 
          case MiscRegClass:
            // Misc registers do not actually rename, so don't change
            // their mappings.  We end up here when a commit or squash
            // tries to update or undo a hardwired misc reg nmapping,
            // which should always be setting it to what it already is.
            assert(phys_reg == lookup(arch_reg));
            return;
 
          default:
            panic("rename setEntry(): unknown reg class %s\n",
                  arch_reg.className());
        }
    }
 
    unsigned
    numFreeEntries() const
    {
        return std::min({intMap.numFreeEntries(),
                         floatMap.numFreeEntries(),
                         vecMap.numFreeEntries(),
                         vecElemMap.numFreeEntries(),
                         predMap.numFreeEntries()});
    }
 
    unsigned numFreeIntEntries() const { return intMap.numFreeEntries(); }
    unsigned numFreeFloatEntries() const { return floatMap.numFreeEntries(); }
    unsigned numFreeVecEntries() const { return vecMap.numFreeEntries(); }
    unsigned
    numFreeVecElemEntries() const
    {
        return vecElemMap.numFreeEntries();
    }
    unsigned numFreePredEntries() const { return predMap.numFreeEntries(); }
    unsigned numFreeCCEntries() const { return ccMap.numFreeEntries(); }
 
    bool
    canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t vectorRegs,
              uint32_t vecElemRegs, uint32_t vecPredRegs,
              uint32_t ccRegs) const
    {
        return intRegs <= intMap.numFreeEntries() &&
            floatRegs <= floatMap.numFreeEntries() &&
            vectorRegs <= vecMap.numFreeEntries() &&
            vecElemRegs <= vecElemMap.numFreeEntries() &&
            vecPredRegs <= predMap.numFreeEntries() &&
            ccRegs <= ccMap.numFreeEntries();
    }
};
 
} // namespace o3
} // namespace gem5
 
#endif //__CPU_O3_RENAME_MAP_HH__