rename_map.cc

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#include "cpu/o3/rename_map.hh"
 
#include <vector>
 
#include "arch/vecregs.hh"
#include "cpu/reg_class.hh"
#include "debug/Rename.hh"
 
namespace gem5
{
 
namespace o3
{
 
SimpleRenameMap::SimpleRenameMap()
    : freeList(NULL), zeroReg(IntRegClass, 0)
{
}
 
 
void
SimpleRenameMap::init(const RegClass &reg_class, SimpleFreeList *_freeList)
{
    assert(freeList == NULL);
    assert(map.empty());
 
    map.resize(reg_class.size());
    freeList = _freeList;
    zeroReg = RegId(IntRegClass, reg_class.zeroReg());
}
 
SimpleRenameMap::RenameInfo
SimpleRenameMap::rename(const RegId& arch_reg)
{
    PhysRegIdPtr renamed_reg;
    // Record the current physical register that is renamed to the
    // requested architected register.
    PhysRegIdPtr prev_reg = map[arch_reg.flatIndex()];
 
    if (arch_reg == zeroReg) {
        assert(prev_reg->index() == zeroReg.index());
        renamed_reg = prev_reg;
    } else if (prev_reg->getNumPinnedWrites() > 0) {
        // Do not rename if the register is pinned
        assert(arch_reg.getNumPinnedWrites() == 0);  // Prevent pinning the
                                                     // same register twice
        DPRINTF(Rename, "Renaming pinned reg, numPinnedWrites %d\n",
                prev_reg->getNumPinnedWrites());
        renamed_reg = prev_reg;
        renamed_reg->decrNumPinnedWrites();
    } else {
        renamed_reg = freeList->getReg();
        map[arch_reg.flatIndex()] = renamed_reg;
        renamed_reg->setNumPinnedWrites(arch_reg.getNumPinnedWrites());
        renamed_reg->setNumPinnedWritesToComplete(
            arch_reg.getNumPinnedWrites() + 1);
    }
 
    DPRINTF(Rename, "Renamed reg %d to physical reg %d (%d) old mapping was"
            " %d (%d)\n",
            arch_reg, renamed_reg->flatIndex(), renamed_reg->flatIndex(),
            prev_reg->flatIndex(), prev_reg->flatIndex());
 
    return RenameInfo(renamed_reg, prev_reg);
}
 
 
/**** UnifiedRenameMap methods ****/
 
void
UnifiedRenameMap::init(const BaseISA::RegClasses &regClasses,
        PhysRegFile *_regFile, UnifiedFreeList *freeList)
{
    regFile = _regFile;
 
    intMap.init(regClasses.at(IntRegClass), &(freeList->intList));
    floatMap.init(regClasses.at(FloatRegClass), &(freeList->floatList));
    vecMap.init(regClasses.at(VecRegClass), &(freeList->vecList));
    vecElemMap.init(regClasses.at(VecElemClass), &(freeList->vecElemList));
    predMap.init(regClasses.at(VecPredRegClass), &(freeList->predList));
    ccMap.init(regClasses.at(CCRegClass), &(freeList->ccList));
}
 
} // namespace o3
} // namespace gem5