generator.cc

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 * Copyright (c) 2024 Arm Limited
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 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
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 * documentation and/or other materials provided with the distribution;
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 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 */
 
#include "mem/ruby/protocol/chi/tlm/generator.hh"
 
#include "mem/ruby/protocol/chi/tlm/controller.hh"
#include "debug/TLM.hh"
 
namespace gem5 {
 
namespace tlm::chi {
 
bool
TlmGenerator::Transaction::Expectation::run(Transaction *tran)
{
    auto res_print = csprintf("Checking %s...", name());
    if (cb(tran)) {
        inform("%s\n", res_print + " Success ");
        return true;
    } else {
        inform("%s\n", res_print + " Fail ");
        return false;
    }
}
TlmGenerator::Transaction::Expectation::run(Transaction *tran) {…}
 
bool
TlmGenerator::Transaction::Assertion::run(Transaction *tran)
{
    if (Expectation::run(tran)) {
        return true;
    } else {
        panic("Failing assertion\n");
    }
}
TlmGenerator::Transaction::Assertion::run(Transaction *tran) {…}
 
TlmGenerator::Transaction::Transaction(ARM::CHI::Payload *pa, ARM::CHI::Phase &ph)
  : passed(true), parent(nullptr), _payload(pa), _phase(ph)
{
    _payload->ref();
}
TlmGenerator::Transaction::Transaction(ARM::CHI::Payload *pa, ARM::CHI::Phase &ph) {…}
 
TlmGenerator::Transaction::~Transaction()
{
    _payload->unref();
}
TlmGenerator::Transaction::~Transaction() {…}
 
void
TlmGenerator::Transaction::setGenerator(TlmGenerator *gen)
{
    parent = gen;
}
TlmGenerator::Transaction::setGenerator(TlmGenerator *gen) {…}
 
std::string
TlmGenerator::Transaction::str() const
{
    return transactionToString(*_payload, _phase);
}
TlmGenerator::Transaction::str() const {…}
 
void
TlmGenerator::Transaction::inject()
{
    parent->inject(this);
}
TlmGenerator::Transaction::inject() {…}
 
bool
TlmGenerator::Transaction::hasCallbacks() const
{
    return !actions.empty();
}
TlmGenerator::Transaction::hasCallbacks() const {…}
 
bool
TlmGenerator::Transaction::failed() const
{
    return !passed;
}
TlmGenerator::Transaction::failed() const {…}
 
void
TlmGenerator::Transaction::addCallback(ActionPtr &&action)
{
    actions.push_back(std::move(action));
}
TlmGenerator::Transaction::addCallback(ActionPtr &&action) {…}
 
void
TlmGenerator::Transaction::runCallbacks()
{
    // print transaction
    auto it = actions.begin();
    while (it != actions.end()) {
        const bool is_passing = (*it)->run(this);
        if (!is_passing) {
            passed = false;
        }
        bool wait = (*it)->wait();
 
        it = actions.erase(it);
 
        if (wait) {
            break;
        }
    }
}
TlmGenerator::Transaction::runCallbacks() {…}
 
void
TlmGenerator::TransactionEvent::process()
{
    transaction->inject();
}
TlmGenerator::TransactionEvent::process() {…}
 
TlmGenerator::TlmGenerator(const Params &p)
  : SimObject(p), cpuId(p.cpu_id), controller(p.chi_controller)
{
    controller->bw = [this] (ARM::CHI::Payload *payload, ARM::CHI::Phase *phase)
    {
        this->recv(payload, phase);
    };
 
    registerExitCallback([this](){ passFailCheck(); });
}
TlmGenerator::TlmGenerator(const Params &p) {…}
 
void
TlmGenerator::scheduleTransaction(Tick when, Transaction *transaction)
{
    transaction->setGenerator(this);
 
    auto event = new TransactionEvent(transaction, when);
 
    scheduledTransactions.push(event);
 
    schedule(event, when);
}
TlmGenerator::scheduleTransaction(Tick when, Transaction *transaction) {…}
 
void
TlmGenerator::inject(Transaction *transaction)
{
    auto payload = transaction->payload();
    ARM::CHI::Phase &phase = transaction->phase();
 
    if (transaction->hasCallbacks())
        pendingTransactions.insert({phase.txn_id, transaction});
 
    DPRINTF(TLM, "[c%d] send %s\n", cpuId, transactionToString(*payload, phase));
 
    controller->sendMsg(*payload, phase);
}
TlmGenerator::inject(Transaction *transaction) {…}
 
void
TlmGenerator::recv(ARM::CHI::Payload *payload, ARM::CHI::Phase *phase)
{
    DPRINTF(TLM, "[c%d] rcvd %s\n", cpuId, transactionToString(*payload, *phase));
 
    auto txn_id = phase->txn_id;
    if (auto it = pendingTransactions.find(txn_id);
        it != pendingTransactions.end()) {
        // Copy the new phase
        it->second->phase() = *phase;
 
        // Check existing expectations
        it->second->runCallbacks();
    } else {
        warn("Transaction untested\n");
    }
}
TlmGenerator::recv(ARM::CHI::Payload *payload, ARM::CHI::Phase *phase) {…}
 
void
TlmGenerator::passFailCheck()
{
    for (auto [txn_id, transaction] : pendingTransactions) {
        // We are failing either if a condition hasn't been met,
        // or if there are pending actions when simulation exits
        if (transaction->failed()) {
            inform(" Suite Fail: failed transaction ");
            return;
        }
        if (transaction->hasCallbacks()) {
            inform(" Suite Fail: non-empty action queue ");
            return;
        }
    }
    inform(" Suite Success ");
}
TlmGenerator::passFailCheck() {…}
 
} // namespace tlm::chi
 
} // namespace gem5