generator.hh

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/*
 * Copyright (c) 2024 Arm Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 */
 
#ifndef __MEM_RUBY_PROTOCOL_CHI_TLM_GENERATOR_HH__
#define __MEM_RUBY_PROTOCOL_CHI_TLM_GENERATOR_HH__
 
#include <queue>
#include <unordered_map>
 
#include <ARM/TLM/arm_chi.h>
 
#include "mem/ruby/protocol/chi/tlm/utils.hh"
#include "params/TlmGenerator.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
 
namespace gem5 {
 
namespace tlm::chi {
 
class CacheController;
 
class TlmGenerator : public SimObject
{
  public:
    PARAMS(TlmGenerator);
    TlmGenerator(const Params &p);
 
    class Transaction
    {
      public:
        class Action
        {
          public:
            using Callback = std::function<
                bool(Transaction *tran)
            >;
 
            Action(Callback _cb, bool waiting)
              : cb(_cb), _wait(waiting)
            {}
            Action(Callback _cb, bool waiting) {…}
            virtual ~Action() {};
 
            /* A basic action always returns true */
            virtual bool
            run(Transaction *tran)
            {
                cb(tran);
                return true;
            }
            run(Transaction *tran) {…}
 
            bool wait() const { return _wait; }
 
          protected:
            Callback cb;
            bool _wait;
        };
        class Action {…};
 
        class Expectation : public Action
        {
          public:
            Expectation(std::string exp_name, Callback _cb)
              : Action(_cb, false), _name(exp_name)
            {}
            Expectation(std::string exp_name, Callback _cb) {…}
 
            bool run(Transaction *tran) override;
 
            std::string name() const { return _name; }
 
          private:
            std::string _name;
        };
        class Expectation : public Action {…};
 
        class Assertion : public Expectation
        {
          public:
            Assertion(std::string exp_name, Callback _cb)
              : Expectation(exp_name, _cb)
            {}
            Assertion(std::string exp_name, Callback _cb) {…}
 
            bool run(Transaction *tran) override;
        };
        class Assertion : public Expectation {…};
 
        using ActionPtr = std::unique_ptr<Action>;
        using Actions = std::list<ActionPtr>;
 
        Transaction(const Transaction &rhs) = delete;
        Transaction(ARM::CHI::Payload *pa, ARM::CHI::Phase &ph);
        ~Transaction();
 
        void setGenerator(TlmGenerator *gen);
 
        std::string str() const;
 
        void inject();
 
        bool failed() const;
 
        bool hasCallbacks() const;
 
        void addCallback(ActionPtr &&action);
 
        void runCallbacks();
 
        ARM::CHI::Payload* payload() const { return _payload; }
        ARM::CHI::Phase& phase() { return _phase; }
 
      private:
        Actions actions;
        bool passed;
 
        TlmGenerator *parent;
        ARM::CHI::Payload *_payload;
        ARM::CHI::Phase _phase;
    };
    class Transaction {…};
 
    void scheduleTransaction(Tick when, Transaction *tr);
 
  protected:
    struct TransactionEvent : public Event
    {
      public:
        struct Compare
        {
            bool
            operator()(const TransactionEvent *lhs,
                       const TransactionEvent *rhs)
            {
                return lhs->when < rhs->when;
            }
            operator()(const TransactionEvent *lhs, {…}
        };
        struct Compare {…};
 
        TransactionEvent(Transaction *_transaction,
                         Tick _when)
          : Event(), transaction(_transaction), when(_when)
        {}
        TransactionEvent(Transaction *_transaction, {…}
 
        void process() override;
 
        const char*
        description() const override
        {
            return "CHI Transaction event";
        }
        description() const override {…}
 
        Transaction *transaction;
        Tick when;
    };
    struct TransactionEvent : public Event {…};
 
    void inject(Transaction *transaction);
    void recv(ARM::CHI::Payload *payload, ARM::CHI::Phase *phase);
    void passFailCheck();
 
  protected:
    uint8_t cpuId;
 
    using SchedulingQueue = std::priority_queue<TransactionEvent*,
        std::vector<TransactionEvent*>,
        TransactionEvent::Compare>;
 
    SchedulingQueue scheduledTransactions;
 
    std::unordered_map<uint16_t, Transaction*> pendingTransactions;
 
    CacheController *controller;
};
class TlmGenerator : public SimObject {…};
 
} // namespace tlm::chi
 
} // namespace gem5
 
#endif // __MEM_RUBY_PROTOCOL_CHI_TLM_GENERATOR_HH__