tlbi_op.cc

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 * Copyright (c) 2018-2024 Arm Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
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 * terms below provided that you ensure that this notice is replicated
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 * Redistribution and use in source and binary forms, with or without
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 * met: redistributions of source code must retain the above copyright
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 * redistributions in binary form must reproduce the above copyright
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 */
 
#include "arch/arm/tlbi_op.hh"
 
#include "arch/arm/mmu.hh"
#include "cpu/checker/cpu.hh"
 
namespace gem5
{
 
namespace ArmISA {
 
bool
TLBIOp::match(TlbEntry* te, vmid_t vmid) const
{
    return matchEntry(te, vmid) && (attr != Attr::ExcludeXS || !te->xs);
}
TLBIOp::match(TlbEntry* te, vmid_t vmid) const {…}
 
void
TLBIALL::operator()(ThreadContext* tc)
{
    el2Enabled = EL2Enabled(tc);
    currentEL = currEL(tc);
 
    getMMUPtr(tc)->flush(*this);
 
    // If CheckerCPU is connected, need to notify it of a flush
    CheckerCPU *checker = tc->getCheckerCpuPtr();
    if (checker) {
        getMMUPtr(checker)->flush(*this);
    }
}
TLBIALL::operator()(ThreadContext* tc) {…}
 
bool
TLBIALL::matchEntry(TlbEntry* te, vmid_t vmid) const
{
    return te->valid && ss == te->ss &&
        (te->vmid == vmid || el2Enabled) &&
        te->checkRegime(targetRegime);
}
TLBIALL::matchEntry(TlbEntry* te, vmid_t vmid) const {…}
 
void
ITLBIALL::operator()(ThreadContext* tc)
{
    el2Enabled = EL2Enabled(tc);
    getMMUPtr(tc)->iflush(*this);
}
ITLBIALL::operator()(ThreadContext* tc) {…}
 
bool
ITLBIALL::matchEntry(TlbEntry* te, vmid_t vmid) const
{
    return TLBIALL::matchEntry(te, vmid) && (te->type & TypeTLB::instruction);
}
ITLBIALL::matchEntry(TlbEntry* te, vmid_t vmid) const {…}
 
void
DTLBIALL::operator()(ThreadContext* tc)
{
    el2Enabled = EL2Enabled(tc);
    getMMUPtr(tc)->dflush(*this);
}
DTLBIALL::operator()(ThreadContext* tc) {…}
 
bool
DTLBIALL::matchEntry(TlbEntry* te, vmid_t vmid) const
{
    return TLBIALL::matchEntry(te, vmid) && (te->type & TypeTLB::data);
}
DTLBIALL::matchEntry(TlbEntry* te, vmid_t vmid) const {…}
 
void
TLBIALLEL::operator()(ThreadContext* tc)
{
    getMMUPtr(tc)->flush(*this);
 
    // If CheckerCPU is connected, need to notify it of a flush
    CheckerCPU *checker = tc->getCheckerCpuPtr();
    if (checker) {
        getMMUPtr(checker)->flush(*this);
    }
}
TLBIALLEL::operator()(ThreadContext* tc) {…}
 
bool
TLBIALLEL::matchEntry(TlbEntry* te, vmid_t vmid) const
{
    return te->valid && ss == te->ss &&
        te->checkRegime(targetRegime);
}
TLBIALLEL::matchEntry(TlbEntry* te, vmid_t vmid) const {…}
 
void
TLBIVMALL::operator()(ThreadContext* tc)
{
    el2Enabled = EL2Enabled(tc);
 
    getMMUPtr(tc)->flush(*this);
 
    // If CheckerCPU is connected, need to notify it of a flush
    CheckerCPU *checker = tc->getCheckerCpuPtr();
    if (checker) {
        getMMUPtr(checker)->flush(*this);
    }
}
TLBIVMALL::operator()(ThreadContext* tc) {…}
 
bool
TLBIVMALL::matchEntry(TlbEntry* te, vmid_t vmid) const
{
    return te->valid && ss == te->ss &&
        te->checkRegime(targetRegime) &&
        (te->vmid == vmid || !el2Enabled || !useVMID(targetRegime));
}
TLBIVMALL::matchEntry(TlbEntry* te, vmid_t vmid) const {…}
 
void
TLBIASID::operator()(ThreadContext* tc)
{
    el2Enabled = EL2Enabled(tc);
 
    getMMUPtr(tc)->flushStage1(*this);
    CheckerCPU *checker = tc->getCheckerCpuPtr();
    if (checker) {
        getMMUPtr(checker)->flushStage1(*this);
    }
}
TLBIASID::operator()(ThreadContext* tc) {…}
 
bool
TLBIASID::matchEntry(TlbEntry* te, vmid_t vmid) const
{
    return te->valid && te->asid == asid &&
        ss == te->ss &&
        te->checkRegime(targetRegime) &&
        (te->vmid == vmid || !el2Enabled || !useVMID(targetRegime));
}
TLBIASID::matchEntry(TlbEntry* te, vmid_t vmid) const {…}
 
void
ITLBIASID::operator()(ThreadContext* tc)
{
    el2Enabled = EL2Enabled(tc);
    getMMUPtr(tc)->iflush(*this);
}
ITLBIASID::operator()(ThreadContext* tc) {…}
 
bool
ITLBIASID::matchEntry(TlbEntry* te, vmid_t vmid) const
{
    return TLBIASID::matchEntry(te, vmid) && (te->type & TypeTLB::instruction);
}
ITLBIASID::matchEntry(TlbEntry* te, vmid_t vmid) const {…}
 
void
DTLBIASID::operator()(ThreadContext* tc)
{
    el2Enabled = EL2Enabled(tc);
    getMMUPtr(tc)->dflush(*this);
}
DTLBIASID::operator()(ThreadContext* tc) {…}
 
bool
DTLBIASID::matchEntry(TlbEntry* te, vmid_t vmid) const
{
    return TLBIASID::matchEntry(te, vmid) && (te->type & TypeTLB::data);
}
DTLBIASID::matchEntry(TlbEntry* te, vmid_t vmid) const {…}
 
void
TLBIALLN::operator()(ThreadContext* tc)
{
    getMMUPtr(tc)->flush(*this);
 
    CheckerCPU *checker = tc->getCheckerCpuPtr();
    if (checker) {
        getMMUPtr(checker)->flush(*this);
    }
}
TLBIALLN::operator()(ThreadContext* tc) {…}
 
bool
TLBIALLN::matchEntry(TlbEntry* te, vmid_t vmid) const
{
    return te->valid && te->ss == SecurityState::NonSecure &&
        te->checkRegime(targetRegime);
}
TLBIALLN::matchEntry(TlbEntry* te, vmid_t vmid) const {…}
 
TlbEntry::KeyType
TLBIMVAA::lookupGen(vmid_t vmid) const
{
    TlbEntry::KeyType lookup_data;
    lookup_data.va = sext<56>(addr);
    lookup_data.ignoreAsn = true;
    lookup_data.vmid = vmid;
    lookup_data.ss = ss;
    lookup_data.functional = true;
    lookup_data.targetRegime = targetRegime;
    lookup_data.mode = BaseMMU::Read;
    return lookup_data;
}
TLBIMVAA::lookupGen(vmid_t vmid) const {…}
 
void
TLBIMVAA::operator()(ThreadContext* tc)
{
    getMMUPtr(tc)->flushStage1(*this);
 
    CheckerCPU *checker = tc->getCheckerCpuPtr();
    if (checker) {
        getMMUPtr(checker)->flushStage1(*this);
    }
}
TLBIMVAA::operator()(ThreadContext* tc) {…}
 
bool
TLBIMVAA::matchEntry(TlbEntry* te, vmid_t vmid) const
{
    TlbEntry::KeyType lookup_data = lookupGen(vmid);
 
    return te->match(lookup_data) && (!lastLevel || !te->partial);
}
TLBIMVAA::matchEntry(TlbEntry* te, vmid_t vmid) const {…}
 
TlbEntry::KeyType
TLBIMVA::lookupGen(vmid_t vmid) const
{
    TlbEntry::KeyType lookup_data;
    lookup_data.va = sext<56>(addr);
    lookup_data.asn = asid;
    lookup_data.ignoreAsn = false;
    lookup_data.vmid = vmid;
    lookup_data.ss = ss;
    lookup_data.functional = true;
    lookup_data.targetRegime = targetRegime;
    lookup_data.mode = BaseMMU::Read;
 
    return lookup_data;
}
TLBIMVA::lookupGen(vmid_t vmid) const {…}
 
void
TLBIMVA::operator()(ThreadContext* tc)
{
    getMMUPtr(tc)->flushStage1(*this);
 
    CheckerCPU *checker = tc->getCheckerCpuPtr();
    if (checker) {
        getMMUPtr(checker)->flushStage1(*this);
    }
}
TLBIMVA::operator()(ThreadContext* tc) {…}
 
bool
TLBIMVA::matchEntry(TlbEntry* te, vmid_t vmid) const
{
    TlbEntry::KeyType lookup_data = lookupGen(vmid);
 
    return te->match(lookup_data) && (!lastLevel || !te->partial);
}
TLBIMVA::matchEntry(TlbEntry* te, vmid_t vmid) const {…}
 
void
ITLBIMVA::operator()(ThreadContext* tc)
{
    getMMUPtr(tc)->iflush(*this);
}
ITLBIMVA::operator()(ThreadContext* tc) {…}
 
bool
ITLBIMVA::matchEntry(TlbEntry* te, vmid_t vmid) const
{
    return TLBIMVA::matchEntry(te, vmid) && (te->type & TypeTLB::instruction);
}
ITLBIMVA::matchEntry(TlbEntry* te, vmid_t vmid) const {…}
 
void
DTLBIMVA::operator()(ThreadContext* tc)
{
    getMMUPtr(tc)->dflush(*this);
}
DTLBIMVA::operator()(ThreadContext* tc) {…}
 
bool
DTLBIMVA::matchEntry(TlbEntry* te, vmid_t vmid) const
{
    return TLBIMVA::matchEntry(te, vmid) && (te->type & TypeTLB::data);
}
DTLBIMVA::matchEntry(TlbEntry* te, vmid_t vmid) const {…}
 
void
TLBIIPA::operator()(ThreadContext* tc)
{
    getMMUPtr(tc)->flushStage2(*this);
 
    CheckerCPU *checker = tc->getCheckerCpuPtr();
    if (checker) {
        getMMUPtr(checker)->flushStage2(*this);
    }
}
TLBIIPA::operator()(ThreadContext* tc) {…}
 
TlbEntry::KeyType
TLBIIPA::lookupGen(vmid_t vmid) const
{
    TlbEntry::KeyType lookup_data;
    lookup_data.va = szext<56>(addr);
    lookup_data.ignoreAsn = true;
    lookup_data.vmid = vmid;
    lookup_data.ss = ss;
    lookup_data.functional = true;
    lookup_data.targetRegime = targetRegime;
    lookup_data.mode = BaseMMU::Read;
    return lookup_data;
}
TLBIIPA::lookupGen(vmid_t vmid) const {…}
 
bool
TLBIIPA::matchEntry(TlbEntry* te, vmid_t vmid) const
{
    TlbEntry::KeyType lookup_data = lookupGen(vmid);
 
    return te->match(lookup_data) && (!lastLevel || !te->partial) &&
        ipaSpace == te->ipaSpace;
}
TLBIIPA::matchEntry(TlbEntry* te, vmid_t vmid) const {…}
 
bool
TLBIRMVA::matchEntry(TlbEntry* te, vmid_t vmid) const
{
    TlbEntry::KeyType lookup_data = lookupGen(vmid);
    lookup_data.size = rangeSize();
 
    auto addr_match = te->match(lookup_data) && (!lastLevel || !te->partial);
    if (addr_match) {
        return tgMap[rangeData.tg] == te->tg &&
        (resTLBIttl(rangeData.tg, rangeData.ttl) ||
            rangeData.ttl == te->lookupLevel);
    } else {
        return false;
    }
}
TLBIRMVA::matchEntry(TlbEntry* te, vmid_t vmid) const {…}
 
bool
TLBIRMVAA::matchEntry(TlbEntry* te, vmid_t vmid) const
{
    TlbEntry::KeyType lookup_data = lookupGen(vmid);
    lookup_data.size = rangeSize();
 
    auto addr_match = te->match(lookup_data) && (!lastLevel || !te->partial);
    if (addr_match) {
        return tgMap[rangeData.tg] == te->tg &&
        (resTLBIttl(rangeData.tg, rangeData.ttl) ||
            rangeData.ttl == te->lookupLevel);
    } else {
        return false;
    }
}
TLBIRMVAA::matchEntry(TlbEntry* te, vmid_t vmid) const {…}
 
bool
TLBIRIPA::matchEntry(TlbEntry* te, vmid_t vmid) const
{
    TlbEntry::KeyType lookup_data = lookupGen(vmid);
    lookup_data.size = rangeSize();
 
    auto addr_match = te->match(lookup_data) && (!lastLevel || !te->partial);
    if (addr_match) {
        return ipaSpace == te->ipaSpace &&
            tgMap[rangeData.tg] == te->tg &&
            (resTLBIttl(rangeData.tg, rangeData.ttl) ||
                rangeData.ttl == te->lookupLevel);
    } else {
        return false;
    }
}
TLBIRIPA::matchEntry(TlbEntry* te, vmid_t vmid) const {…}
 
} // namespace ArmISA
} // namespace gem5