tlb.hh

Go to the documentation of this file.

/*
 * Copyright (c) 2010-2013, 2016, 2019-2022, 2024 Arm Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2001-2005 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __ARCH_ARM_TLB_HH__
#define __ARCH_ARM_TLB_HH__
 
 
#include "arch/arm/faults.hh"
#include "arch/arm/pagetable.hh"
#include "arch/arm/utility.hh"
#include "arch/generic/tlb.hh"
#include "base/cache/associative_cache.hh"
#include "base/statistics.hh"
#include "enums/TypeTLB.hh"
#include "mem/request.hh"
#include "params/ArmTLB.hh"
#include "sim/probe/pmu.hh"
 
namespace gem5
{
 
class ThreadContext;
 
namespace ArmISA {
 
class TableWalker;
class TLB;
class TLBIOp;
 
class TlbTestInterface
{
  public:
    TlbTestInterface() {}
    virtual ~TlbTestInterface() {}

    virtual Fault translationCheck(const RequestPtr &req, bool is_priv,
                                   BaseMMU::Mode mode,
                                   DomainType domain) = 0;

    virtual Fault walkCheck(const RequestPtr &walk_req,
                            Addr va, bool is_secure,
                            Addr is_priv, BaseMMU::Mode mode,
                            DomainType domain,
                            enums::ArmLookupLevel lookup_level) = 0;
};
 
class TLB : public BaseTLB
{
  protected:
    class Table : public AssociativeCache<TlbEntry>
    {
      public:
        using AssociativeCache<TlbEntry>::AssociativeCache;
        using AssociativeCache<TlbEntry>::accessEntry;
        TlbEntry* accessEntry(const KeyType &key) override;
        TlbEntry* findEntry(const KeyType &key) const override;

        void invalidatePrev(const TlbEntry *invalid=nullptr);
 
      private:
        mutable TlbEntry *prev = nullptr;
    } table;

    int size;

    bool isStage2;

    std::unordered_map<enums::ArmLookupLevel, bool> partialLevels;

    bool _walkCache;
 
    TableWalker *tableWalker;
 
    struct TlbStats : public statistics::Group
    {
        TlbStats(TLB &parent);
 
        const TLB &tlb;
 
        // Access Stats
        mutable statistics::Scalar partialHits;
        mutable statistics::Scalar instHits;
        mutable statistics::Scalar instMisses;
        mutable statistics::Scalar readHits;
        mutable statistics::Scalar readMisses;
        mutable statistics::Scalar writeHits;
        mutable statistics::Scalar writeMisses;
        mutable statistics::Scalar inserts;
        mutable statistics::Scalar flushTlb;
        mutable statistics::Scalar flushedEntries;
 
        statistics::Formula readAccesses;
        statistics::Formula writeAccesses;
        statistics::Formula instAccesses;
        statistics::Formula hits;
        statistics::Formula misses;
        statistics::Formula accesses;
    } stats;

    probing::PMUUPtr ppRefills;
 
    int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
    vmid_t vmid;

    std::set<Addr> observedPageSizes;
 
  public:
    using Params = ArmTLBParams;
    using Lookup = TlbEntry::KeyType;
    using LookupLevel = enums::ArmLookupLevel;
 
    TLB(const Params &p);
    TLB(const Params &p, int _size, TableWalker *_walker);

    TlbEntry *lookup(Lookup lookup_data);

    TlbEntry *multiLookup(const Lookup &lookup_data);
 
    virtual ~TLB();
 
    void takeOverFrom(BaseTLB *otlb) override;
 
    void setTableWalker(TableWalker *table_walker);
 
    TableWalker *getTableWalker() { return tableWalker; }
 
    int getsize() const { return size; }
 
    bool walkCache() const { return _walkCache; }
 
    void setVMID(vmid_t _vmid) { vmid = _vmid; }

    void insert(const Lookup &lookup_data, TlbEntry &pte);

    void multiInsert(const Lookup &lookup_data, TlbEntry &pte);

    void flushAll() override;
 

    void flush(const TLBIOp &tlbi_op);
 
    void printTlb() const;
 
    void demapPage(Addr vaddr, uint64_t asn) override
    {
        // needed for x86 only
        panic("demapPage() is not implemented.\n");
    }
 
    Fault
    translateAtomic(const RequestPtr &req, ThreadContext *tc,
                    BaseMMU::Mode mode) override
    {
        panic("unimplemented");
    }
 
    void
    translateTiming(const RequestPtr &req, ThreadContext *tc,
                    BaseMMU::Translation *translation,
                    BaseMMU::Mode mode) override
    {
        panic("unimplemented");
    }
 
    Fault
    finalizePhysical(const RequestPtr &req, ThreadContext *tc,
                     BaseMMU::Mode mode) const override
    {
        panic("unimplemented");
    }
 
    void regProbePoints() override;

    Port *getTableWalkerPort() override;
 
    // Caching misc register values here.
    // Writing to misc registers needs to invalidate them.
    // translateFunctional/translateSe/translateFs checks if they are
    // invalid and call updateMiscReg if necessary.
 
  private:
    void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
                   bool ignore_asn, ExceptionLevel target_el,
                   bool in_host, TypeTLB entry_type);

    void checkPromotion(TlbEntry *entry, BaseMMU::Mode mode);
};
 
} // namespace ArmISA
} // namespace gem5
 
#endif // __ARCH_ARM_TLB_HH__