52#include "debug/TLB.hh"
53#include "debug/TLBVerbose.hh"
54#include "params/ArmTLB.hh"
66 if (entry && !key.functional) {
77 if (
prev &&
prev->N == key.pageSize &&
prev->match(key)) {
82 auto entry =
static_cast<TlbEntry*
>(candidate);
86 if (entry->N == key.pageSize && entry->match(key)) {
97 if (!invalid || invalid ==
prev)
111 for (
int lvl = LookupLevel::L0;
112 lvl < LookupLevel::Num_ArmLookupLevel; lvl++) {
115 p.partial_levels.begin(),
116 p.partial_levels.end(),
121 if (it !=
p.partial_levels.end()) {
127 if (lvl != LookupLevel::Num_ArmLookupLevel - 1) {
135 table.setDebugFlag(::gem5::debug::TLB);
160 if (retval =
table.accessEntry(lookup_data); retval)
164 DPRINTF(TLBVerbose,
"Lookup %#x, asn %#x -> %s vmn 0x%x ss %s "
165 "ppn %#x size: %#x pa: %#x ap:%d piindex:%d "
166 "ns:%d ss:%s g:%d asid: %d "
167 "xs: %d regime: %s\n",
168 lookup_data.
va, lookup_data.
asn, retval ?
"hit" :
"miss",
169 lookup_data.
vmid, lookup_data.
ss,
170 retval ? retval->
pfn : 0, retval ? retval->
size : 0,
171 retval ? retval->
pAddr(lookup_data.
va) : 0,
172 retval ? retval->
ap : 0,
174 retval ? retval->
ns : 0,
176 retval ? retval->
global : 0, retval ? retval->
asid : 0,
177 retval ? retval->
xs : 0,
217 te =
tlb->multiLookup(lookup_data);
235 TypeTLB::instruction : TypeTLB::data;
240 if (!(entry->
type & acc_type))
241 entry->
type = TypeTLB::unified;
252 table.insertEntry(lookup_data, victim);
254 table.invalidatePrev(victim);
276 next_level->multiInsert(
lookup, entry);
298 stats.flushedEntries++;
302 table.invalidatePrev();
311 bool valid_entry =
false;
319 stats.flushedEntries++;
321 valid_entry = valid_entry ||
te.valid;
337 "partial translation hits"),
345 "Number of times an entry is inserted into the TLB"),
347 "Number of times a TLB invalidation was requested"),
349 "Number of entries that have been flushed from TLB"),
357 "Total TLB (inst and data) hits",
360 "Total TLB (inst and data) misses",
363 "Total TLB (inst and data) accesses",
369 if (
tlb.type() == TypeTLB::data) {
370 instHits.flags(statistics::nozero);
371 instMisses.flags(statistics::nozero);
373 instAccesses.flags(statistics::nozero);
379 if (
tlb.type() & TypeTLB::instruction) {
380 readHits.flags(statistics::nozero);
381 readMisses.flags(statistics::nozero);
382 writeHits.flags(statistics::nozero);
383 writeMisses.flags(statistics::nozero);
385 readAccesses.flags(statistics::nozero);
386 writeAccesses.flags(statistics::nozero);
bool match(TlbEntry *entry, vmid_t curr_vmid) const
TlbEntry * findEntry(const KeyType &key) const override
TlbEntry * accessEntry(const KeyType &key) override
TlbEntry * prev
Last matched entry.
void invalidatePrev(const TlbEntry *invalid=nullptr)
Invalidate the last matched entry The method has an optional param, which means: invalidate cached pr...
void takeOverFrom(BaseTLB *otlb) override
Take over from an old tlb context.
TableWalker * tableWalker
std::set< Addr > observedPageSizes
Set of observed page sizes in the TLB We update the set conservatively, therefore allowing false posi...
void setTableWalker(TableWalker *table_walker)
TlbEntry * multiLookup(const Lookup &lookup_data)
Lookup an entry in the TLB and in the next levels by following the nextLevel pointer.
void flush(const TLBIOp &tlbi_op)
Flush TLB entries.
void regProbePoints() override
Register probe points for this object.
probing::PMUUPtr ppDataRefills
Port * getTableWalkerPort() override
Get the table walker port.
bool _walkCache
True if the TLB caches partial translations.
gem5::ArmISA::TLB::Table table
std::unordered_map< enums::ArmLookupLevel, bool > partialLevels
Hash map containing one entry per lookup level The TLB is caching partial translations from the key l...
probing::PMUUPtr ppInstRefills
PMU probe for TLB refills.
void insert(const Lookup &lookup_data, TlbEntry &pte)
Insert a PTE in the current TLB.
void checkPromotion(TlbEntry *entry, BaseMMU::Mode mode)
Check if the tlb entry passed as an argument needs to be "promoted" as a unified entry: this should h...
gem5::ArmISA::TLB::TlbStats stats
TlbEntry * lookup(Lookup lookup_data)
Lookup an entry in the TLB.
enums::ArmLookupLevel LookupLevel
bool isStage2
Indicates this TLB caches IPA->PA translations.
void flushAll() override
Reset the entire TLB.
void multiInsert(const Lookup &lookup_data, TlbEntry &pte)
Insert a PTE in the current TLB and in the higher levels.
IndexingPolicy * indexingPolicy
TlbEntry::KeyType KeyType
BaseTLB(const BaseTLBParams &p)
BaseTLB * nextLevel() const
virtual std::string name() const
Ports are used to interface objects to each other.
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
ProbeManager * getProbeManager()
Get the probe manager for this object.
static const char * regimeToStr(TranslationRegime regime)
ProbePointArg< uint64_t > PMU
PMU probe point.
const FlagsType nozero
Don't print if this is zero.
Copyright (c) 2024 Arm Limited All rights reserved.
statistics::Formula writeAccesses
statistics::Scalar readHits
statistics::Scalar instHits
statistics::Scalar flushedEntries
statistics::Formula misses
statistics::Formula readAccesses
statistics::Formula accesses
statistics::Scalar inserts
statistics::Scalar flushTlb
statistics::Scalar readMisses
statistics::Scalar writeHits
statistics::Scalar writeMisses
statistics::Formula instAccesses
statistics::Scalar instMisses
statistics::Scalar partialHits
Addr pAddr(Addr va) const
The file contains the definition of a set of TLB Invalidate Instructions.