43#include "debug/HWPrefetch.hh"
45#include "params/FetchDirectedPrefetcher.hh"
54 const FetchDirectedPrefetcherParams &
p)
64 stats(this,
p.pfq_size,
p.tq_size)
73 for (
Addr blk_addr = start_blk_addr; blk_addr <= end_blk_addr;
77 auto it = std::find(
pfq.begin(),
pfq.end(), blk_addr);
78 if (it !=
pfq.end()) {
79 DPRINTF(HWPrefetch,
"%#x already in prefetch_queue\n", blk_addr);
86 DPRINTF(HWPrefetch,
"%#x already in translation queue\n",
95 DPRINTF(HWPrefetch,
"Translation queue full, dropping %#x\n",
102 translationq.emplace_back(*
this, blk_addr, ft->getTid(), ft->ftNum());
103 DPRINTF(HWPrefetch,
"Start translation for %#x, reqID=%i, ctxID=%i\n",
109 stats.pfqSizeDistAtNotify.sample(
pfq.size());
127 if (
pr.ftn == ft->ftNum()) {
135 auto it =
pfq.begin();
136 while (it !=
pfq.end()) {
137 if (it->ftn == ft->ftNum()) {
158 "Cache is not set. Cache snooping will not work!\n");
161 DPRINTF(HWPrefetch,
"Translation of %#x failed\n", it->addr);
162 stats.translationFail++;
164 DPRINTF(HWPrefetch,
"Translation of %#x succeeded\n", it->addr);
165 stats.translationSuccess++;
167 if (it->isCanceled()) {
169 "Drop Packet. Canceled by notifyFTQRemove during "
171 }
else if (it->req->isUncacheable()) {
172 DPRINTF(HWPrefetch,
"Drop uncacheable requests.\n");
174 (
cache->inCache(it->req->getPaddr(), it->req->isSecure()) ||
175 (
cache->inMissQueue(it->req->getPaddr(),
176 it->req->isSecure())))) {
178 DPRINTF(HWPrefetch,
"Drop Packet. In Cache / MSHR\n");
183 stats.pfPacketsCreated++;
185 "Addr:%#x Add packet to PFQ. pkt PA:%#x, "
187 it->addr, it->pkt->getAddr(),
pfq.size());
189 stats.pfCandidatesAdded++;
193 DPRINTF(HWPrefetch,
"Prefetch queue full, dropping %#x\n",
206 if (
pfq.size() == 0) {
211 DPRINTF(HWPrefetch,
"Issue Prefetch to: pkt:%#x, PC:%#x, PFQ size:%i\n",
234 owner.cpu->getContext(tid)->contextId());
235 if (
owner.markReqAsPrefetch) {
252 assert(
owner.mmu !=
nullptr);
253 auto tc =
owner.system->threads[
req->contextId()];
263 bool failed = (fault !=
NoFault);
264 owner.translationComplete(
this, failed);
272 if (
cpu ==
nullptr) {
273 warn(
"FetchDirectedPrefetcher: No CPU to listen from registered\n");
277 listeners.push_back(
cpu->getProbeManager()->connect<FetchTargetListener>(
281 listeners.push_back(
cpu->getProbeManager()->connect<FetchTargetListener>(
290 "Number of notifications from an insertion in the FTQ"),
292 "Number of prefetches identified."),
294 "Number of prefetches squashed."),
296 "Number of prefetches hit in the prefetch queue"),
298 "Number of prefetches hit in the translation queue"),
300 "Number of prefetches hit in in cache"),
302 "Number of prefetches hit in cache but prefetched"),
304 "Number of prefetch packets created"),
306 "Number of prefetch candidates added to the prefetch queue"),
308 "Number of prefetches that failed translation"),
310 "Number of prefetches that succeeded translation"),
312 "Distribution of the prefetch queue size at the time of "
313 "notification of a new fetch target"),
315 "Distribution of the translation queue size at the time of "
316 "notification of a new fetch target"),
318 "Number of insertions into the prefetch candidate queue"),
320 "Number of uses into the prefetch candidate queue"),
322 "Number of drops into the prefetch candidate queue"),
324 "Number of insertions into the prefetch translation queue"),
326 "Number of uses into the prefetch translation queue"),
328 "Number of drops into the prefetch translation queue")
Tick cyclesToTicks(Cycles c) const
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
ProbeListenerArgFunc generates a listener for the class of Arg and a lambda callback function that is...
@ INST_FETCH
The request was an instruction fetch.
@ PREFETCH
The request is a prefetch.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Base(const BasePrefetcherParams &p)
unsigned blkSize
The block size of the parent cache.
void regProbeListeners() override
Register probe points for this object.
gem5::prefetch::Base::StatGroup prefetchStats
Addr blockAddress(Addr a) const
Determine the address of the block in which a lays.
std::list< PrefetchRequest > pfq
The prefetch queue.
void translationComplete(PrefetchRequest *pf_req, const bool failed)
A translation has completed and can now be added to the PFQ.
const unsigned int tqSize
Translation queue size: Maximum number of outstanding translations.
const bool markReqAsPrefetch
Mark memory requests as prefetches.
gem5::prefetch::FetchDirectedPrefetcher::Stats stats
const bool cacheSnoop
Probe the cache before a prefetch gets inserted into the PFQ.
void notifyFTQRemove(const o3::FetchTargetPtr &ft)
Notifies the prefetcher that a fetch target was removed from the FTQ.
BaseCPU * cpu
Pointer to the CPU object that contains the FTQ.
std::list< PrefetchRequest > translationq
const unsigned int pfqSize
Prefetch queue size: Maximum number of queued prefetches.
const bool squashPrefetches
Squash prefetches in case its fetch target is removed from the FTQ.
const unsigned int latency
The latency of the prefetcher.
void regProbeListeners() override
Base class overrides.
BaseCache * cache
Pointer to the cache it is attached to.
FetchDirectedPrefetcher(const FetchDirectedPrefetcherParams &p)
std::vector< ProbeListenerPtr<> > listeners
Array of probe listeners.
PacketPtr getPacket() override
Gets a packet from the prefetch queue to be prefetched.
void notifyFTQInsert(const o3::FetchTargetPtr &ft)
Notifies the prefetcher that a new fetch target was inserted into the FTQ.
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
#define warn_if_once(cond,...)
Declares a basic cache interface BaseCache.
std::shared_ptr< FetchTarget > FetchTargetPtr
Copyright (c) 2024 Arm Limited All rights reserved.
std::shared_ptr< FaultBase > Fault
int16_t ThreadID
Thread index/ID type.
std::shared_ptr< Request > RequestPtr
Tick curTick()
The universal simulation clock.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
constexpr decltype(nullptr) NoFault
The prefetch queue entry objects.
PrefetchRequest(FetchDirectedPrefetcher &_owner, uint64_t _addr, ThreadID tid, o3::FTSeqNum ftn)
Tick readyTime
The time when the prefetch is ready to be sent to the cache.
bool canceled
Marks a Prefetch Request as canceled if notifyFTQRemove was called during translation.
void startTranslation()
Issues the translation request.
const uint64_t addr
The virtual address.
RequestPtr req
The request and packet that will be sent to the cache.
const o3::FTSeqNum ftn
The fetch target number that created this request.
FetchDirectedPrefetcher & owner
Owner of the packet.
void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
void createPkt()
Creates the packet that is send to the memory.
statistics::Scalar pfInCachePrefetched
statistics::Scalar pfInPFQ
statistics::Scalar pfPacketsCreated
statistics::Scalar pfqDrops
Stats(statistics::Group *parent, int pfq_size, int tq_size)
statistics::Distribution pfqSizeDistAtNotify
statistics::Scalar tqDrops
statistics::Scalar pfSquashed
statistics::Scalar translationSuccess
statistics::Scalar pfIdentified
statistics::Scalar pfqInserts
statistics::Distribution tqSizeDistAtNotify
statistics::Scalar tqPops
statistics::Scalar pfInTQ
statistics::Scalar tqInserts
statistics::Scalar pfInCache
statistics::Scalar pfCandidatesAdded
statistics::Scalar pfqPops
statistics::Scalar translationFail
statistics::Scalar fdipInsertions