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bs.cc
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28 
29 #include "arch/riscv/insts/bs.hh"
30 
31 #include <sstream>
32 #include <string>
33 
34 #include "arch/riscv/utility.hh"
35 
36 namespace gem5
37 {
38 
39 namespace RiscvISA
40 {
41 
42 std::string
43 BSOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
44 {
45  std::stringstream ss;
46  ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
47  registerName(srcRegIdx(0)) << ", " << registerName(srcRegIdx(1)) <<
48  ", " << (uint32_t)bs;
49  return ss.str();
50 }
51 
52 } // namespace RiscvISA
53 } // namespace gem5
gem5::RiscvISA::BSOp::bs
uint8_t bs
Definition: bs.hh:43
gem5::loader::SymbolTable
Definition: symtab.hh:64
bs.hh
gem5::StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:215
gem5::RiscvISA::registerName
std::string registerName(RegId reg)
Definition: utility.hh:108
gem5::RiscvISA::ss
Bitfield< 11, 8 > ss
Definition: pra_constants.hh:257
gem5::StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:225
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::RiscvISA::BSOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: bs.cc:43
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
utility.hh
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:259
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
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