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bs.hh
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28 
29 #ifndef __ARCH_RISCV_BS_INST_HH__
30 #define __ARCH_RISCV_BS_INST_HH__
31 
33 
34 namespace gem5
35 {
36 
37 namespace RiscvISA
38 {
39 
40 class BSOp : public RiscvStaticInst
41 {
42  protected:
43  uint8_t bs;
44 
45  BSOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
46  : RiscvStaticInst(mnem, _machInst, __opClass), bs(0)
47  {}
48 
49  std::string generateDisassembly(
50  Addr pc, const loader::SymbolTable *symtab) const override;
51 };
52 
53 } // namespace RiscvISA
54 } // namespace gem5
55 
56 #endif // __ARCH_RISCV_BS_INST_HH__
gem5::RiscvISA::BSOp::bs
uint8_t bs
Definition: bs.hh:43
gem5::RiscvISA::RiscvStaticInst
Base class for all RISC-V static instructions.
Definition: static_inst.hh:51
gem5::loader::SymbolTable
Definition: symtab.hh:64
gem5::RiscvISA::BSOp::BSOp
BSOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: bs.hh:45
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::RiscvISA::BSOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: bs.cc:43
static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::ExtMachInst
Definition: types.hh:212
gem5::RiscvISA::BSOp
Definition: bs.hh:40
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37

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