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cortex_a76.cc
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27 
28 #include "arch/arm/fastmodel/CortexA76/cortex_a76.hh"
29 
30 #include "arch/arm/fastmodel/iris/cpu.hh"
31 #include "arch/arm/regs/misc.hh"
32 #include "base/logging.hh"
33 #include "dev/arm/base_gic.hh"
34 #include "systemc/tlm_bridge/gem5_to_tlm.hh"
35 
36 namespace gem5
37 {
38 
39 namespace fastmodel
40 {
41 
42 void
43 CortexA76::initState()
44 {
45  for (auto *tc : threadContexts)
46  tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0, params().cntfrq);
47 
48  evs_base_cpu->setSysCounterFrq(params().cntfrq);
49 }
50 
51 void
52 CortexA76::setCluster(CortexA76Cluster *_cluster, int _num)
53 {
54  cluster = _cluster;
55  num = _num;
56 
57  set_evs_param("CFGEND", params().CFGEND);
58  set_evs_param("CFGTE", params().CFGTE);
59  set_evs_param("CRYPTODISABLE", params().CRYPTODISABLE);
60  set_evs_param("RVBARADDR", params().RVBARADDR);
61  set_evs_param("VINITHI", params().VINITHI);
62  set_evs_param("enable_trace_special_hlt_imm16",
63  params().enable_trace_special_hlt_imm16);
64  set_evs_param("l2cache-hit_latency", params().l2cache_hit_latency);
65  set_evs_param("l2cache-maintenance_latency",
66  params().l2cache_maintenance_latency);
67  set_evs_param("l2cache-miss_latency", params().l2cache_miss_latency);
68  set_evs_param("l2cache-read_access_latency",
69  params().l2cache_read_access_latency);
70  set_evs_param("l2cache-read_latency", params().l2cache_read_latency);
71  set_evs_param("l2cache-size", params().l2cache_size);
72  set_evs_param("l2cache-snoop_data_transfer_latency",
73  params().l2cache_snoop_data_transfer_latency);
74  set_evs_param("l2cache-snoop_issue_latency",
75  params().l2cache_snoop_issue_latency);
76  set_evs_param("l2cache-write_access_latency",
77  params().l2cache_write_access_latency);
78  set_evs_param("l2cache-write_latency", params().l2cache_write_latency);
79  set_evs_param("max_code_cache_mb", params().max_code_cache_mb);
80  set_evs_param("min_sync_level", params().min_sync_level);
81  set_evs_param("semihosting-A32_HLT", params().semihosting_A32_HLT);
82  set_evs_param("semihosting-A64_HLT", params().semihosting_A64_HLT);
83  set_evs_param("semihosting-ARM_SVC", params().semihosting_ARM_SVC);
84  set_evs_param("semihosting-T32_HLT", params().semihosting_T32_HLT);
85  set_evs_param("semihosting-Thumb_SVC", params().semihosting_Thumb_SVC);
86  set_evs_param("semihosting-cmd_line", params().semihosting_cmd_line);
87  set_evs_param("semihosting-cwd", params().semihosting_cwd);
88  set_evs_param("semihosting-enable", params().semihosting_enable);
89  set_evs_param("semihosting-heap_base", params().semihosting_heap_base);
90  set_evs_param("semihosting-heap_limit", params().semihosting_heap_limit);
91  set_evs_param("semihosting-stack_base", params().semihosting_stack_base);
92  set_evs_param("semihosting-stack_limit", params().semihosting_stack_limit);
93  set_evs_param("trace_special_hlt_imm16", params().trace_special_hlt_imm16);
94  set_evs_param("vfp-enable_at_reset", params().vfp_enable_at_reset);
95 }
96 
97 void
98 CortexA76::setResetAddr(Addr addr, bool secure)
99 {
100  evs_base_cpu->setResetAddr(num, addr, secure);
101 }
102 
103 Port &
104 CortexA76::getPort(const std::string &if_name, PortID idx)
105 {
106  if (if_name == "redistributor" || if_name == "core_reset" ||
107  if_name == "poweron_reset")
108  return cluster->getEvs()->gem5_getPort(if_name, num);
109  else
110  return Base::getPort(if_name, idx);
111 }
112 
113 CortexA76Cluster::CortexA76Cluster(const Params &p) :
114  SimObject(p), cores(p.cores), evs(p.evs)
115 {
116  for (int i = 0; i < p.cores.size(); i++)
117  p.cores[i]->setCluster(this, i);
118 
119  Iris::BaseCpuEvs *e = dynamic_cast<Iris::BaseCpuEvs *>(evs);
120  panic_if(!e, "EVS should be of type Iris::BaseCpuEvs");
121  e->setCluster(this);
122 
123  set_evs_param("core.BROADCASTATOMIC", p.BROADCASTATOMIC);
124  set_evs_param("core.BROADCASTCACHEMAINT", p.BROADCASTCACHEMAINT);
125  set_evs_param("core.BROADCASTOUTER", p.BROADCASTOUTER);
126  set_evs_param("core.BROADCASTPERSIST", p.BROADCASTPERSIST);
127  set_evs_param("core.CLUSTER_ID", p.CLUSTER_ID);
128  set_evs_param("core.GICDISABLE", p.GICDISABLE);
129  set_evs_param("core.cpi_div", p.cpi_div);
130  set_evs_param("core.cpi_mul", p.cpi_mul);
131  set_evs_param("core.dcache-hit_latency", p.dcache_hit_latency);
132  set_evs_param("core.dcache-maintenance_latency",
133  p.dcache_maintenance_latency);
134  set_evs_param("core.dcache-miss_latency", p.dcache_miss_latency);
135  set_evs_param("core.dcache-prefetch_enabled",
136  p.dcache_prefetch_enabled);
137  set_evs_param("core.dcache-read_access_latency",
138  p.dcache_read_access_latency);
139  set_evs_param("core.dcache-read_latency", p.dcache_read_latency);
140  set_evs_param("core.dcache-snoop_data_transfer_latency",
141  p.dcache_snoop_data_transfer_latency);
142  set_evs_param("core.dcache-state_modelled", p.dcache_state_modelled);
143  set_evs_param("core.dcache-write_access_latency",
144  p.dcache_write_access_latency);
145  set_evs_param("core.dcache-write_latency", p.dcache_write_latency);
146  set_evs_param("core.default_opmode", p.default_opmode);
147  set_evs_param("core.diagnostics", p.diagnostics);
148  set_evs_param("core.enable_simulation_performance_optimizations",
149  p.enable_simulation_performance_optimizations);
150  set_evs_param("core.ext_abort_device_read_is_sync",
151  p.ext_abort_device_read_is_sync);
152  set_evs_param("core.ext_abort_device_write_is_sync",
153  p.ext_abort_device_write_is_sync);
154  set_evs_param("core.ext_abort_so_read_is_sync",
155  p.ext_abort_so_read_is_sync);
156  set_evs_param("core.ext_abort_so_write_is_sync",
157  p.ext_abort_so_write_is_sync);
158  set_evs_param("core.gicv3.cpuintf-mmap-access-level",
159  p.gicv3_cpuintf_mmap_access_level);
160  set_evs_param("core.has_peripheral_port", p.has_peripheral_port);
161  set_evs_param("core.has_statistical_profiling",
162  p.has_statistical_profiling);
163  set_evs_param("core.icache-hit_latency", p.icache_hit_latency);
164  set_evs_param("core.icache-maintenance_latency",
165  p.icache_maintenance_latency);
166  set_evs_param("core.icache-miss_latency", p.icache_miss_latency);
167  set_evs_param("core.icache-prefetch_enabled",
168  p.icache_prefetch_enabled);
169  set_evs_param("core.icache-read_access_latency",
170  p.icache_read_access_latency);
171  set_evs_param("core.icache-read_latency", p.icache_read_latency);
172  set_evs_param("core.icache-state_modelled", p.icache_state_modelled);
173  set_evs_param("core.l3cache-hit_latency", p.l3cache_hit_latency);
174  set_evs_param("core.l3cache-maintenance_latency",
175  p.l3cache_maintenance_latency);
176  set_evs_param("core.l3cache-miss_latency", p.l3cache_miss_latency);
177  set_evs_param("core.l3cache-read_access_latency",
178  p.l3cache_read_access_latency);
179  set_evs_param("core.l3cache-read_latency", p.l3cache_read_latency);
180  set_evs_param("core.l3cache-size", p.l3cache_size);
181  set_evs_param("core.l3cache-snoop_data_transfer_latency",
182  p.l3cache_snoop_data_transfer_latency);
183  set_evs_param("core.l3cache-snoop_issue_latency",
184  p.l3cache_snoop_issue_latency);
185  set_evs_param("core.l3cache-write_access_latency",
186  p.l3cache_write_access_latency);
187  set_evs_param("core.l3cache-write_latency", p.l3cache_write_latency);
188  set_evs_param("core.pchannel_treat_simreset_as_poreset",
189  p.pchannel_treat_simreset_as_poreset);
190  set_evs_param("core.periph_address_end", p.periph_address_end);
191  set_evs_param("core.periph_address_start", p.periph_address_start);
192  set_evs_param("core.ptw_latency", p.ptw_latency);
193  set_evs_param("core.tlb_latency", p.tlb_latency);
194  set_evs_param("core.treat-dcache-cmos-to-pou-as-nop",
195  p.treat_dcache_cmos_to_pou_as_nop);
196  set_evs_param("core.walk_cache_latency", p.walk_cache_latency);
197 }
198 
199 Port &
200 CortexA76Cluster::getPort(const std::string &if_name, PortID idx)
201 {
202  if (if_name == "amba" || if_name == "top_reset" ||
203  if_name == "dbg_reset" || if_name == "model_reset") {
204  return evs->gem5_getPort(if_name, idx);
205  } else {
206  return SimObject::getPort(if_name, idx);
207  }
208 }
209 
210 } // namespace fastmodel
211 } // namespace gem5
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:245
gem5::SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:123
cortex_a76.hh
gem5::Iris::BaseCpuEvs::setResetAddr
virtual void setResetAddr(int core, Addr addr, bool secure)=0
gem5_to_tlm.hh
base_gic.hh
gem5::fastmodel::CortexA76Cluster::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: cortex_a76.cc:200
gem5::Iris::BaseCpuEvs
Definition: cpu.hh:47
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:65
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::fastmodel::CortexA76::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: cortex_a76.cc:43
cpu.hh
gem5::fastmodel::CortexA76Cluster::evs
sc_core::sc_module * evs
Definition: cortex_a76.hh:86
gem5::Iris::BaseCPU::evs_base_cpu
Iris::BaseCpuEvs * evs_base_cpu
Definition: cpu.hh:98
gem5::Iris::BaseCpuEvs::setSysCounterFrq
virtual void setSysCounterFrq(uint64_t sys_counter_frq)=0
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::fastmodel::CortexA76::num
int num
Definition: cortex_a76.hh:61
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::fastmodel::CortexA76::setCluster
void setCluster(CortexA76Cluster *_cluster, int _num)
Definition: cortex_a76.cc:52
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::fastmodel::CortexA76Cluster::getEvs
sc_core::sc_module * getEvs() const
Definition: cortex_a76.hh:98
gem5::fastmodel::CortexA76::cluster
CortexA76Cluster * cluster
Definition: cortex_a76.hh:60
gem5::fastmodel::CortexA76::setResetAddr
void setResetAddr(Addr addr, bool secure=false) override
Definition: cortex_a76.cc:98
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::fastmodel::CortexA76Cluster::CortexA76Cluster
CortexA76Cluster(const Params &p)
Definition: cortex_a76.cc:113
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:214
gem5::BaseCPU::threadContexts
std::vector< ThreadContext * > threadContexts
Definition: base.hh:260
gem5::fastmodel::CortexA76::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: cortex_a76.cc:104
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::BaseCPU::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port on this CPU.
Definition: base.cc:455
misc.hh
sc_core::sc_module::gem5_getPort
virtual gem5::Port & gem5_getPort(const std::string &if_name, int idx=-1)
Definition: sc_module.cc:117
gem5::fastmodel::CortexA76::set_evs_param
void set_evs_param(const std::string &n, T val)
Definition: cortex_a76.hh:108
logging.hh
gem5::fastmodel::CortexA76Cluster
Definition: cortex_a76.hh:82
gem5::ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: misc.hh:775
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::fastmodel::CortexA76Cluster::set_evs_param
void set_evs_param(const std::string &n, T val)
Definition: cortex_a76.hh:92
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