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queued.cc
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37 
39 
40 #include <cassert>
41 
42 #include "arch/generic/tlb.hh"
43 #include "base/logging.hh"
44 #include "base/trace.hh"
45 #include "debug/HWPrefetch.hh"
46 #include "debug/HWPrefetchQueue.hh"
47 #include "mem/cache/base.hh"
48 #include "mem/request.hh"
49 #include "params/QueuedPrefetcher.hh"
50 
51 namespace gem5
52 {
53 
54 namespace prefetch
55 {
56 
57 void
58 Queued::DeferredPacket::createPkt(Addr paddr, unsigned blk_size,
59  RequestorID requestor_id,
60  bool tag_prefetch,
61  Tick t) {
62  /* Create a prefetch memory request */
63  RequestPtr req = std::make_shared<Request>(paddr, blk_size,
64  0, requestor_id);
65 
66  if (pfInfo.isSecure()) {
67  req->setFlags(Request::SECURE);
68  }
70  pkt = new Packet(req, MemCmd::HardPFReq);
71  pkt->allocate();
72  if (tag_prefetch && pfInfo.hasPC()) {
73  // Tag prefetch packet with accessing pc
74  pkt->req->setPC(pfInfo.getPC());
75  }
76  tick = t;
77 }
78 
79 void
81 {
82  assert(translationRequest != nullptr);
83  if (!ongoingTranslation) {
84  ongoingTranslation = true;
85  // Prefetchers only operate in Timing mode
86  mmu->translateTiming(translationRequest, tc, this, BaseMMU::Read);
87  }
88 }
89 
90 void
92  const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)
93 {
94  assert(ongoingTranslation);
95  ongoingTranslation = false;
96  bool failed = (fault != NoFault);
97  owner->translationComplete(this, failed);
98 }
99 
100 Queued::Queued(const QueuedPrefetcherParams &p)
101  : Base(p), queueSize(p.queue_size),
103  p.max_prefetch_requests_with_pending_translation),
104  latency(p.latency), queueSquash(p.queue_squash),
105  queueFilter(p.queue_filter), cacheSnoop(p.cache_snoop),
106  tagPrefetch(p.tag_prefetch),
107  throttleControlPct(p.throttle_control_percentage), statsQueued(this)
108 {
109 }
110 
112 {
113  // Delete the queued prefetch packets
114  for (DeferredPacket &p : pfq) {
115  delete p.pkt;
116  }
117 }
118 
119 void
121 {
122  int pos = 0;
123  std::string queue_name = "";
124  if (&queue == &pfq) {
125  queue_name = "PFQ";
126  } else {
127  assert(&queue == &pfqMissingTranslation);
128  queue_name = "PFTransQ";
129  }
130 
131  for (const_iterator it = queue.cbegin(); it != queue.cend();
132  it++, pos++) {
133  Addr vaddr = it->pfInfo.getAddr();
134  /* Set paddr to 0 if not yet translated */
135  Addr paddr = it->pkt ? it->pkt->getAddr() : 0;
136  DPRINTF(HWPrefetchQueue, "%s[%d]: Prefetch Req VA: %#x PA: %#x "
137  "prio: %3d\n", queue_name, pos, vaddr, paddr, it->priority);
138  }
139 }
140 
141 size_t
143 {
160  size_t max_pfs = total;
161  if (total > 0 && issuedPrefetches > 0) {
162  size_t throttle_pfs = (total * throttleControlPct) / 100;
163  size_t min_pfs = (total - throttle_pfs) == 0 ?
164  1 : (total - throttle_pfs);
165  max_pfs = min_pfs + (total - min_pfs) *
167  }
168  return max_pfs;
169 }
170 
171 void
172 Queued::notify(const PacketPtr &pkt, const PrefetchInfo &pfi)
173 {
174  Addr blk_addr = blockAddress(pfi.getAddr());
175  bool is_secure = pfi.isSecure();
176 
177  // Squash queued prefetches if demand miss to same line
178  if (queueSquash) {
179  auto itr = pfq.begin();
180  while (itr != pfq.end()) {
181  if (itr->pfInfo.getAddr() == blk_addr &&
182  itr->pfInfo.isSecure() == is_secure) {
183  DPRINTF(HWPrefetch, "Removing pf candidate addr: %#x "
184  "(cl: %#x), demand request going to the same addr\n",
185  itr->pfInfo.getAddr(),
186  blockAddress(itr->pfInfo.getAddr()));
187  delete itr->pkt;
188  itr = pfq.erase(itr);
190  } else {
191  ++itr;
192  }
193  }
194  }
195 
196  // Calculate prefetches given this access
197  std::vector<AddrPriority> addresses;
198  calculatePrefetch(pfi, addresses);
199 
200  // Get the maximu number of prefetches that we are allowed to generate
201  size_t max_pfs = getMaxPermittedPrefetches(addresses.size());
202 
203  // Queue up generated prefetches
204  size_t num_pfs = 0;
205  for (AddrPriority& addr_prio : addresses) {
206 
207  // Block align prefetch address
208  addr_prio.first = blockAddress(addr_prio.first);
209 
210  if (!samePage(addr_prio.first, pfi.getAddr())) {
211  statsQueued.pfSpanPage += 1;
212 
213  if (hasBeenPrefetched(pkt->getAddr(), pkt->isSecure())) {
215  }
216  }
217 
218  bool can_cross_page = (mmu != nullptr);
219  if (can_cross_page || samePage(addr_prio.first, pfi.getAddr())) {
220  PrefetchInfo new_pfi(pfi,addr_prio.first);
222  DPRINTF(HWPrefetch, "Found a pf candidate addr: %#x, "
223  "inserting into prefetch queue.\n", new_pfi.getAddr());
224  // Create and insert the request
225  insert(pkt, new_pfi, addr_prio.second);
226  num_pfs += 1;
227  if (num_pfs == max_pfs) {
228  break;
229  }
230  } else {
231  DPRINTF(HWPrefetch, "Ignoring page crossing prefetch.\n");
232  }
233  }
234 }
235 
236 PacketPtr
238 {
239  DPRINTF(HWPrefetch, "Requesting a prefetch to issue.\n");
240 
241  if (pfq.empty()) {
242  // If the queue is empty, attempt first to fill it with requests
243  // from the queue of missing translations
245  }
246 
247  if (pfq.empty()) {
248  DPRINTF(HWPrefetch, "No hardware prefetches available.\n");
249  return nullptr;
250  }
251 
252  PacketPtr pkt = pfq.front().pkt;
253  pfq.pop_front();
254 
256  issuedPrefetches += 1;
257  assert(pkt != nullptr);
258  DPRINTF(HWPrefetch, "Generating prefetch for %#x.\n", pkt->getAddr());
259 
261  return pkt;
262 }
263 
265  : statistics::Group(parent),
266  ADD_STAT(pfIdentified, statistics::units::Count::get(),
267  "number of prefetch candidates identified"),
268  ADD_STAT(pfBufferHit, statistics::units::Count::get(),
269  "number of redundant prefetches already in prefetch queue"),
270  ADD_STAT(pfInCache, statistics::units::Count::get(),
271  "number of redundant prefetches already in cache/mshr dropped"),
272  ADD_STAT(pfRemovedDemand, statistics::units::Count::get(),
273  "number of prefetches dropped due to a demand for the same "
274  "address"),
275  ADD_STAT(pfRemovedFull, statistics::units::Count::get(),
276  "number of prefetches dropped due to prefetch queue size"),
277  ADD_STAT(pfSpanPage, statistics::units::Count::get(),
278  "number of prefetches that crossed the page"),
279  ADD_STAT(pfUsefulSpanPage, statistics::units::Count::get(),
280  "number of prefetches that is useful and crossed the page")
281 {
282 }
283 
284 
285 void
287 {
288  unsigned count = 0;
289  iterator it = pfqMissingTranslation.begin();
290  while (it != pfqMissingTranslation.end() && count < max) {
291  DeferredPacket &dp = *it;
292  // Increase the iterator first because dp.startTranslation can end up
293  // calling finishTranslation, which will erase "it"
294  it++;
295  dp.startTranslation(mmu);
296  count += 1;
297  }
298 }
299 
300 void
302 {
303  auto it = pfqMissingTranslation.begin();
304  while (it != pfqMissingTranslation.end()) {
305  if (&(*it) == dp) {
306  break;
307  }
308  it++;
309  }
310  assert(it != pfqMissingTranslation.end());
311  if (!failed) {
312  DPRINTF(HWPrefetch, "%s Translation of vaddr %#x succeeded: "
313  "paddr %#x \n", mmu->name(),
314  it->translationRequest->getVaddr(),
315  it->translationRequest->getPaddr());
316  Addr target_paddr = it->translationRequest->getPaddr();
317  // check if this prefetch is already redundant
318  if (cacheSnoop && (inCache(target_paddr, it->pfInfo.isSecure()) ||
319  inMissQueue(target_paddr, it->pfInfo.isSecure()))) {
321  DPRINTF(HWPrefetch, "Dropping redundant in "
322  "cache/MSHR prefetch addr:%#x\n", target_paddr);
323  } else {
324  Tick pf_time = curTick() + clockPeriod() * latency;
325  it->createPkt(target_paddr, blkSize, requestorId, tagPrefetch,
326  pf_time);
327  addToQueue(pfq, *it);
328  }
329  } else {
330  DPRINTF(HWPrefetch, "%s Translation of vaddr %#x failed, dropping "
331  "prefetch request %#x \n", mmu->name(),
332  it->translationRequest->getVaddr());
333  }
334  pfqMissingTranslation.erase(it);
335 }
336 
337 bool
339  const PrefetchInfo &pfi, int32_t priority)
340 {
341  bool found = false;
342  iterator it;
343  for (it = queue.begin(); it != queue.end() && !found; it++) {
344  found = it->pfInfo.sameAddr(pfi);
345  }
346 
347  /* If the address is already in the queue, update priority and leave */
348  if (it != queue.end()) {
350  if (it->priority < priority) {
351  /* Update priority value and position in the queue */
352  it->priority = priority;
353  iterator prev = it;
354  while (prev != queue.begin()) {
355  prev--;
356  /* If the packet has higher priority, swap */
357  if (*it > *prev) {
358  std::swap(*it, *prev);
359  it = prev;
360  }
361  }
362  DPRINTF(HWPrefetch, "Prefetch addr already in "
363  "prefetch queue, priority updated\n");
364  } else {
365  DPRINTF(HWPrefetch, "Prefetch addr already in "
366  "prefetch queue\n");
367  }
368  }
369  return found;
370 }
371 
374  PacketPtr pkt)
375 {
376  RequestPtr translation_req = std::make_shared<Request>(
377  addr, blkSize, pkt->req->getFlags(), requestorId, pfi.getPC(),
378  pkt->req->contextId());
379  translation_req->setFlags(Request::PREFETCH);
380  return translation_req;
381 }
382 
383 void
384 Queued::insert(const PacketPtr &pkt, PrefetchInfo &new_pfi,
385  int32_t priority)
386 {
387  if (queueFilter) {
388  if (alreadyInQueue(pfq, new_pfi, priority)) {
389  return;
390  }
392  return;
393  }
394  }
395 
396  /*
397  * Physical address computation
398  * if the prefetch is within the same page
399  * using VA: add the computed stride to the original PA
400  * using PA: no actions needed
401  * if we are page crossing
402  * using VA: Create a translaion request and enqueue the corresponding
403  * deferred packet to the queue of pending translations
404  * using PA: use the provided VA to obtain the target VA, then attempt to
405  * translate the resulting address
406  */
407 
408  Addr orig_addr = useVirtualAddresses ?
409  pkt->req->getVaddr() : pkt->req->getPaddr();
410  bool positive_stride = new_pfi.getAddr() >= orig_addr;
411  Addr stride = positive_stride ?
412  (new_pfi.getAddr() - orig_addr) : (orig_addr - new_pfi.getAddr());
413 
414  Addr target_paddr;
415  bool has_target_pa = false;
416  RequestPtr translation_req = nullptr;
417  if (samePage(orig_addr, new_pfi.getAddr())) {
418  if (useVirtualAddresses) {
419  // if we trained with virtual addresses,
420  // compute the target PA using the original PA and adding the
421  // prefetch stride (difference between target VA and original VA)
422  target_paddr = positive_stride ? (pkt->req->getPaddr() + stride) :
423  (pkt->req->getPaddr() - stride);
424  } else {
425  target_paddr = new_pfi.getAddr();
426  }
427  has_target_pa = true;
428  } else {
429  // Page crossing reference
430 
431  // ContextID is needed for translation
432  if (!pkt->req->hasContextId()) {
433  return;
434  }
435  if (useVirtualAddresses) {
436  has_target_pa = false;
437  translation_req = createPrefetchRequest(new_pfi.getAddr(), new_pfi,
438  pkt);
439  } else if (pkt->req->hasVaddr()) {
440  has_target_pa = false;
441  // Compute the target VA using req->getVaddr + stride
442  Addr target_vaddr = positive_stride ?
443  (pkt->req->getVaddr() + stride) :
444  (pkt->req->getVaddr() - stride);
445  translation_req = createPrefetchRequest(target_vaddr, new_pfi,
446  pkt);
447  } else {
448  // Using PA for training but the request does not have a VA,
449  // unable to process this page crossing prefetch.
450  return;
451  }
452  }
453  if (has_target_pa && cacheSnoop &&
454  (inCache(target_paddr, new_pfi.isSecure()) ||
455  inMissQueue(target_paddr, new_pfi.isSecure()))) {
457  DPRINTF(HWPrefetch, "Dropping redundant in "
458  "cache/MSHR prefetch addr:%#x\n", target_paddr);
459  return;
460  }
461 
462  /* Create the packet and find the spot to insert it */
463  DeferredPacket dpp(this, new_pfi, 0, priority);
464  if (has_target_pa) {
465  Tick pf_time = curTick() + clockPeriod() * latency;
466  dpp.createPkt(target_paddr, blkSize, requestorId, tagPrefetch,
467  pf_time);
468  DPRINTF(HWPrefetch, "Prefetch queued. "
469  "addr:%#x priority: %3d tick:%lld.\n",
470  new_pfi.getAddr(), priority, pf_time);
471  addToQueue(pfq, dpp);
472  } else {
473  // Add the translation request and try to resolve it later
474  dpp.setTranslationRequest(translation_req);
475  dpp.tc = cache->system->threads[translation_req->contextId()];
476  DPRINTF(HWPrefetch, "Prefetch queued with no translation. "
477  "addr:%#x priority: %3d\n", new_pfi.getAddr(), priority);
479  }
480 }
481 
482 void
484  DeferredPacket &dpp)
485 {
486  /* Verify prefetch buffer space for request */
487  if (queue.size() == queueSize) {
489  /* Lowest priority packet */
490  iterator it = queue.end();
491  panic_if (it == queue.begin(),
492  "Prefetch queue is both full and empty!");
493  --it;
494  /* Look for oldest in that level of priority */
495  panic_if (it == queue.begin(),
496  "Prefetch queue is full with 1 element!");
497  iterator prev = it;
498  bool cont = true;
499  /* While not at the head of the queue */
500  while (cont && prev != queue.begin()) {
501  prev--;
502  /* While at the same level of priority */
503  cont = prev->priority == it->priority;
504  if (cont)
505  /* update pointer */
506  it = prev;
507  }
508  DPRINTF(HWPrefetch, "Prefetch queue full, removing lowest priority "
509  "oldest packet, addr: %#x\n",it->pfInfo.getAddr());
510  delete it->pkt;
511  queue.erase(it);
512  }
513 
514  if ((queue.size() == 0) || (dpp <= queue.back())) {
515  queue.emplace_back(dpp);
516  } else {
517  iterator it = queue.end();
518  do {
519  --it;
520  } while (it != queue.begin() && dpp > *it);
521  /* If we reach the head, we have to see if the new element is new head
522  * or not */
523  if (it == queue.begin() && dpp <= *it)
524  it++;
525  queue.insert(it, dpp);
526  }
527 
528  if (debug::HWPrefetchQueue)
529  printQueue(queue);
530 }
531 
532 } // namespace prefetch
533 } // namespace gem5
gem5::prefetch::Base::PrefetchInfo::getAddr
Addr getAddr() const
Obtains the address value of this Prefetcher address.
Definition: base.hh:124
gem5::prefetch::Queued::DeferredPacket::finish
void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
Definition: queued.cc:91
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::prefetch::Queued::DeferredPacket::startTranslation
void startTranslation(BaseMMU *mmu)
Issues the translation request to the provided MMU.
Definition: queued.cc:80
gem5::prefetch::Base::useVirtualAddresses
const bool useVirtualAddresses
Use Virtual Addresses for prefetching.
Definition: base.hh:301
gem5::prefetch::Queued::~Queued
virtual ~Queued()
Definition: queued.cc:111
gem5::prefetch::Queued::cacheSnoop
const bool cacheSnoop
Snoop the cache before generating prefetch (cheating basically)
Definition: queued.hh:169
gem5::BaseMMU::Read
@ Read
Definition: mmu.hh:56
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
gem5::prefetch::Queued::notify
void notify(const PacketPtr &pkt, const PrefetchInfo &pfi) override
Notify prefetcher of cache access (may be any access or just misses, depending on cache parameters....
Definition: queued.cc:172
gem5::prefetch::Queued::iterator
std::list< DeferredPacket >::iterator iterator
Definition: queued.hh:146
gem5::prefetch::Base::hasBeenPrefetched
bool hasBeenPrefetched(Addr addr, bool is_secure) const
Definition: base.cc:200
gem5::prefetch::Queued::addToQueue
void addToQueue(std::list< DeferredPacket > &queue, DeferredPacket &dpp)
Adds a DeferredPacket to the specified queue.
Definition: queued.cc:483
base.hh
gem5::prefetch::Queued::QueuedStats::pfRemovedDemand
statistics::Scalar pfRemovedDemand
Definition: queued.hh:184
gem5::prefetch::Queued::DeferredPacket::tick
Tick tick
Time when this prefetch becomes ready.
Definition: queued.hh:69
gem5::MipsISA::misc_reg::Count
@ Count
Definition: misc.hh:94
gem5::prefetch::Queued::getMaxPermittedPrefetches
size_t getMaxPermittedPrefetches(size_t total) const
Returns the maxmimum number of prefetch requests that are allowed to be created from the number of pr...
Definition: queued.cc:142
gem5::prefetch::Queued::DeferredPacket::setTranslationRequest
void setTranslationRequest(const RequestPtr &req)
Sets the translation request needed to obtain the physical address of this request.
Definition: queued.hh:124
gem5::prefetch::Queued::QueuedStats::pfInCache
statistics::Scalar pfInCache
Definition: queued.hh:183
gem5::prefetch::Base::PrefetchInfo::isSecure
bool isSecure() const
Returns true if the address targets the secure memory space.
Definition: base.hh:133
gem5::prefetch::Queued::QueuedStats::pfSpanPage
statistics::Scalar pfSpanPage
Definition: queued.hh:186
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::prefetch::Base::StatGroup::pfIssued
statistics::Scalar pfIssued
Definition: base.hh:334
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:377
gem5::prefetch::Queued::missingTranslationQueueSize
const unsigned missingTranslationQueueSize
Maximum size of the queue holding prefetch requests with missing address translations.
Definition: queued.hh:157
tlb.hh
gem5::Packet::isSecure
bool isSecure() const
Definition: packet.hh:836
gem5::prefetch::Base::inMissQueue
bool inMissQueue(Addr addr, bool is_secure) const
Determine if address is in cache miss queue.
Definition: base.cc:194
std::vector
STL vector class.
Definition: stl.hh:37
gem5::prefetch::Queued::printQueue
void printQueue(const std::list< DeferredPacket > &queue) const
Definition: queued.cc:120
gem5::prefetch::Base::blockAddress
Addr blockAddress(Addr a) const
Determine the address of the block in which a lays.
Definition: base.cc:212
gem5::prefetch::Queued::QueuedStats::pfIdentified
statistics::Scalar pfIdentified
Definition: queued.hh:181
gem5::prefetch::Queued::tagPrefetch
const bool tagPrefetch
Tag prefetch with PC of generating access?
Definition: queued.hh:172
gem5::MemCmd::HardPFReq
@ HardPFReq
Definition: packet.hh:99
gem5::prefetch::Base::requestorId
const RequestorID requestorId
Request id for prefetches.
Definition: base.hh:290
gem5::prefetch::Queued::insert
void insert(const PacketPtr &pkt, PrefetchInfo &new_pfi, int32_t priority)
Definition: queued.cc:384
gem5::prefetch::Queued::calculatePrefetch
virtual void calculatePrefetch(const PrefetchInfo &pfi, std::vector< AddrPriority > &addresses)=0
request.hh
gem5::prefetch::Base::mmu
BaseMMU * mmu
Registered mmu for address translations.
Definition: base.hh:367
queued.hh
gem5::BaseMMU
Definition: mmu.hh:53
gem5::prefetch::Queued::QueuedStats::pfUsefulSpanPage
statistics::Scalar pfUsefulSpanPage
Definition: queued.hh:187
gem5::prefetch::Base::PrefetchInfo::getPC
Addr getPC() const
Returns the program counter that generated this request.
Definition: base.hh:142
gem5::ArmISA::priority
Bitfield< 3, 0 > priority
Definition: misc_types.hh:833
gem5::prefetch::Queued::latency
const Cycles latency
Cycles after generation when a prefetch can first be issued.
Definition: queued.hh:160
gem5::prefetch::Base::samePage
bool samePage(Addr a, Addr b) const
Determine if addresses are on the same page.
Definition: base.cc:206
gem5::Request::PREFETCH
@ PREFETCH
The request is a prefetch.
Definition: request.hh:164
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
gem5::VegaISA::t
Bitfield< 51 > t
Definition: pagetable.hh:56
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:210
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::X86ISA::count
count
Definition: misc.hh:710
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:294
gem5::prefetch::Queued::alreadyInQueue
bool alreadyInQueue(std::list< DeferredPacket > &queue, const PrefetchInfo &pfi, int32_t priority)
Checks whether the specified prefetch request is already in the specified queue.
Definition: queued.cc:338
gem5::prefetch::Base::usefulPrefetches
uint64_t usefulPrefetches
Total prefetches that has been useful.
Definition: base.hh:364
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:108
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::prefetch::Queued::QueuedStats::pfBufferHit
statistics::Scalar pfBufferHit
Definition: queued.hh:182
gem5::prefetch::Queued::DeferredPacket::createPkt
void createPkt(Addr paddr, unsigned blk_size, RequestorID requestor_id, bool tag_prefetch, Tick t)
Create the associated memory packet.
Definition: queued.cc:58
gem5::prefetch::Queued::throttleControlPct
const unsigned int throttleControlPct
Percentage of requests that can be throttled.
Definition: queued.hh:175
std::pair
STL pair class.
Definition: stl.hh:58
gem5::prefetch::Queued::getPacket
PacketPtr getPacket() override
Definition: queued.cc:237
gem5::prefetch::Queued::pfq
std::list< DeferredPacket > pfq
Definition: queued.hh:142
gem5::prefetch::Queued::QueuedStats::QueuedStats
QueuedStats(statistics::Group *parent)
Definition: queued.cc:264
gem5::prefetch::Queued::queueFilter
const bool queueFilter
Filter prefetches if already queued.
Definition: queued.hh:166
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::BaseMMU::translateTiming
virtual void translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode)
Definition: mmu.cc:111
gem5::prefetch::Queued::translationComplete
void translationComplete(DeferredPacket *dp, bool failed)
Indicates that the translation of the address of the provided deferred packet has been successfully c...
Definition: queued.cc:301
gem5::prefetch::Queued::DeferredPacket::tc
ThreadContext * tc
Definition: queued.hh:76
gem5::prefetch::Queued::queueSize
const unsigned queueSize
Maximum size of the prefetch queue.
Definition: queued.hh:151
gem5::prefetch::Base::prefetchStats
gem5::prefetch::Base::StatGroup prefetchStats
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:214
gem5::prefetch::Queued::DeferredPacket::pfInfo
PrefetchInfo pfInfo
Prefetch info corresponding to this packet.
Definition: queued.hh:67
gem5::prefetch::Base::issuedPrefetches
uint64_t issuedPrefetches
Total prefetches issued.
Definition: base.hh:362
gem5::ArmISA::dp
Bitfield< 7, 4 > dp
Definition: misc_types.hh:95
gem5::prefetch::Queued::processMissingTranslations
void processMissingTranslations(unsigned max)
Starts the translations of the queued prefetches with a missing translation.
Definition: queued.cc:286
gem5::Packet::allocate
void allocate()
Allocate memory for the packet.
Definition: packet.hh:1367
gem5::System::threads
Threads threads
Definition: system.hh:310
gem5::prefetch::Queued::DeferredPacket::pkt
PacketPtr pkt
The memory packet generated by this prefetch.
Definition: queued.hh:71
gem5::prefetch::Queued::Queued
Queued(const QueuedPrefetcherParams &p)
Definition: queued.cc:100
gem5::BaseCache::system
System * system
System we are currently operating in.
Definition: base.hh:982
gem5::Request::SECURE
@ SECURE
The request targets the secure memory space.
Definition: request.hh:186
logging.hh
gem5::statistics::Group
Statistics container.
Definition: group.hh:92
gem5::prefetch::Base::cache
BaseCache * cache
Pointr to the parent cache.
Definition: base.hh:266
gem5::prefetch::Base::blkSize
unsigned blkSize
The block size of the parent cache.
Definition: base.hh:269
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
trace.hh
gem5::context_switch_task_id::Prefetcher
@ Prefetcher
Definition: request.hh:83
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::prefetch::Base::inCache
bool inCache(Addr addr, bool is_secure) const
Determine if address is in cache.
Definition: base.cc:188
gem5::prefetch::Queued::createPrefetchRequest
RequestPtr createPrefetchRequest(Addr addr, PrefetchInfo const &pfi, PacketPtr pkt)
Definition: queued.cc:373
std::list< DeferredPacket >
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:807
gem5::prefetch::Queued::const_iterator
std::list< DeferredPacket >::const_iterator const_iterator
Definition: queued.hh:145
gem5::prefetch::Queued::DeferredPacket
Definition: queued.hh:62
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::statistics::total
const FlagsType total
Print the total.
Definition: info.hh:59
gem5::ArmISA::stride
Bitfield< 21, 20 > stride
Definition: misc_types.hh:504
gem5::prefetch::Base
Definition: base.hh:71
gem5::prefetch::Base::PrefetchInfo
Class containing the information needed by the prefetch to train and generate new prefetch requests.
Definition: base.hh:96
gem5::prefetch::Queued::QueuedStats::pfRemovedFull
statistics::Scalar pfRemovedFull
Definition: queued.hh:185
gem5::Clocked::clockPeriod
Tick clockPeriod() const
Definition: clocked_object.hh:217
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::prefetch::Queued::pfqMissingTranslation
std::list< DeferredPacket > pfqMissingTranslation
Definition: queued.hh:143
gem5::prefetch::Base::PrefetchInfo::hasPC
bool hasPC() const
Returns true if the associated program counter is valid.
Definition: base.hh:152
gem5::prefetch::Queued::queueSquash
const bool queueSquash
Squash queued prefetch if demand access observed.
Definition: queued.hh:163
gem5::prefetch::Queued::statsQueued
gem5::prefetch::Queued::QueuedStats statsQueued

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