gem5  v21.2.0.0
DMASequencer.hh
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28 
29 #ifndef __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
30 #define __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
31 
32 #include <memory>
33 #include <ostream>
34 #include <unordered_map>
35 
38 #include "mem/ruby/protocol/DMASequencerRequestType.hh"
40 #include "params/DMASequencer.hh"
41 
42 namespace gem5
43 {
44 
45 namespace ruby
46 {
47 
48 struct DMARequest
49 {
50  DMARequest(uint64_t start_paddr, int len, bool write, int bytes_completed,
51  int bytes_issued, uint8_t *data, PacketPtr pkt);
52 
53  uint64_t start_paddr;
54  int len;
55  bool write;
58  uint8_t *data;
60 };
61 
62 class DMASequencer : public RubyPort
63 {
64  public:
65  typedef DMASequencerParams Params;
66  DMASequencer(const Params &);
67  void init() override;
68 
69  /* external interface */
70  RequestStatus makeRequest(PacketPtr pkt) override;
71  bool busy() { return m_outstanding_count > 0; }
72  int outstandingCount() const override { return m_outstanding_count; }
73  bool isDeadlockEventScheduled() const override { return false; }
74  void descheduleDeadlockEvent() override {}
75 
76  /* SLICC callback */
77  void dataCallback(const DataBlock &dblk, const Addr &addr);
78  void ackCallback(const Addr &addr);
79  void atomicCallback(const DataBlock &dblk, const Addr &addr);
80 
81  void recordRequestType(DMASequencerRequestType requestType);
82 
83  private:
84  void issueNext(const Addr &addr);
85 
87 
88  typedef std::unordered_map<Addr, DMARequest> RequestTable;
90 
93 };
94 
95 } // namespace ruby
96 } // namespace gem5
97 
98 #endif // __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
gem5::ruby::DMARequest::bytes_issued
int bytes_issued
Definition: DMASequencer.hh:57
gem5::ruby::DMASequencer::m_RequestTable
RequestTable m_RequestTable
Definition: DMASequencer.hh:89
gem5::ruby::DMARequest::DMARequest
DMARequest(uint64_t start_paddr, int len, bool write, int bytes_completed, int bytes_issued, uint8_t *data, PacketPtr pkt)
Definition: DMASequencer.cc:57
gem5::ruby::DMASequencer::m_outstanding_count
int m_outstanding_count
Definition: DMASequencer.hh:91
gem5::ruby::DMARequest::bytes_completed
int bytes_completed
Definition: DMASequencer.hh:56
gem5::ruby::DMASequencer::atomicCallback
void atomicCallback(const DataBlock &dblk, const Addr &addr)
Definition: DMASequencer.cc:246
gem5::ruby::DMASequencer::busy
bool busy()
Definition: DMASequencer.hh:71
gem5::ruby::DMASequencer::dataCallback
void dataCallback(const DataBlock &dblk, const Addr &addr)
Definition: DMASequencer.cc:219
gem5::ruby::DMASequencer::makeRequest
RequestStatus makeRequest(PacketPtr pkt) override
Definition: DMASequencer.cc:80
gem5::ruby::DMASequencer::descheduleDeadlockEvent
void descheduleDeadlockEvent() override
Definition: DMASequencer.hh:74
gem5::ruby::DMASequencer::m_data_block_mask
uint64_t m_data_block_mask
Definition: DMASequencer.hh:86
gem5::ruby::DMASequencer::Params
DMASequencerParams Params
Definition: DMASequencer.hh:65
gem5::ruby::DMASequencer::DMASequencer
DMASequencer(const Params &)
Definition: DMASequencer.cc:66
gem5::ruby::DMASequencer
Definition: DMASequencer.hh:62
gem5::ruby::DMASequencer::ackCallback
void ackCallback(const Addr &addr)
Definition: DMASequencer.cc:239
gem5::ruby::DMASequencer::issueNext
void issueNext(const Addr &addr)
Definition: DMASequencer.cc:167
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::ruby::DMARequest::start_paddr
uint64_t start_paddr
Definition: DMASequencer.hh:53
DataBlock.hh
gem5::ruby::DMASequencer::recordRequestType
void recordRequestType(DMASequencerRequestType requestType)
Definition: DMASequencer.cc:265
gem5::ruby::DMASequencer::isDeadlockEventScheduled
bool isDeadlockEventScheduled() const override
Definition: DMASequencer.hh:73
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ruby::DMASequencer::RequestTable
std::unordered_map< Addr, DMARequest > RequestTable
Definition: DMASequencer.hh:88
gem5::ruby::DMASequencer::outstandingCount
int outstandingCount() const override
Definition: DMASequencer.hh:72
gem5::ruby::DMASequencer::m_max_outstanding_requests
int m_max_outstanding_requests
Definition: DMASequencer.hh:92
gem5::ruby::DMARequest::write
bool write
Definition: DMASequencer.hh:55
Address.hh
gem5::ruby::DataBlock
Definition: DataBlock.hh:60
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ruby::DMARequest::pkt
PacketPtr pkt
Definition: DMASequencer.hh:59
RubyPort.hh
gem5::ruby::RubyPort
Definition: RubyPort.hh:64
gem5::ruby::DMASequencer::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: DMASequencer.cc:73
gem5::ruby::DMARequest
Definition: DMASequencer.hh:48
gem5::ruby::DMARequest::len
int len
Definition: DMASequencer.hh:54
gem5::ruby::DMARequest::data
uint8_t * data
Definition: DMASequencer.hh:58
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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