gem5  v21.1.0.2
a2901.h
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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21 
22  a2901.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
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33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 #ifndef A2901_H
39 #define A2901_H
40 
41 #include "a2901_alu.h"
42 #include "a2901_alu_inputs.h"
44 #include "a2901_edge.h"
45 
46 SC_MODULE( a2901 )
47 {
48  // shared state
49  long RAM[15];
50 
51  // signals
52  sig4 RE, S, F, Q, A;
53  sig5 R_ext, S_ext;
54 
55  // constructor
56  a2901( sc_module_name,
57  const sc_clock& CLK_,
58  const sig9& I_,
59  const sig4& Aadd_,
60  const sig4& Badd_,
61  const sig4& D_,
62  const sig1& RAM0_,
63  const sig1& RAM3_,
64  const sig1& Q0_,
65  const sig1& Q3_,
66  const sig1& C0_,
67  const sig1& OEbar_,
68  sig4& Y_,
69  sig1& t_RAM0_,
70  sig1& t_RAM3_,
71  sig1& t_Q0_,
72  sig1& t_Q3_,
73  sig1& C4_,
74  sig1& Gbar_,
75  sig1& Pbar_,
76  sig1& OVR_,
77  sig1& F3_,
78  sig1& F30_ )
79  {
80  SC_NEW( a2901_alu( "alu",
81  I_, RE, S, C0_,
82  R_ext, S_ext, F, OVR_, C4_, Pbar_, Gbar_,
83  F3_, F30_ ) );
84  SC_NEW( a2901_alu_inputs( "alu_inputs",
85  RAM,
86  I_, Aadd_, Badd_, D_, Q,
87  RE, S, A ) );
88  SC_NEW( a2901_output_and_shifter( "o_and_s",
89  I_, OEbar_, A, F, Q,
90  Y_, t_RAM0_, t_RAM3_,
91  t_Q0_, t_Q3_ ) );
92  SC_NEW( a2901_edge( "edge",
93  CLK_,
94  RAM,
95  I_, Badd_, F, Q3_, Q0_, RAM3_, RAM0_,
96  Q ) );
97  // initialize the RAM (to get rid of UMRs)
98  for( int i = 0; i < 15; ++ i ) {
99  RAM[0] = 0;
100  }
101  }
102 };
103 
104 #endif
105 
sig4
sc_signal< int4 > sig4
Definition: common.h:49
SC_NEW
#define SC_NEW(x)
Definition: sc_module.hh:356
gem5::ruby::garnet::I_
@ I_
Definition: CommonTypes.hh:51
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
sig1
sc_signal< int1 > sig1
Definition: common.h:48
sig5
sc_signal< int5 > sig5
Definition: common.h:50
gem5::X86ISA::RE
const uint8_t RE
Definition: decoder_tables.cc:56
a2901_edge.h
a2901_alu_inputs.h
sig9
sc_signal< int9 > sig9
Definition: common.h:51
a2901_output_and_shifter.h
SC_MODULE
SC_MODULE(a2901)
Definition: a2901.h:46
a2901_alu.h

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