gem5 v24.0.0.0
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Class Hierarchy
This inheritance list is sorted roughly, but not completely, alphabetically:
[detail level 123456789]
 Cgem5::_amd_queue_t
 Cgem5::_hsa_agent_dispatch_packet_t
 Cgem5::_hsa_barrier_and_packet_t
 Cgem5::_hsa_barrier_or_packet_t
 Cgem5::_hsa_dispatch_packet_t
 Cgem5::_hsa_generic_vendor_pkt
 Cgem5::_hsa_queue_t
 Cgem5::_hsa_signal_t
 Ca_new_struct
 ►Cgem5::Aapcs32
 ►Cgem5::guest_abi::Aapcs32ArgumentBase
 Cgem5::guest_abi::Aapcs32ArrayType< T >
 Cgem5::guest_abi::Aapcs32ArrayType< E[N]>
 Cgem5::Aapcs64
 ►Cgem5::guest_abi::Aapcs64ArgumentBase
 Cgem5::guest_abi::Aapcs64ArrayType< T >
 Cgem5::guest_abi::Aapcs64ArrayType< E[N]>
 ►CAbiBase
 ►Cgem5::BaseSemihosting::AbiBase
 CAccess
 CRegisterBankTest::Access
 Cmm::access
 Cgem5::X86ISA::GpuTLB::AccessInfoThis hash map will use the virtual page address as a key and will keep track of total number of accesses per page
 Cgem5::ruby::ALUFreeListArray::AccessRecord
 Cgem5::ruby::BankedArray::AccessRecord
 Cgem5::ruby::AccessTraceForAddress
 Cgem5::Episode::Action
 ►Cgem5::ActivityRecorderActivityRecorder helper class that informs the CPU if it can switch over to being idle or not
 Cgem5::AddressManager
 Cgem5::prefetch::IrregularStreamBuffer::AddressMappingAddress Mapping entry, holds an address and a confidence counter
 Cgem5::AddressMonitor
 Cgem5::ruby::AddressProfiler
 Cgem5::decode_cache::AddrMap< Value, CacheChunkShift >A sparse map from an Addr to a Value, stored in page chunks
 Cgem5::decode_cache::AddrMap< gem5::GenericISA::BasicDecodeCache::AddrMapEntry >
 Cgem5::GenericISA::BasicDecodeCache< Decoder, EMI >::AddrMapEntry
 Cgem5::ruby::Network::AddrMapNode
 Cgem5::X86ISA::AddrOp
 Cgem5::AddrRangeEncapsulates an address range, and supports a number of tests to check if two ranges intersect, if a range contains a specific address etc
 Cgem5::AMDGPUDevice::AddrRangeHasher
 Cgem5::AddrRangeMap< V, max_cache_size >The AddrRangeMap uses an STL map to implement an interval tree for address decoding
 Cgem5::AddrRangeMap< bool, 3 >
 Cgem5::AddrRangeMap< gem5::Flags, 1 >
 Cgem5::AddrRangeMap< gem5::MemBackdoor >
 Cgem5::AddrRangeMap< gem5::MemBackdoor, 1 >
 Cgem5::AddrRangeMap< gem5::memory::AbstractMemory *, 1 >
 Cgem5::AddrRangeMap< PortID, 3 >
 Cgem5::branch_prediction::ReturnAddrStack::AddrStackSubclass that implements the actual address stack
 Cgem5::CxxConfigParams::AddToConfigDir
 ►Cgem5::X86ISA::ACPI::Allocator
 Cgem5::ruby::ALUFreeListArray
 ►Camba_pv::amba_pv_from_tlm_bridge
 ►Camba_pv::amba_pv_to_tlm_bridge
 ►Cgem5::AmbaDevice
 Cgem5::amd_event_t
 Cgem5::amd_signal_s
 Cgem5::AMDGPUGfx
 Cgem5::AMDGPUIHRegsStruct to contain all interrupt handler related registers
 Cgem5::AMDGPUInterruptCookie
 Cgem5::AMDGPUNbio
 Cgem5::AMDMMIOReaderHelper class to read Linux kernel MMIO trace from amdgpu modprobes
 Cgem5::ApertureRegister
 Cgem5::AQLRingBufferInternal ring buffer which is used to prefetch/store copies of the in-memory HSA ring buffer
 Cgem5::X86ISA::AddrOp::ArgType
 Cgem5::guest_abi::Argument< ABI, Arg, Enabled >
 ►Cgem5::guest_abi::Argument< Aapcs32, Composite >
 ►Cgem5::guest_abi::Argument< Aapcs32, Integer >
 Cgem5::guest_abi::Argument< Aapcs32Vfp, VarArgs< Types... > >
 Cgem5::guest_abi::Argument< ABI, Arg, typename std::enable_if_t< std::is_base_of_v< ArmISA::RegABI32, ABI > &&std::is_integral_v< Arg > &&ABI::template IsWideV< Arg > > >
 Cgem5::guest_abi::Argument< ABI, Arg, typename std::enable_if_t< std::is_base_of_v< GenericSyscallABI64, ABI > &&(std::is_integral_v< Arg >||std::is_same< Arg, pseudo_inst::GuestAddr >::value)> >
 Cgem5::guest_abi::Argument< ABI, Arg, typename std::enable_if_t< std::is_base_of_v< RiscvISA::RegABI32, ABI > &&std::is_integral_v< Arg > &&ABI::template IsWideV< Arg > > >
 Cgem5::guest_abi::Argument< ABI, Arg, typename std::enable_if_t< std::is_integral_v< Arg > &&!ABI::template IsWideV< Arg > > >
 Cgem5::guest_abi::Argument< Abi, ArmSemihosting::InPlaceArg, typename std::enable_if_t< std::is_base_of_v< ArmSemihosting::AbiBase, Abi > > >
 Cgem5::guest_abi::Argument< ABI, ConstProxyPtr< T, Proxy > >
 Cgem5::guest_abi::Argument< ABI, ProxyPtr< T, Proxy > >
 Cgem5::guest_abi::Argument< Abi, RiscvSemihosting::InPlaceArg, typename std::enable_if_t< std::is_base_of_v< RiscvSemihosting::AbiBase, Abi > > >
 Cgem5::guest_abi::Argument< ABI, VarArgs< Types... > >
 Cgem5::guest_abi::Argument< ArmISA::RegABI32, pseudo_inst::GuestAddr >
 Cgem5::guest_abi::Argument< ArmSemihosting::Abi32, Arg, typename std::enable_if_t<(std::is_integral_v< Arg >||std::is_same< Arg, pseudo_inst::GuestAddr >::value)> >
 ►Cgem5::guest_abi::Argument< ArmSemihosting::Abi32, T >
 Cgem5::guest_abi::Argument< ArmSemihosting::Abi64, Arg, typename std::enable_if_t<(std::is_integral_v< Arg >||std::is_same< Arg, pseudo_inst::GuestAddr >::value)> >
 ►Cgem5::guest_abi::Argument< ArmSemihosting::Abi64, T >
 Cgem5::guest_abi::Argument< RiscvISA::RegABI32, pseudo_inst::GuestAddr >
 Cgem5::guest_abi::Argument< RiscvSemihosting::Abi32, Arg, typename std::enable_if_t< std::is_integral_v< Arg > > >
 Cgem5::guest_abi::Argument< RiscvSemihosting::Abi64, Arg, typename std::enable_if_t< std::is_integral_v< Arg > > >
 Cgem5::guest_abi::Argument< SparcISA::SEWorkload::SyscallABI32, Arg, typename std::enable_if_t< std::is_integral_v< Arg > &&SparcISA::SEWorkload::SyscallABI32::IsWideV< Arg > > >
 Cgem5::guest_abi::Argument< SparcPseudoInstABI, pseudo_inst::GuestAddr >
 Cgem5::guest_abi::Argument< SparcPseudoInstABI, uint64_t >
 Cgem5::guest_abi::Argument< TestABI, Addr >
 Cgem5::guest_abi::Argument< TestABI_1D, Arg, typename std::enable_if_t< std::is_floating_point_v< Arg > > >
 Cgem5::guest_abi::Argument< TestABI_1D, int >
 Cgem5::guest_abi::Argument< TestABI_2D, Arg, typename std::enable_if_t< std::is_floating_point_v< Arg > > >
 Cgem5::guest_abi::Argument< TestABI_2D, int >
 Cgem5::guest_abi::Argument< TestABI_Prepare, int >
 Cgem5::guest_abi::Argument< TestABI_TcInit, int >
 Cgem5::guest_abi::Argument< X86ISA::EmuLinux::SyscallABI32, Arg, typename std::enable_if_t< std::is_integral_v< Arg > &&X86ISA::EmuLinux::SyscallABI32::IsWideV< Arg > > >
 Cgem5::guest_abi::Argument< X86PseudoInstABI, pseudo_inst::GuestAddr >
 Cgem5::guest_abi::Argument< X86PseudoInstABI, uint64_t >
 Carr_struct1
 Carr_struct2
 Cgem5::o3::DynInst::Arrays
 ►Cgem5::AtagHeader
 Cataparams
 ►Cgem5::AtomicOpFunctor
 ►Cgem5::AtomicRequestProtocol
 ►Cgem5::AtomicResponseProtocol
 Cgem5::AddressManager::AtomicStruct
 Cgem5::auxv::AuxVector< IntType >
 Cgem5::statistics::AvgSampleStorTemplatized storage for distribution that calculates per tick mean and variance
 Cgem5::statistics::AvgStorTemplatized storage and interface to a per-tick average stat
 Cb_new_struct
 ►Cgem5::BackdoorManagerThis class manages the backdoors for RangeAddrMapper
 CBackingStore
 Cgem5::memory::BackingStoreEntryA single entry for the backing store
 Cgem5::memory::MemInterface::BankA basic class to track the bank state, i.e
 Cgem5::ruby::BankedArray
 Cgem5::Barrier
 ►CBase
 ►Cgem5::compression::encoder::BaseBase class for encoders
 ►Cgem5::statistics::units::BaseParent class of all unit classes
 ►CTypes::Base
 ►Cgem5::BaseBufferArgBase class for BufferArg and TypedBufferArg, Not intended to be used directly
 ►Cgem5::Iris::BaseCpuEvs
 ►Cgem5::BaseGdbRegCacheConcrete subclasses of this abstract class represent how the register values are transmitted on the wire
 ►Cgem5::BaseGenBase class for all generators, with the shared functionality and virtual functions for entering, executing and leaving the generator
 ►Cgem5::BaseHTMCheckpointTransactional Memory checkpoint
 ►Cgem5::ArmISA::BaseISADeviceBase class for devices that use the MiscReg interfaces
 ►Cgem5::BaseKvmTimerTimer functions to interrupt VM execution after a number of simulation ticks
 ►Cgem5::statistics::BasePrint
 ►Cgem5::BaseRemoteGDB
 ►Cgem5::BaseStackTrace
 ►Cgem5::ArmISA::EmuFreebsd::BaseSyscallABI
 ►Cgem5::ArmISA::EmuLinux::BaseSyscallABI
 ►Cgem5::SparcISA::SEWorkload::BaseSyscallABI
 Cgem5::GenericISA::BasicDecodeCache< Decoder, EMI >
 Cgem5::GenericISA::BasicDecodeCache< gem5::ArmISA::Decoder, gem5::X86ISA::ExtMachInst >
 Cgem5::GenericISA::BasicDecodeCache< gem5::MipsISA::Decoder, ExtMachInst >
 Cgem5::GenericISA::BasicDecodeCache< gem5::PowerISA::Decoder, gem5::X86ISA::ExtMachInst >
 Cgem5::GenericISA::BasicDecodeCache< gem5::SparcISA::Decoder, ExtMachInst >
 Cgem5::BasicSignal
 Cgem5::SimPoint::BBInfoBasic Block information
 Cgem5::AMDGPU::binary32_u
 Csc_gem5::Port::Binding
 Cgem5::bitfield_backend::BitfieldTypes< Storage >
 Cgem5::bitfield_backend::BitUnionBaseType< T >
 Cgem5::bitfield_backend::BitUnionBaseType< BitUnionType< T > >
 Cgem5::VirtIOBlock::BlkRequestVirtIO block device request as sent by guest
 CBlock
 Cgem5::IdeController::Channel::BMIRegsRegisters used for bus master interface
 Cgem5::BmpWriter::BmpPixel32
 Cgem5::branch_prediction::BiModeBP::BPHistory
 Cgem5::branch_prediction::TournamentBP::BPHistoryThe branch history information that is created upon predicting a branch
 Cgem5::Iris::ThreadContext::BpInfo
 Cgem5::minor::BranchDataForward data betwen Execute and Fetch1 carrying change-of-address/stream information
 Cgem5::branch_prediction::LoopPredictor::BranchInfo
 ►Cgem5::branch_prediction::StatisticalCorrector::BranchInfo
 ►Cgem5::branch_prediction::TAGEBase::BranchInfo
 ►Cgem5::SysBridge::BridgingPort
 Cgem5::ArmISA::BrkPoint
 Cgem5::branch_prediction::SimpleBTB::BTBEntry
 Cgem5::minor::BubbleIFInterface class for data with 'bubble' values
 Cgem5::minor::BubbleTraitsAdaptor< ElemType >Pass on call to the element
 Cgem5::minor::BubbleTraitsPtrAdaptor< PtrType, ElemType >Pass on call to the element where the element is a pointer
 Cgem5::VegaISA::BufferRsrcDescriptor
 Cgem5::memory::BurstHelperA burst helper helps organize and manage a packet that is larger than the memory burst size
 ►Cgem5::CacheAccessorProvides generic cache lookup functions
 Cgem5::CacheAccessProbeArgInformation provided to probes on a cache event
 Cgem5::decode_cache::AddrMap< Value, CacheChunkShift >::CacheChunk
 Cgem5::CacheDataUpdateProbeArgA data contents update is composed of the updated block's address, the old contents, and the new contents
 Cgem5::ArmISA::MMU::CachedState
 Cgem5::ruby::CacheRecorder
 Cgem5::FlashDevice::CallBackEntry
 Cgem5::Coroutine< Arg, Ret >::CallerTypeCallerType: A reference to an object of this class will be passed to the coroutine task
 Cgem5::PixelConverter::ChannelColor channel conversion and scaling helper class
 Cgem5::X86ISA::I8237::Channel
 Cgem5::ChannelAddrClass holding a guest address in a contiguous channel-local address space
 Cgem5::ChannelAddrRangeThe ChanneelAddrRange class describes a contiguous range of addresses in a contiguous channel-local address space
 Cgem5::Check
 Cgem5::CheckpointIn
 Cgem5::CheckTable
 Cgem5::ChunkGeneratorThis class takes an arbitrary memory region (address/length pair) and generates a series of appropriately (e.g
 Cgem5::CircleBuf< T >Circular buffer backed by a vector
 Cgem5::CircleBuf< char >
 Cgem5::CircleBuf< value_type >
 Ctlm::circular_buffer< T >
 Ctlm::circular_buffer< REQ >
 Ctlm::circular_buffer< RSP >
 Cgem5::CircularQueue< T >Circular queue
 Cgem5::CircularQueue< Addr >
 Cgem5::CircularQueue< CompactorEntry >
 Cgem5::CircularQueue< gem5::prefetch::SBOOE::SandboxEntry >
 Cgem5::CircularQueue< gem5::prefetch::STeMS::RegionMissOrderBufferEntry >
 Cgem5::CircularQueue< gem5::ruby::RubyPrefetcher::NonUnitFilterEntry >
 Cgem5::CircularQueue< gem5::ruby::RubyPrefetcher::UnitFilterEntry >
 Cgem5::CircularQueue< HistoryBuffer::iterator >
 Cgem5::CircularQueue< LQEntry >
 Cgem5::CircularQueue< SQEntry >
 Cgem5::CircularQueue< Tick >
 Cgem5::VncInput::ClientCutTextMessage
 ►Cgem5::ClockedHelper class for objects that need to be clocked
 Cgem5::ClockRateControlDummyProtocolType
 Cgem5::ruby::CoalescedRequest
 Cgem5::compression::encoder::Code
 CCoeff8
 CCoeff8x8
 Cgem5::memory::DRAMInterface::CommandSimple structure to hold the values needed to keep track of commands for DRAMPower
 Cgem5::ItsCommand::CommandEntry
 Cgem5::MemCmd::CommandInfoStructure that defines attributes and other data associated with a Command
 Cgem5::CommandReg_t
 Cgem5::o3::CommitCommit handles single threaded and SMT commit
 Cgem5::o3::TimeStruct::CommitComm
 Cgem5::prefetch::PIF::CompactorEntryThe compactor tracks retired instructions addresses, leveraging the spatial and temporal locality among instructions for compaction
 Cgem5::BmpWriter::CompleteV1Header
 CCompressed
 Cgem5::compression::FrequentValues::CompData::CompressedValueA compressed value contains its encoding, and the compressed data itself
 ►Cgem5::compression::Base::CompressionData
 Cgem5::VirtIO9PBase::ConfigVirtIO 9p configuration structure
 Cgem5::VirtIOBlock::ConfigBlock device configuration structure
 Cgem5::VirtIOConsole::ConfigConsole configuration structure
 CSimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS >::ConnectionInfo
 Cgem5::System::Threads::const_iterator
 ►Cgem5::ConstProxyPtr< T, Proxy >
 ►Cgem5::ruby::Consumer
 Cgem5::BaseRemoteGDB::GdbCommand::Context
 Cgem5::BaseRemoteGDB::GdbMultiLetterCommand::Context
 Cgem5::BaseRemoteGDB::QuerySetCommand::Context
 Cgem5::ContextDescriptor
 ►Ctlm_utils::convenience_socket_base
 ►Ctlm_utils::convenience_socket_cb_holder
 Cgem5::fastmodel::ResetControllerExample::CorePins
 Cgem5::fastmodel::ScxEvsCortexR52< Types >::CorePins
 Cgem5::MipsISA::CoreSpecific
 Cgem5::Intel8254Timer::CounterCounter element for PIT
 Cgem5::X86ISA::CpuidResult
 Cgem5::X86ISA::CrRegIndex
 Cgem5::ArmISA::Crypto
 Cgem5::RiscvISA::CSRMetadata
 Cgem5::X86ISA::CtrlRegIndex
 Cgem5::CxxConfigDirectoryEntryConfig details entry for a SimObject
 ►Cgem5::CxxConfigFileBaseConfig file wrapper providing a common interface to CxxConfigManager
 Cgem5::CxxConfigManagerThis class allows a config file to be read into gem5 (generating the appropriate SimObjects) from C++
 Cgem5::CxxConfigParamsBase for peer classes of SimObjectParams derived classes with parameter modifying member functions
 Cgem5::CyclesCycles is a wrapper class for representing cycle counts, i.e
 Cgem5::SMMUEvent::Data
 Cgem5::trace::InstRecord::Data
 Cgem5::ruby::DataBlock
 Cgem5::X86ISA::DataHiOp
 Cgem5::X86ISA::DataLowOp
 Cgem5::X86ISA::DataOp
 Cgem5::X86ISA::DbgRegIndex
 Cgem5::o3::DecodeDecode class handles both single threaded and SMT decode
 Cgem5::o3::TimeStruct::DecodeComm
 Cgem5::VegaISA::Decoder
 Cgem5::o3::DecodeStructStruct that defines the information passed from decode to rename
 Cgem5::minor::Decode::DecodeThreadInfoData members after this line are cycle-to-cycle state
 Csc_gem5::DefaultReportMessages
 Cgem5::Bridge::DeferredPacketA deferred packet stores a packet along with its scheduled transmission time
 Cgem5::memory::CfiMemory::DeferredPacketA deferred packet stores a packet along with its scheduled transmission time
 Cgem5::memory::SimpleMemory::DeferredPacketA deferred packet stores a packet along with its scheduled transmission time
 Cgem5::PacketQueue::DeferredPacketA deferred packet, buffered to transmit later
 Cgem5::SerialLink::DeferredPacketA deferred packet stores a packet along with its scheduled transmission time
 Cgem5::prefetch::BOP::DelayQueueEntryIn a first implementation of the BO prefetcher, both banks of the RR were written simultaneously when a prefetched line is inserted into the cache
 Ctlm_utils::peq_with_cb_and_phase< OWNER, TYPES >::delta_list
 Cgem5::o3::DependencyEntry< DynInstPtr >Node in a linked list
 Cgem5::o3::DependencyGraph< DynInstPtr >Array of linked list that maintains the dependencies between producing instructions and consuming instructions
 Cgem5::o3::DependencyGraph< gem5::RefCountingPtr >
 Cstd::deque< T >STL deque class
 Cstd::deque< DmaDoneEventUPtr >
 Cstd::deque< DynInstPtr >
 Cstd::deque< ElemType >
 Cstd::deque< FetchRequestPtr >
 Cstd::deque< gem5::branch_prediction::SimpleIndirectPredictor::HistoryEntry >
 Cstd::deque< gem5::Bridge::DeferredPacket >
 Cstd::deque< gem5::DmaPort::DmaReqState * >
 Cstd::deque< gem5::EventFunctionWrapper >
 Cstd::deque< gem5::memory::MemPacket * >
 Cstd::deque< gem5::minor::ForwardInstData >
 Cstd::deque< gem5::minor::ForwardLineData >
 Cstd::deque< gem5::minor::LSQ::LSQRequest >
 Cstd::deque< gem5::minor::QueuedInst >
 Cstd::deque< gem5::Packet >
 Cstd::deque< gem5::prefetch::BOP::DelayQueueEntry >
 Cstd::deque< gem5::prefetch::PIF::CompactorEntry >
 Cstd::deque< gem5::RefCountingPtr >
 Cstd::deque< gem5::ruby::ALUFreeListArray::AccessRecord >
 Cstd::deque< gem5::ruby::garnet::flit * >
 Cstd::deque< gem5::ruby::SequencerRequest * >
 Cstd::deque< gem5::ruby::TriggerQueue::ValType >
 Cstd::deque< gem5::SerialLink::DeferredPacket >
 Cstd::deque< GPUDynInstPtr >
 Cstd::deque< igbreg::RxDesc * >
 Cstd::deque< igbreg::TxDesc * >
 Cstd::deque< LSQRequestPtr >
 Cstd::deque< RequestPort * >
 Cstd::deque< ResponsePort * >
 Cstd::deque< SrcType * >
 Cstd::deque< std::pair< gem5::Packet, gem5::Wavefront * > >
 Cstd::deque< std::pair< gem5::Packet, GPUDynInstPtr > >
 Cstd::deque< std::pair< GPUDynInstPtr, SCH_STATUS > >
 Cstd::deque< std::pair< Tick, EthPacketPtr > >
 Cstd::deque< struct gem5::FlashDevice::CallBackEntry >
 Cstd::deque< struct gem5::UFSHostDevice::SCSIResumeInfo >
 Cstd::deque< struct gem5::UFSHostDevice::taskStart >
 Cstd::deque< struct gem5::UFSHostDevice::transferInfo >
 Cstd::deque< struct gem5::UFSHostDevice::transferStart >
 Cstd::deque< struct gem5::UFSHostDevice::UTPTransferReqDesc * >
 Cstd::deque< struct gem5::UFSHostDevice::writeToDiskBurst >
 Cstd::deque< T * >
 Cstd::deque< Tick >
 Cstd::deque< tlm::tlm_analysis_if< T > * >
 Cstd::deque< tlm::tlm_generic_payload * >
 Cstd::deque< uint32_t >
 Cstd::deque< uint8_t * >
 Cstd::deque< uint8_t >
 Cgem5::DescheduleDeleter
 ►Cgem5::ArmISA::TableWalker::DescriptorBase
 Cgem5::X86ISA::DestOp
 ►Cgem5::RealViewCtrl::Device
 Cgem5::PciHost::DeviceInterfaceCallback interface from PCI devices to the host
 Cgem5::ItsCommand::DispatchEntryDispatch entry is a metadata struct which contains information about the command (like the name) and the function object implementing the command
 Cgem5::statistics::DistDataGeneral container for distribution data
 Cgem5::DistHeaderPkt
 Cgem5::statistics::DistProxy< Stat >
 Cgem5::statistics::DistStorTemplatized storage and interface for a distribution stat
 Cgem5::HSAPacketProcessor::dma_series_ctxCalls getCurrentEntry once the queueEntry has been dmaRead
 Cgem5::copy_engine_reg::DmaDesc
 Cgem5::ruby::DMARequest
 Cgem5::DoorbellInfo
 Cgem5::RiscvISA::double_width< Type >
 Cgem5::RiscvISA::double_width< float16_t >
 Cgem5::RiscvISA::double_width< float32_t >
 Cgem5::RiscvISA::double_width< float8_t >
 Cgem5::RiscvISA::double_width< int16_t >
 Cgem5::RiscvISA::double_width< int32_t >
 Cgem5::RiscvISA::double_width< int64_t >
 Cgem5::RiscvISA::double_width< int8_t >
 Cgem5::RiscvISA::double_width< uint16_t >
 Cgem5::RiscvISA::double_width< uint32_t >
 Cgem5::RiscvISA::double_width< uint64_t >
 Cgem5::RiscvISA::double_width< uint8_t >
 Cgem5::RiscvISA::double_widthf< Type >
 Cgem5::RiscvISA::double_widthf< int16_t >
 Cgem5::RiscvISA::double_widthf< int32_t >
 Cgem5::RiscvISA::double_widthf< int8_t >
 Cgem5::RiscvISA::double_widthf< uint16_t >
 Cgem5::RiscvISA::double_widthf< uint32_t >
 Cgem5::RiscvISA::double_widthf< uint8_t >
 Cgem5::dp_regsEthernet device registers
 Cgem5::dp_rom
 ►Cgem5::DrainableInterface for objects that might require draining before checkpointing
 Cgem5::DrainManager
 Cgem5::DRAMPowerDRAMPower is a standalone tool which calculates the power consumed by a DRAM in the system
 Cgem5::memory::DRAMSim2WrapperWrapper class to avoid having DRAMSim2 names like ClockDomain etc clashing with the normal gem5 world
 Cgem5::memory::DRAMsim3WrapperWrapper class to avoid having DRAMsim3 names like ClockDomain etc clashing with the normal gem5 world
 ►Cgem5::DuelerA dueler is an entry that may or may not be accounted for sampling
 Cgem5::DuelingMonitorDuel between two sampled options to determine which is the winner
 Cgem5::AddrRange::Dummy
 Cgem5::DummyMatRegContainerDummy type aliases and constants for architectures that do not implement matrix registers
 Cgem5::DummyVecPredRegContainerDummy type aliases and constants for architectures that do not implement vector predicate registers
 Cgem5::DummyVecRegContainerDummy type aliases and constants for architectures that do not implement vector registers
 Cgem5::TraceCPU::ElasticDataGenThe elastic data memory request generator to read protobuf trace containing execution trace annotated with data and ordering dependencies
 Ctlm_utils::time_ordered_list< PAYLOAD >::element
 Cgem5::EmbeddedPyBind
 Cgem5::EmbeddedPython
 Cgem5::Coroutine< Arg, Ret >::Empty
 ►Ctesting::EmptyTestEventListener
 Cgem5::X86ISA::EmulEnv
 Csc_gem5::enable_if< Cond, T >
 Csc_gem5::enable_if< true, T >
 Cgem5::ARMArchTLB::Entry
 Cgem5::ConfigCache::Entry
 Cgem5::EmulationPageTable::Entry
 Cgem5::IniFile::EntryA single key/value pair
 Cgem5::IPACache::Entry
 Cgem5::SMMUTLB::Entry
 Cgem5::WalkCache::Entry
 CExtensionPool< T >::entry
 Cgem5::EtherSwitch::Interface::PortFifo::EntryOrder
 Cgem5::ruby::ExpectedMap< RespType, DataType >::ExpectedState< Type >::EnumClassHash
 Cgem5::Episode
 ►Ceth_addr
 ►Ceth_hdr
 Cgem5::EthPacketData
 Cgem5::networking::EthPtr
 Csc_gem5::Event
 ►Cgem5::EventBaseCommon base class for Event and GlobalEvent, so they can share flag and priority definitions and accessor functions
 Cgem5::GPUComputeDriver::EventList
 ►Cgem5::EventManager
 Cgem5::EventQueueQueue of events sorted in time order
 Cgem5::GenericTimer::CoreTimers::EventStream
 Cgem5::GPUComputeDriver::EventTableEntry
 ►Cstd::exception
 ►Csc_gem5::ExceptionWrapperBase
 ►Cgem5::ExecContextThe ExecContext is an abstract base class the provides the interface used by the ISA to manipulate the state of the CPU model
 Cgem5::ExecStage
 Cgem5::minor::Execute::ExecuteThreadInfo
 Cgem5::ruby::ExpectedMap< RespType, DataType >
 Cgem5::ruby::ExpectedMap< RespType, DataType >::ExpectedState< Type >
 Cgem5::ruby::ExpectedMap< RespType, DataType >::ExpectedState< DataType >
 Cgem5::ruby::ExpectedMap< RespType, DataType >::ExpectedState< RespType >
 Cgem5::ArmISA::vector_element_traits::extend_element< IntDestElemType, IntSrcElemType >
 Cgem5::Extensible< Target >
 ►Cgem5::Extensible< Packet >
 ►Cgem5::Extensible< Request >
 ►Cgem5::ExtensionBaseThis is base of every extension
 CExtensionPool< T >
 CExtensionPool< MultiSocketSimpleSwitchAT::ConnectionInfo >
 Cgem5::X86ISA::ExtMachInst
 Cgem5::compression::DictionaryCompressor< T >::Factory< Head, Tail >Create a factory to determine if input matches a pattern
 Cgem5::compression::DictionaryCompressor< T >::Factory< Head >Specialization to end the recursion
 ►Cstd::false_type
 Cgem5::ArmISA::misc_regs::FarAccessor
 Cgem5::SMMUTranslationProcess::Fault
 ►Cgem5::FaultBase
 Cgem5::X86ISA::FaultOp
 Cgem5::ArmISA::ArmFault::FaultVals
 Cgem5::MipsISA::MipsFaultBase::FaultVals
 Cgem5::SparcISA::SparcFaultBase::FaultVals
 Cgem5::Linux::fd_set
 Cgem5::o3::FetchFetch class handles both single threaded and SMT fetch
 Cgem5::minor::Fetch1::Fetch1ThreadInfoStage cycle-by-cycle state
 Cgem5::minor::Fetch2::Fetch2ThreadInfoData members after this line are cycle-to-cycle state
 Cgem5::FetchUnit::FetchBufDescFetch buffer descriptor
 Cgem5::FetchStage
 Cgem5::o3::FetchStructStruct that defines the information passed from fetch to decode
 Cgem5::FetchUnit
 ►Cgem5::FiberThis class represents a fiber, which is a light weight sort of thread which is cooperatively scheduled and runs sequentially with other fibers, swapping in and out of a single actual thread of execution
 Cgem5::Fifo< T >Simple FIFO implementation backed by a circular buffer
 Cgem5::Fifo< uint8_t >
 Cgem5::BmpWriter::FileHeader
 Cgem5::branch_prediction::MultiperspectivePerceptron::FilterEntryEntry of the branch filter
 Cgem5::TraceCPU::FixedRetryGenGenerator to read protobuf trace containing memory requests at fixed timestamps, perform flow control and issue memory requests
 ►Cgem5::debug::Flag
 Cgem5::Flags< T >Wrapper that groups a few flag bits under the same undelying container
 Cgem5::Flags< CacheCoherenceFlagsType >
 Cgem5::Flags< FlagsStorage >
 Cgem5::Flags< FlagsType >
 Cgem5::Flags< PrivateFlagsType >
 ►Cgem5::ruby::garnet::flit
 Cgem5::ruby::garnet::flitBuffer
 Cgem5::Float16
 Ctlm_utils::fn_container< signature >
 Cgem5::branch_prediction::TAGEBase::FoldedHistory
 Cgem5::cp::Format
 Cgem5::minor::ForwardInstDataForward flowing data between Fetch2,Decode,Execute carrying a packet of instructions of a width appropriate to the configured stage widths
 Cgem5::minor::ForwardLineDataLine fetch data in the forward direction
 Cgem5::AMDGPU::fp16_e5m10_info
 Cgem5::AMDGPU::fp16_e8m7_info
 Cgem5::AMDGPU::fp8_e4m3_info
 Cgem5::AMDGPU::fp8_e5m2_info
 Cgem5::X86ISA::FpRegIndex
 Cgem5::VncServer::FrameBufferRect
 Cgem5::VncServer::FrameBufferUpdate
 Cgem5::VncInput::FrameBufferUpdateReq
 Cgem5::o3::Rename::FreeEntriesStructures whose free entries impact the amount of instructions that can be renamed
 Cgem5::o3::FUPool::FUIdxQueueClass that implements a circular queue to hold FU indices
 ►Cgem5::FunctionalRequestProtocol
 ►Cgem5::FunctionalResponseProtocol
 Cgem5::FunctionProfile
 ►Cgem5::FuncUnit
 Cgem5::FutexKeyFutexKey class defines an unique identifier for a particular futex in the system
 ►Cgem5::qemu::FwCfgItem
 Cgem5::FXSave
 Cgem5::BaseRemoteGDB::GdbCommand
 Cgem5::BaseRemoteGDB::GdbMultiLetterCommand
 ►Cgem5::AMDGPUVM::GEM5_PACKED
 Cgem5::ArmISA::RemoteGDB::AArch32GdbRegCache::GEM5_PACKED
 Cgem5::ArmISA::RemoteGDB::AArch64GdbRegCache::GEM5_PACKED
 ►Cgem5::GEM5_PACKEDPM4 packets
 Cgem5::PowerISA::RemoteGDB::Power64GdbRegCache::GEM5_PACKED
 Cgem5::PowerISA::RemoteGDB::PowerGdbRegCache::GEM5_PACKED
 Cgem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::GEM5_PACKEDRISC-V Register Cache Order and sizes of registers found in ext/gdb-xml/riscv.xml To add support for more CSRs:
 Cgem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::GEM5_PACKEDRISC-V Register Cache Order and sizes of registers found in ext/gdb-xml/riscv.xml To add support for more CSRs:
 Cgem5::X86ISA::RemoteGDB::AMD64GdbRegCache::GEM5_PACKED
 Cgem5::GenericSatCounter< T >Implements an n bit saturating counter and provides methods to increment, decrement, and read it
 Cgem5::GenericSatCounter< uint32_t >
 Cgem5::GenericSatCounter< uint8_t >
 ►Cgem5::GenericSyscallABI
 ►Cgem5::GicV2Registers
 Cgem5::GicV2Types
 ►Csvp_gicv3_comms::gicv3_comms_fw_if
 ►Cgem5::Gicv3Registers
 Cgem5::GicV3Types
 Cgem5::GlobalMemPipeline
 Cgem5::X86ISA::GpRegIndexClasses for register indices passed to instruction constructors
 ►Cgem5::GPUExecContext
 Cgem5::VegaISA::GPUISA
 ►CGPUStaticInstFlags
 Cgem5::TraceCPU::ElasticDataGen::GraphNodeThe struct GraphNode stores an instruction in the trace file
 ►Cgem5::statistics::GroupStatistics container
 Cgem5::GTestException
 Cgem5::GTestTickHandler
 Cgem5::pseudo_inst::GuestAddrThis struct wrapper for Addr enables m5ops for systems with 32 bit pointer, since it allows to distinguish between address arguments and native C++ types
 Cgem5::ExternalMaster::Handler
 ►Cgem5::ExternalSlave::Handler
 Cgem5::TraceCPU::ElasticDataGen::HardwareResourceModels structures that hold the in-flight nodes
 Cgem5::stl_helpers::hash_impl::hash< T, typename >
 ►Cstd::hash
 Cstd::hash< gem5::ArmISA::MiscRegNum32 >
 Cstd::hash< gem5::ArmISA::MiscRegNum64 >
 Cstd::hash< gem5::BasicBlockRange >
 Cstd::hash< gem5::ChannelAddr >
 Cstd::hash< gem5::FutexKey >The unordered_map structure needs the parenthesis operator defined for std::hash if a user defined key is used
 Cstd::hash< gem5::RegId >
 Cstd::hash< gem5::ruby::MachineID >
 Cstd::hash< gem5::X86ISA::ExtMachInst >
 Cgem5::stl_helpers::hash_impl::hash< std::pair< T, U > >
 Cgem5::stl_helpers::hash_impl::hash< std::tuple< T... > >
 Cgem5::stl_helpers::hash_impl::hash< T, std::enable_if_t< !is_std_hash_enabled_v< T > &&is_iterable_v< T > > >
 Cgem5::PcCountPair::HashFunctionEnable hashing for this parameter
 Cgem5::UFSHostDevice::HCIMemHost Controller Interface This is a set of registers that allow the driver to control the transactions to the flash devices
 Cgem5::DistHeaderPkt::Header
 Cgem5::VirtQueue::VirtRing< T >::Header
 Cgem5::ruby::Histogram
 Cgem5::branch_prediction::SimpleIndirectPredictor::HistoryEntry
 ►Cgem5::branch_prediction::MultiperspectivePerceptron::HistorySpecBase class to implement the predictor tables
 Cgem5::statistics::HistStorTemplatized storage and interface for a histogram stat
 Cgem5::HorizontalSlice< ElemType, Container, FromTile >Provides a view of a horizontal slice of either a MatStore or a Tile
 Cgem5::Gicv3CPUInterface::hppi_t
 Chsa_agent_dispatch_packet_sAgent dispatch packet
 Chsa_agent_sStruct containing an opaque handle to an agent, a device that participates in the HSA memory model
 Chsa_barrier_and_packet_sBarrier-AND packet
 Chsa_barrier_or_packet_sBarrier-OR packet
 Chsa_cache_sCache handle
 Chsa_callback_data_sApplication data handle that is passed to the serialization and deserialization functions
 Chsa_code_object_reader_sCode object reader handle
 Chsa_code_object_sStruct containing an opaque handle to a code object, which contains ISA for finalized kernels and indirect functions together with information about the global or readonly segment variables they reference
 Chsa_code_symbol_sCode object symbol handle
 Chsa_dim3_sThree-dimensional coordinate
 Chsa_executable_sStruct containing an opaque handle to an executable, which contains ISA for finalized kernels and indirect functions together with the allocated global or readonly segment variables they reference
 Chsa_executable_symbol_sExecutable symbol handle
 Chsa_isa_sInstruction set architecture
 Chsa_kernel_dispatch_packet_sAQL kernel dispatch packet
 Chsa_loaded_code_object_sLoaded code object handle
 Cgem5::hsa_packet_header_bitfield_t
 Chsa_queue_sUser mode queue
 Chsa_region_sA memory region represents a block of virtual memory with certain properties
 Chsa_signal_group_sGroup of signals
 Chsa_signal_sSignal handle
 Chsa_wavefront_sWavefront handle
 Cgem5::HSAQueueDescriptor
 Cgem5::HSAQueueEntry
 CHUFFMTBL_ENTRY
 Cgem5::HWScheduler
 Csc_dt::ieee_double
 Csc_dt::ieee_float
 Cgem5::o3::IEWIEW handles both single threaded and SMT IEW (issue/execute/writeback)
 Cgem5::o3::TimeStruct::IewComm
 Cgem5::o3::IEWStructStruct that defines the information passed from IEW to commit
 ►Cgem5::loader::ImageFile
 Cgem5::loader::ImageFileData
 ►Cgem5::ImgWriter
 Cgem5::X86ISA::Imm64Op
 Cgem5::X86ISA::Imm8Op
 Cgem5::branch_prediction::SimpleIndirectPredictor::IndirectHistoryIndirect branch history information Used for prediction, update and recovery
 Cgem5::VegaISA::InFmt_DS
 Cgem5::VegaISA::InFmt_DS_1
 Cgem5::VegaISA::InFmt_EXP
 Cgem5::VegaISA::InFmt_EXP_1
 Cgem5::VegaISA::InFmt_FLAT
 Cgem5::VegaISA::InFmt_FLAT_1
 Cgem5::VegaISA::InFmt_INST
 Cgem5::VegaISA::InFmt_MIMG
 Cgem5::VegaISA::InFmt_MIMG_1
 Cgem5::VegaISA::InFmt_MTBUF
 Cgem5::VegaISA::InFmt_MTBUF_1
 Cgem5::VegaISA::InFmt_MUBUF
 Cgem5::VegaISA::InFmt_MUBUF_1
 Cgem5::VegaISA::InFmt_SMEM
 Cgem5::VegaISA::InFmt_SMEM_1
 Cgem5::VegaISA::InFmt_SOP1
 Cgem5::VegaISA::InFmt_SOP2
 Cgem5::VegaISA::InFmt_SOPC
 Cgem5::VegaISA::InFmt_SOPK
 Cgem5::VegaISA::InFmt_SOPP
 Cgem5::VegaISA::InFmt_VINTRP
 Cgem5::VegaISA::InFmt_VOP1
 Cgem5::VegaISA::InFmt_VOP2
 Cgem5::VegaISA::InFmt_VOP3_1
 Cgem5::VegaISA::InFmt_VOP3A
 Cgem5::VegaISA::InFmt_VOP3B
 Cgem5::VegaISA::InFmt_VOP3P
 Cgem5::VegaISA::InFmt_VOP3P_1
 Cgem5::VegaISA::InFmt_VOP3P_MAI
 Cgem5::VegaISA::InFmt_VOP3P_MAI_1
 Cgem5::VegaISA::InFmt_VOP_DPP
 Cgem5::VegaISA::InFmt_VOP_SDWA
 Cgem5::VegaISA::InFmt_VOP_SDWAB
 Cgem5::VegaISA::InFmt_VOPC
 Cgem5::sinic::registers::Info
 ►Cgem5::statistics::Info
 ►Cgem5::statistics::InfoAccess
 Cgem5::BmpWriter::InfoHeaderV1
 Cgem5::IniFileThis class represents the contents of a ".ini" file
 Cgem5::BaseSemihosting::InPlaceArg
 Cgem5::minor::Latch< Data >::InputEncapsulate wires on either input or output of the latch
 Cgem5::ruby::garnet::NetworkInterface::InputPort
 Cgem5::TraceCPU::ElasticDataGen::InputStreamThe InputStream encapsulates a trace file and the internal buffers and populates GraphNodes based on the input
 Cgem5::TraceCPU::FixedRetryGen::InputStreamThe InputStream encapsulates a trace file and the internal buffers and populates TraceElements based on the input
 Cgem5::TraceGen::InputStreamThe InputStream encapsulates a trace file and the internal buffers and populates TraceElements based on the input
 Ctlm_utils::instance_specific_extension_accessor
 Ctlm_utils::instance_specific_extension_container
 Ctlm_utils::instance_specific_extension_container_pool
 Ctlm_utils::instance_specific_extensions_per_accessor
 Cgem5::X86ISA::Decoder::InstBytes
 ►Cgem5::trace::TarmacBaseRecord::InstEntryTARMAC instruction trace record
 Cgem5::o3::ElasticTrace::InstExecInfo
 Cgem5::VegaISA::InstFormat
 Cgem5::minor::InstIdId for lines and instructions
 Cinstr
 ►Cgem5::trace::InstRecord
 Cgem5::InstResult
 Cgem5::o3::InstructionQueueA standard instruction queue class
 Cgem5::Iob::IntBusy
 Cgem5::Iob::IntCtl
 Cgem5::X86ISA::smbios::SMBiosTable::SMBiosHeader::IntermediateHeader
 CMultiSocketSimpleSwitchAT::internalPEQTypes
 Cgem5::Iob::IntMan
 Cgem5::ArmV8KvmCPU::IntRegInfoMapping between integer registers in gem5 and KVM
 Cgem5::IntSinkPinBase< gem5::Clint >
 Cgem5::IntSinkPinBase< gem5::RiscvISA::Interrupts >
 Cgem5::IntSinkPinBase< gem5::X86ISA::I82094AA >
 Cgem5::IntSinkPinBase< gem5::X86ISA::I8259 >
 Cgem5::IntSinkPinBase< gem5::X86ISA::Interrupts >
 Cgem5::IntSourcePinBase< gem5::X86IdeController >
 Cgem5::IntSourcePinBase< gem5::X86ISA::Cmos::X86RTC >
 Cgem5::IntSourcePinBase< gem5::X86ISA::I8042 >
 Cgem5::IntSourcePinBase< gem5::X86ISA::I8254 >
 Cgem5::IntSourcePinBase< gem5::X86ISA::I8259 >
 ►Cip6_hdr
 Cgem5::networking::ip6_opt_dstopts
 Cgem5::networking::ip6_opt_fragment
 ►Cgem5::networking::ip6_opt_hdr
 Cgem5::networking::ip6_opt_routing_type2
 Cgem5::networking::Ip6Ptr
 ►Cip_hdr
 ►Cip_opt
 ►Cgem5::networking::IpAddress
 Cgem5::networking::IpPtr
 Cgem5::branch_prediction::SimpleIndirectPredictor::IPredEntry
 Csc_gem5::is_const< T >
 Csc_gem5::is_const< const T >
 Csc_gem5::is_more_const< CT, T >
 Csc_gem5::is_same< T, U >
 Csc_gem5::is_same< T, T >
 ►Ctlm_utils::ispex_base
 Cgem5::o3::IssueStruct
 Cgem5::CircularQueue< T >::iteratorIterator to the circular queue
 Cgem5::ItsAction
 Cgem5::VncInput::KeyEventMessage
 Cgem5::kfd_event_data
 Cgem5::kfd_hsa_hw_exception_data
 Cgem5::kfd_hsa_memory_exception_data
 Cgem5::kfd_ioctl_acquire_vm_args
 Cgem5::kfd_ioctl_alloc_memory_of_gpu_args
 Cgem5::kfd_ioctl_alloc_queue_gws_args
 Cgem5::kfd_ioctl_create_event_args
 Cgem5::kfd_ioctl_create_queue_args
 Cgem5::kfd_ioctl_dbg_address_watch_args
 Cgem5::kfd_ioctl_dbg_register_args
 Cgem5::kfd_ioctl_dbg_unregister_args
 Cgem5::kfd_ioctl_dbg_wave_control_args
 Cgem5::kfd_ioctl_destroy_event_args
 Cgem5::kfd_ioctl_destroy_queue_args
 Cgem5::kfd_ioctl_free_memory_of_gpu_args
 Cgem5::kfd_ioctl_get_clock_counters_args
 Cgem5::kfd_ioctl_get_dmabuf_info_args
 Cgem5::kfd_ioctl_get_process_apertures_args
 Cgem5::kfd_ioctl_get_process_apertures_new_args
 Cgem5::kfd_ioctl_get_queue_wave_state_args
 Cgem5::kfd_ioctl_get_tile_config_args
 Cgem5::kfd_ioctl_get_version_args
 Cgem5::kfd_ioctl_import_dmabuf_args
 Cgem5::kfd_ioctl_map_memory_to_gpu_args
 Cgem5::kfd_ioctl_reset_event_args
 Cgem5::kfd_ioctl_set_cu_mask_args
 Cgem5::kfd_ioctl_set_event_args
 Cgem5::kfd_ioctl_set_memory_policy_args
 Cgem5::kfd_ioctl_set_scratch_backing_va_args
 Cgem5::kfd_ioctl_set_trap_handler_args
 Cgem5::kfd_ioctl_smi_events_args
 Cgem5::kfd_ioctl_unmap_memory_from_gpu_args
 Cgem5::kfd_ioctl_update_queue_args
 Cgem5::kfd_ioctl_wait_events_args
 Cgem5::kfd_memory_exception_failure
 Cgem5::kfd_process_device_apertures
 Cgem5::KvmKVM parent interface
 Cgem5::ArmKvmCPU::KvmCoreMiscRegInfo
 Cgem5::KvmDeviceKVM device wrapper
 Cgem5::KvmFPReg
 Cgem5::ArmKvmCPU::KvmIntRegInfo
 ►Cgem5::KvmKernelGicKVM in-kernel GIC abstraction
 Cgem5::Packet::PrintReqState::LabelStackEntryAn entry in the label stack
 Cgem5::AddressManager::LastWriter
 Cgem5::minor::Latch< Data >Wraps a MinorBuffer with Input/Output interfaces to ensure that units within the model can only see the right end of buffers between them
 Cgem5::minor::Latch< gem5::minor::BranchData >
 Cgem5::minor::Latch< gem5::minor::ForwardInstData >
 Cgem5::minor::Latch< gem5::minor::ForwardLineData >
 Cgem5::LdsChunkThis represents a slice of the overall LDS, intended to be associated with an individual workgroup
 Cgem5::LinearEquationThis class describes a linear equation with constant coefficients
 Cgem5::LinearSystem
 Cgem5::EtherLink::Link
 Cgem5::ruby::LinkEntry
 Cgem5::ruby::WeightBased::LinkInfo
 Cstd::list< T >STL list class
 Cstd::list< AddrRange >
 Cstd::list< DeferredPacket >
 Cstd::list< DynInstPtr >
 Cstd::list< EtherInt * >
 Cstd::list< gem5::ArmISA::TableWalker::WalkerState * >
 Cstd::list< gem5::BasicSignal >
 Cstd::list< gem5::CacheBlk::Lock >
 Cstd::list< gem5::CxxConfigManager::Renaming >
 Cstd::list< gem5::Event * >
 Cstd::list< gem5::memory::CfiMemory::DeferredPacket >
 Cstd::list< gem5::memory::LockedAddr >
 Cstd::list< gem5::memory::SimpleMemory::DeferredPacket >
 Cstd::list< gem5::o3::InstructionQueue::ListOrderEntry >
 Cstd::list< gem5::o3::Rename::RenameHistory >
 Cstd::list< gem5::PacketFifoEntry >
 Cstd::list< gem5::PCEvent * >
 Cstd::list< gem5::prefetch::Queued::DeferredPacket >
 Cstd::list< gem5::RefCountingPtr >
 Cstd::list< gem5::RiscvISA::Walker::WalkerState * >
 Cstd::list< gem5::ruby::Throttle >
 Cstd::list< gem5::SimObject * >
 Cstd::list< gem5::SMMUProcess * >
 Cstd::list< gem5::SMMUTranslationProcess * >
 Cstd::list< gem5::SparcISA::TlbEntry * >
 Cstd::list< gem5::trace::TarmacParserRecord::ParserRegEntry >
 Cstd::list< gem5::TraceCPU::ElasticDataGen::ReadyNode >
 Cstd::list< gem5::VegaISA::Walker::WalkerState * >
 Cstd::list< gem5::VMA >
 Cstd::list< gem5::X86ISA::Walker::WalkerState * >
 Cstd::list< InstSeqNum >
 Cstd::list< int >
 Cstd::list< iterator >
 Cstd::list< LabelStackEntry >
 Cstd::list< ListOrderEntry >
 Cstd::list< NodeSeqNum >
 Cstd::list< RequestorID >
 Cstd::list< RetryEntry >
 Cstd::list< ScEvent * >
 ►Cstd::list< std::function< void()> >
 Cstd::list< std::pair< int, int > >
 Cstd::list< std::shared_ptr< gem5::ExtensionBase > >
 Cstd::list< std::unique_ptr< gem5::MemBackdoor > >
 ►Cstd::list< Target >
 Cstd::list< ThreadID >
 Cstd::list< Tick >
 Cstd::list< TimeSlot * >
 Cstd::list< TlbEntry * >
 Cstd::list< Transaction >
 Cstd::list< TranslationGen::Range >
 Cstd::list< unsigned >
 Cstd::list< WriteCluster >
 Cgem5::ListenSocketConfig
 ►Csc_gem5::ListNode
 Cgem5::o3::InstructionQueue::ListOrderEntryEntry for the list age ordering by op class
 Cgem5::Process::LoaderEach instance of a Loader subclass will have a chance to try to load an object file when tryLoaders is called
 Cgem5::Logger::Loc
 Cgem5::branch_prediction::MultiperspectivePerceptron::LocalHistoriesLocal history entries, each enty contains the history of directions taken by a given branch
 Cgem5::LocalMemPipeline
 ►Cgem5::compression::DictionaryCompressor< uint32_t >::LocatedMaskedPattern
 Cgem5::CacheBlk::LockRepresents that the indicated thread context has a "lock" on the block, in the LL/SC sense
 Cgem5::memory::LockedAddrLocked address class that represents a physical address and a context id
 Cgem5::Logger
 ►Cgem5::trace::LoggerDebug logging base class
 Cgem5::ArmISA::TableWalker::WalkerState::LongDescDataHelper variables used to implement hierarchical access permissions when the long-desc
 Cgem5::X86ISA::LongModePTE
 Cgem5::ArmISA::TlbEntry::Lookup
 Cgem5::branch_prediction::LoopPredictor::LoopEntry
 Cgem5::o3::LSQ
 ►Cgem5::o3::LSQUnit::LSQEntry
 Cgem5::o3::LSQUnitClass that implements the actual LQ and SQ for each specific thread
 Cgem5::o3::ltseqnum
 Cgem5::UFSHostDevice::LUNInfoLogic unit information structure
 Cgem5::LupioTMR::LupioTimer
 Cgem5::ruby::MachineID
 Cgem5::PCEventQueue::MapCompare
 Cgem5::VMA::MappedFileBufferMappedFileBuffer is a wrapper around a region of host memory backed by a file
 ►Cgem5::compression::DictionaryCompressor< uint32_t >::MaskedPattern
 ►Cgem5::compression::DictionaryCompressor< uint32_t >::MaskedValuePattern
 Cgem5::MathExpr
 CMatrix64x12
 Cgem5::MatStore< X, Y >Backing store for matrices
 Cgem5::MatStore< size, size >
 ►Cgem5::X86ISA::ACPI::MADT::Record::Mem
 ►Cgem5::X86ISA::ACPI::SysDescTable::Mem
 Cgem5::MemBackdoor
 Cgem5::MemBackdoorReq
 Cgem5::MemberFunctionSignature< F >
 Cgem5::MemberFunctionSignature< R(C::*)(A...) const >
 Cgem5::MemberFunctionSignature< R(C::*)(A...) const volatile >
 Cgem5::MemberFunctionSignature< R(C::*)(A...) volatile >
 Cgem5::MemberFunctionSignature< R(C::*)(A...)>
 Cgem5::MemCmd
 Cgem5::o3::MemDepUnit::MemDepEntryMemory dependence entries that track memory operations, marking when the instruction is ready to execute and what instructions depend upon it
 Cgem5::o3::MemDepUnitMemory dependency unit class
 ►Cgem5::trace::TarmacBaseRecord::MemEntryTARMAC memory access trace record (stores only)
 Cgem5::Memoizer< Ret, Args >This class takes a function as a constructor argument and memoizes it: every time the function gets invoked through the Memoizer object (see operator()), the result gets saved in the internal cache, ready to be retrieved next time an invokation is made with the same arguments
 Cgem5::Memoizer< int, gem5::ThreadContext *, bool, bool, TCR, ExceptionLevel >
 Cgem5::loader::MemoryImage
 Cgem5::KvmVM::MemorySlotStructures tracking memory slots
 Cgem5::memory::MemPacketA memory packet stores packets along with the timestamp of when the packet entered the queue, and also the decoded address
 ►Cgem5::X86ISA::ACPI::RSDP::MemR0
 Cgem5::KvmVM::MemSlot
 ►Cgem5::ruby::Message
 Cgem5::scmi::Message
 Cgem5::X86ISAInst::MicrocodeRom
 CMipsAccess
 Cgem5::ArmV8KvmCPU::MiscRegInfoMapping between misc registers in gem5 and registers in KVM
 Cgem5::ArmISA::MiscRegLUTEntryMiscReg metadata
 Cgem5::ArmISA::MiscRegLUTEntryInitializerMetadata table accessible via the value of the register
 Cgem5::ArmISA::MiscRegNum32
 Cgem5::ArmISA::MiscRegNum64
 Cgem5::AMDMMIOReader::MmioTrace
 Cgem5::ruby::MN_TBEStorage< RetryEntry >
 Csc_gem5::Module
 Cgem5::ArmISA::misc_regs::MpamAccessor
 ►Cgem5::branch_prediction::MultiperspectivePerceptron::MPPBranchInfoBranch information data
 CMSICAPDefines the MSI Capability register and its associated bitfields for the a PCI/PCIe device
 CMSIXDefines the MSI-X Capability register and its associated bitfields for a PCIe device
 CMSIXCAP
 CMSIXPbaEntry
 CMSIXTable
 Ctlm_utils::multi_init_base_if< TYPES >
 ►Ctlm_utils::multi_init_base_if< tlm::tlm_base_protocol_types >
 Ctlm_utils::multi_target_base_if< TYPES >
 ►Ctlm_utils::multi_target_base_if< tlm::tlm_base_protocol_types >
 Ctlm_utils::multi_to_multi_bind_base< TYPES >
 ►Ctlm_utils::multi_to_multi_bind_base< tlm::tlm_base_protocol_types >
 Cgem5::AMDGPU::mxfp< FMT >
 Cmy_extended_payload_types
 ►Cgem5::NamedInterface for things with names
 Cgem5::ruby::NetDest
 Cgem5::minor::NoBubbleTraits< ElemType >... BubbleTraits are trait classes to add BubbleIF interface functionality to templates which process elements which don't necessarily implement BubbleIF themselves
 Cgem5::compression::encoder::Huffman::NodeNode for the Huffman tree
 Cgem5::MathExpr::Node
 Cgem5::StackDistCalc::NodeNode which takes form of Leaf, INode or Root
 ►Cgem5::statistics::NodeBase class for formula statistic node
 Cgem5::Trie< Key, Value >::Node
 Cgem5::compression::encoder::Huffman::NodeComparatorEntries are not inserted directly into the tree
 Cgem5::TCPIface::NodeInfoCompute node info and storage for the very first connection from each node (used by the switch)
 Cgem5::ns_desc32
 Cgem5::ns_desc64
 Cstd::numeric_limits< gem5::AMDGPU::binary32 >
 Cstd::numeric_limits< gem5::AMDGPU::fp16_e5m10_info >
 Cstd::numeric_limits< gem5::AMDGPU::fp16_e8m7_info >
 Cstd::numeric_limits< gem5::AMDGPU::fp8_e4m3_info >
 Cstd::numeric_limits< gem5::AMDGPU::fp8_e5m2_info >
 Csc_gem5::Object
 ►Cgem5::loader::ObjectFileFormat
 Cgem5::ObjectMatchObjectMatch contains a vector of expressions
 Cgem5::OpenFlagTable< Target >
 ►Cgem5::OpenFlagTable< ArmFreebsd32 >
 ►Cgem5::OpenFlagTable< ArmFreebsd64 >
 ►Cgem5::OpenFlagTable< ArmLinux32 >
 ►Cgem5::OpenFlagTable< ArmLinux64 >
 ►Cgem5::OpenFlagTable< MipsLinux >
 ►Cgem5::OpenFlagTable< PowerLinux >
 ►Cgem5::OpenFlagTable< RiscvLinux32 >
 ►Cgem5::OpenFlagTable< RiscvLinux64 >
 ►Cgem5::OpenFlagTable< SparcLinux >
 ►Cgem5::OpenFlagTable< SparcSolaris >
 ►Cgem5::OpenFlagTable< X86Linux32 >
 ►Cgem5::OpenFlagTable< X86Linux64 >
 ►Cgem5::VegaISA::Operand
 Coperand
 Cgem5::OperandInfo
 ►COperands...
 ►Cgem5::OperatingSystemThis class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to an operating system syscall interface
 Cgem5::MathExpr::OpSearch
 Cgem5::statistics::OpString< Op >
 Cgem5::statistics::OpString< std::divides< Result > >
 Cgem5::statistics::OpString< std::minus< Result > >
 Cgem5::statistics::OpString< std::modulus< Result > >
 Cgem5::statistics::OpString< std::multiplies< Result > >
 Cgem5::statistics::OpString< std::negate< Result > >
 Cgem5::statistics::OpString< std::plus< Result > >
 Cgem5::VegaISA::OpTraits< T >Convenience traits so we can automatically infer the correct FP type without looking at the number of dwords (i.e., to determine if we need a float or a double when creating FP constants)
 Cgem5::VegaISA::OpTraits< ScalarRegF64 >
 Cgem5::VegaISA::OpTraits< ScalarRegU64 >
 Cgem5::RegisterFileCache::OrderedRegs
 ►Cstd::ostringstream
 Cgem5::minor::Latch< Data >::Output
 ►Cgem5::statistics::Output
 Cgem5::OutputDirectoryInterface for creating files in a gem5 output directory
 Cgem5::ruby::garnet::NetworkInterface::OutputPort
 Cgem5::ruby::PerfectSwitch::OutputPort
 ►Cgem5::OutputStream
 Cgem5::TesterThread::OutstandingReq
 Cgem5::ruby::garnet::OutVcState
 Cgem5::P9MsgHeader
 Cgem5::P9MsgInfo
 Cgem5::VegaISA::PackedReg< BITS, ELEM_SIZE >
 Cgem5::SysBridge::PacketData
 Cgem5::PacketFifo
 Cgem5::PacketFifoEntry
 Cgem5::probing::PacketInfoA struct to hold on to the essential fields from a packet, so that the packet and underlying request can be safely passed on, and consequently modified or even deleted
 Cgem5::FlashDevice::PageMapEntryEvery logical address maps to a physical block and a physical page
 Cgem5::SparcISA::PageTableEntry
 ►Cgem5::ArmISA::PageTableOps
 Cstd::pair< X, Y >STL pair class
 Cstd::pair< Addr, Addr >
 Cstd::pair< Addr, std::vector< uint8_t > >
 Cstd::pair< flit_stage, Tick >
 Cstd::pair< gem5::Packet, gem5::Wavefront * >
 Cstd::pair< gem5::Packet, GPUDynInstPtr >
 Cstd::pair< gem5::TCPIface::NodeInfo, int >
 Cstd::pair< gem5::Wavefront *, bool >
 Cstd::pair< GPUDynInstPtr, SCH_STATUS >
 Cstd::pair< int, AtomicOpFunctor * >
 Cstd::pair< int, int >
 Cstd::pair< std::string, sc_gem5::VcdTraceValBase * >
 Cstd::pair< Tick, EthPacketPtr >
 Cstd::pair< tlm::tlm_dmi, bool >
 Cstd::pair< uint32_t, ExceptionCode >
 Cstd::pair< VC_state_type, Tick >
 Cgem5::FALRU::PairHashHash table type mapping addresses to cache block pointers
 Cgem5::CxxConfigDirectoryEntry::ParamDesc
 Cgem5::ParseParam< T, Enable >
 Cgem5::ParseParam< BitUnionType< T > >
 Cgem5::ParseParam< bool >
 Cgem5::ParseParam< DummyMatRegContainer >
 Cgem5::ParseParam< DummyVecPredRegContainer >
 Cgem5::ParseParam< DummyVecRegContainer >
 Cgem5::ParseParam< MatStore< X, Y > >Calls required for serialization/deserialization
 Cgem5::ParseParam< std::string >
 Cgem5::ParseParam< T, decltype(to_number("", std::declval< T & >()), void())>
 Cgem5::ParseParam< T, std::enable_if_t< std::is_base_of_v< typename RegisterBankBase::RegisterBaseBase, T > > >
 Cgem5::ParseParam< VecPredRegContainer< NumBits, Packed > >
 Cgem5::ParseParam< VecRegContainer< Sz > >Calls required for serialization/deserialization
 ►Cgem5::compression::DictionaryCompressor< T >::PatternThe compressed data is composed of multiple pattern entries
 ►Cgem5::compression::DictionaryCompressor< uint32_t >::Pattern
 Cgem5::prefetch::SignaturePath::PatternStrideEntryA stride entry with its counter
 Cgem5::pcap_file_header
 Cgem5::pcap_pkthdr
 Cgem5::linux::pcb_struct
 Cgem5::PcCountPair
 ►Cgem5::PCEvent
 ►Cgem5::PCEventScope
 Cgem5::PciBusAddr
 Cgem5::prefetch::Stride::PCTableInfoInformation used to create a new PC table
 Cgem5::ruby::PendingWriteInst
 Cgem5::ruby::PerfectCacheLineState< ENTRY >
 Cgem5::ruby::PerfectCacheMemory< ENTRY >
 Cgem5::PerfKvmCounterAn instance of a performance counter
 Cgem5::PerfKvmCounterConfigPerfEvent counter configuration
 Cgem5::ruby::PersistentTable
 Cgem5::ruby::PersistentTableEntry
 Cgem5::o3::PhysRegFileSimple physical register file class
 ►Cgem5::PipeStageIFace
 Cgem5::PixelInternal gem5 representation of a Pixel
 Cgem5::PixelConverterConfigurable RGB pixel converter
 Cgem5::VncInput::PixelEncodingsMessage
 Cgem5::VncInput::PixelFormat
 Cgem5::VncInput::PixelFormatMessage
 Cgem5::PlicOutputNOTE: This implementation of PLIC is based on he riscv-plic-spec repository: https://github.com/riscv/riscv-plic-spec/releases/tag/1.0.0
 Cgem5::PM4QueueClass defining a PM4 queue
 CPMCAPDefines the Power Management capability register and all its associated bitfields for a PCIe device
 Cgem5::RiscvISA::PMP::PmpEntrySingle pmp entry struct
 ►Cgem5::ArmISA::PMU::PMUEventEvent definition base class
 Cgem5::PngWriter::PngPixel24Png Pixel type: not containing padding
 Cgem5::PngWriter::PngStructHandle
 Cgem5::VncInput::PointerEventMessage
 Cgem5::PollQueue
 ►Cgem5::PortPorts are used to interface objects to each other
 Csc_gem5::Port
 Cgem5::CxxConfigDirectoryEntry::PortDescSimilar to ParamDesc to describe ports
 Cgem5::o3::InstructionQueue::PqCompareStruct for comparing entries to be added to the priority queue
 Cgem5::PrdEntry_t
 Cgem5::PrdTableEntry
 Cgem5::branch_prediction::BPredUnit::PredictorHistory
 Cgem5::ruby::PrefetchEntry
 Cgem5::prefetch::Base::PrefetchInfoClass containing the information needed by the prefetch to train and generate new prefetch requests
 Cgem5::guest_abi::Preparer< ABI, Role, Type, Enabled >
 Cgem5::guest_abi::Preparer< ABI, Role, Type, decltype((void)&Role< ABI, Type >::prepare)>
 Cgem5::cp::Print
 ►Cgem5::PrintableAbstract base class for objects which support being printed to a stream for debugging
 Cgem5::stl_helpers::Printer< T >
 ►Cgem5::ProbeListenerProbeListener base class; here to simplify things like containers containing multiple types of ProbeListener
 Cgem5::ProbeManagerProbeManager is a conduit class that lives on each SimObject, and is used to match up probe listeners with probe points
 ►Cgem5::ProbePointProbeListener base class; again used to simplify use of ProbePoints in containers and used as to define interface for adding removing listeners to the ProbePoint
 Ctlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::process_handle_class
 Ctlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::process_handle_class
 Ctlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::process_handle_list
 Ctlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::process_handle_list
 ►Csc_gem5::ProcessFuncWrapper
 Cgem5::ProfileNode
 Cgem5::ruby::Profiler
 ►Cgem5::scmi::Protocol
 ►CProtoStreamA ProtoStream provides the shared functionality of the input and output streams
 Cgem5::ProxyPtr< void, Proxy >
 Cgem5::ProxyPtrBuffer< Proxy >
 Cgem5::ArmISA::PTE
 Cgem5::MipsISA::PTE
 Cgem5::PowerISA::PTE
 CPXCAPDefines the PCI Express capability register and its associated bitfields for a PCIe device
 Cgem5::PybindModuleInit
 Csc_gem5::PythonInitFunc
 Cgem5::QCntxt
 CQTIsaac< ALPHA >
 Cgem5::BaseRemoteGDB::QuerySetCommand
 Cgem5::minor::QueuedInstContainer class to box instructions in the FUs to make those queues have correct bubble behaviour when stepped
 ►Cgem5::memory::qos::QueuePolicyQoS Queue Policy
 CQTIsaac< ALPHA >::randctx
 Cgem5::TranslationGen::RangeThis structure represents a single, contiguous translation, or carries information about whatever fault might have happened while attempting it
 Cgem5::branch_prediction::ReturnAddrStack::RASHistory
 Cgem5::TraceCPU::ElasticDataGen::ReadyNodeStruct to store a ready-to-execute node and its execution tick
 ►Cgem5::RefCountedDerive from RefCounted if you want to enable reference counting of this class
 Cgem5::RefCountingPtr< T >If you want a reference counting pointer to a mutable object, create it like this:
 Cgem5::RefCountingPtr< DynInst >
 Cgem5::RefCountingPtr< MinorDynInst >
 Cgem5::RefCountingPtr< StaticInst >
 Cgem5::copy_engine_reg::Reg< T >
 Cgem5::igbreg::Regs::Reg< T >
 ►Cgem5::copy_engine_reg::Reg< uint16_t >
 ►Cgem5::copy_engine_reg::Reg< uint32_t >
 ►Cgem5::igbreg::Regs::Reg< uint32_t >
 ►Cgem5::copy_engine_reg::Reg< uint64_t >
 ►Cgem5::igbreg::Regs::Reg< uint64_t >
 ►Cgem5::copy_engine_reg::Reg< uint8_t >
 Cgem5::RegClass
 Cgem5::RegClassIterator
 ►Cgem5::RegClassOps
 ►Cgem5::trace::TarmacBaseRecord::RegEntryTARMAC register trace record
 Cgem5::RegFile
 ►Cgem5::RegIdRegister ID: describe an architectural register with its class and index
 Cgem5::prefetch::STeMS::RegionMissOrderBufferEntryData type of the Region Miss Order Buffer entry
 ►CRegister
 ►CTestRegBank::Register32
 Cgem5::RegisterBank< BankByteOrder >::RegisterAdder
 ►Cgem5::RegisterBankBase
 ►Cgem5::RegisterBank< ByteOrder::little >::RegisterBase
 ►Cgem5::RegisterBankBase::RegisterBaseBase
 ►Cgem5::RegisterManagerPolicyRegister Manager Policy abstract class
 Cgem5::RegisterOperandInfo
 Cgem5::FVPBasePwrCtrl::Registers
 Csc_gem5::remove_const< T >
 Csc_gem5::remove_const< const T >
 Csc_gem5::remove_special_fptr< T >
 Csc_gem5::remove_special_fptr< special_result &(*)(T)>
 Cgem5::o3::RenameRename handles both single threaded and SMT rename
 Cgem5::o3::TimeStruct::RenameComm
 Cgem5::o3::Rename::RenameHistoryHolds the information for each destination register rename
 Cgem5::o3::RenameStructStruct that defines the information passed from rename to IEW
 Cgem5::CxxConfigManager::RenamingName substitution when instantiating any object whose name starts with fromPrefix
 ►Cgem5::compression::DictionaryCompressor< uint32_t >::RepeatedValuePattern
 ►Cgem5::ReplaceableEntryA replaceable entry is a basic entry in a 2d table-like structure that needs to have replacement functionality
 ►Cgem5::replacement_policy::ReplacementDataThe replacement data needed by replacement policies
 Cgem5::minor::ReportIFInterface class for data with reporting/tracing facilities
 Csc_gem5::ReportMsgInfo
 Csc_gem5::ReportSevInfo
 Cgem5::minor::ReportTraitsAdaptor< ElemType >...ReportTraits are trait classes with the same functionality as ReportIF, but with elements explicitly passed into the report... functions
 Cgem5::minor::ReportTraitsPtrAdaptor< PtrType >A similar adaptor but for elements held by pointer ElemType should implement ReportIF
 Cgem5::SnoopFilter::ReqLookupResultA request lookup must be followed by a call to finishRequest to inform the operation's success
 Cgem5::UFSHostDevice::UTPTransferReqDesc::RequestDescHeaderStruct RequestDescHeader dword0: Descriptor Header DW0 dword1: Descriptor Header DW1 dword2: Descriptor Header DW2 dword3: Descriptor Header DW3
 Cgem5::RequestorInfoData about a specific requestor
 Cgem5::AMDGPUMemoryManager::RequestStatus
 ►Cgem5::minor::ReservableBase class for space reservation requestable objects
 Csc_core::sc_spawn_options::Reset< T >
 Csc_gem5::Reset
 Csc_core::sc_spawn_options::Reset< const sc_core::sc_in< bool > >
 Csc_core::sc_spawn_options::Reset< const sc_core::sc_inout< bool > >
 Csc_core::sc_spawn_options::Reset< const sc_core::sc_out< bool > >
 Csc_core::sc_spawn_options::Reset< const sc_core::sc_signal_in_if< bool > >
 Cgem5::guest_abi::Result< ABI, Ret, Enabled >
 ►Cgem5::guest_abi::Result< Aapcs32, Composite >
 Cgem5::guest_abi::Result< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >
 Cgem5::guest_abi::Result< Aapcs32, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >
 ►Cgem5::guest_abi::Result< Aapcs32, Integer >
 Cgem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)< sizeof(uint32_t))> >
 Cgem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)==sizeof(uint32_t))> >
 Cgem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)==sizeof(uint64_t))> >
 Cgem5::guest_abi::Result< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >
 Cgem5::guest_abi::Result< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >
 Cgem5::guest_abi::Result< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >
 Cgem5::guest_abi::Result< Aapcs64, Float, typename std::enable_if_t< std::is_floating_point_v< Float >||IsAapcs64ShortVectorV< Float > > >
 Cgem5::guest_abi::Result< Aapcs64, HA, typename std::enable_if_t< IsAapcs64HxaV< HA > > >
 Cgem5::guest_abi::Result< Aapcs64, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer) > 8)> >
 Cgem5::guest_abi::Result< Aapcs64, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)<=8)> >
 Cgem5::guest_abi::Result< Abi, RiscvSemihosting::RetErrno >
 Cgem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< ArmISA::EmuFreebsd::BaseSyscallABI, ABI > > >
 Cgem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< ArmISA::EmuLinux::BaseSyscallABI, ABI > > >
 Cgem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< SparcISA::SEWorkload::BaseSyscallABI, ABI > > >
 Cgem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< X86Linux::SyscallABI, ABI > > >
 Cgem5::guest_abi::Result< ABI, void >
 Cgem5::guest_abi::Result< ArmSemihosting::Abi32, ArmSemihosting::RetErrno >
 Cgem5::guest_abi::Result< ArmSemihosting::Abi64, ArmSemihosting::RetErrno >
 Cgem5::guest_abi::Result< MipsISA::SEWorkload::SyscallABI, SyscallReturn >
 Cgem5::guest_abi::Result< PowerISA::SEWorkload::SyscallABI, SyscallReturn >
 Cgem5::guest_abi::Result< RiscvISA::SEWorkload::SyscallABI32, SyscallReturn >
 Cgem5::guest_abi::Result< RiscvISA::SEWorkload::SyscallABI64, SyscallReturn >
 Cgem5::guest_abi::Result< SparcPseudoInstABI, T >
 Cgem5::guest_abi::Result< TestABI_1D, int >
 Cgem5::guest_abi::Result< TestABI_1D, Ret, typename std::enable_if_t< std::is_floating_point_v< Ret > > >
 Cgem5::guest_abi::Result< TestABI_2D, int >
 Cgem5::guest_abi::Result< TestABI_2D, Ret, typename std::enable_if_t< std::is_floating_point_v< Ret > > >
 Cgem5::guest_abi::Result< TestABI_Prepare, Ret >
 Cgem5::guest_abi::Result< X86PseudoInstABI, T >
 Cgem5::guest_abi::ResultStorer< ABI, Ret, Enabled >
 Cgem5::guest_abi::ResultStorer< ABI, Ret, typename std::enable_if_t< std::is_same_v< void(*)(ThreadContext *, const Ret &, typename ABI::State &), decltype(&Result< ABI, Ret >::store)> > >
 Crgb_t
 Cgem5::ArmFreebsd32::rlimitLimit struct for getrlimit/setrlimit
 Cgem5::ArmFreebsd64::rlimitLimit struct for getrlimit/setrlimit
 Cgem5::ArmLinux32::rlimitLimit struct for getrlimit/setrlimit
 Cgem5::ArmLinux64::rlimitLimit struct for getrlimit/setrlimit
 Cgem5::Linux::rlimitLimit struct for getrlimit/setrlimit
 Cgem5::OperatingSystem::rlimitLimit struct for getrlimit/setrlimit
 Cgem5::RiscvLinux32::rlimitLimit struct for getrlimit/setrlimit
 Cgem5::o3::ROBROB class
 Cgem5::ruby::BaseRoutingUnit::RouteInfo
 Cgem5::ruby::garnet::RouteInfo
 Cgem5::ruby::garnet::RoutingUnit
 Cgem5::HSAPacketProcessor::RQLEntry
 Cgem5::ArmFreebsd32::rusageFor getrusage()
 Cgem5::ArmFreebsd64::rusageFor getrusage()
 Cgem5::ArmLinux32::rusageFor getrusage()
 Cgem5::ArmLinux64::rusageFor getrusage()
 Cgem5::Linux::rusage
 Cgem5::OperatingSystem::rusageFor getrusage()
 Cgem5::igbreg::RxDesc
 Cgem5::statistics::SampleStorTemplatized storage and interface for a distribution that calculates mean and variance
 Cgem5::prefetch::SBOOE::Sandbox
 Cgem5::prefetch::SBOOE::SandboxEntry
 ►Csc_core::sc_attr_base
 Csc_core::sc_attr_cltn
 Csc_dp::sc_barrier
 Csc_core::sc_bind_proxy
 Csc_dt::sc_bit
 ►Csc_dt::sc_bitref_conv_r< T, Traits >
 Csc_dt::sc_bitref_conv_r< T, sc_proxy_traits< sc_bv_base > >
 Csc_core::sc_byte_heap
 Csc_dt::sc_context< T >
 Csc_core::sc_curr_proc_info
 ►Csc_core::sc_direct_access< Element >
 ►Csc_core::sc_event
 Csc_core::sc_event_and_expr
 Csc_core::sc_event_and_list
 ►Csc_core::sc_event_finder
 Csc_core::sc_event_or_expr
 Csc_core::sc_event_or_list
 Csc_dt::sc_fxcast_switch
 ►Csc_dt::sc_fxnum
 Csc_dt::sc_fxnum_bitref
 ►Csc_dt::sc_fxnum_fast
 Csc_dt::sc_fxnum_fast_bitref
 Csc_dt::sc_fxnum_fast_observer
 Csc_dt::sc_fxnum_fast_subref
 Csc_dt::sc_fxnum_observer
 Csc_dt::sc_fxnum_subref
 Csc_dt::sc_fxtype_params
 Csc_dt::sc_fxval
 Csc_dt::sc_fxval_fast
 Csc_dt::sc_fxval_fast_observer
 Csc_dt::sc_fxval_observer
 Csc_dt::sc_generic_base< T >
 ►Csc_dt::sc_generic_base< sc_concatref >
 Csc_dt::sc_global< T >
 ►Csc_core::sc_interface
 Csc_core::sc_join
 Csc_dt::sc_length_param
 Csc_dt::sc_logic
 Csc_core::sc_member_access< Element, Access >
 Csc_core::sc_mempool
 ►Csc_module
 Csc_core::sc_module_name
 Csc_core::sc_mpobject
 ►Csc_core::sc_object
 Csc_core::sc_process_handle
 Csc_dt::sc_proxy< X >
 ►Csc_dt::sc_proxy< sc_bv_base >
 ►Csc_dt::sc_proxy< sc_concref_r< X, Y > >
 ►Csc_dt::sc_proxy< sc_lv_base >
 ►Csc_dt::sc_proxy< sc_subref_r< X > >
 ►Csc_dt::sc_proxy_traits< X >
 Csc_dt::sc_proxy_traits< sc_bv_base >
 ►Csc_dt::sc_proxy_traits< sc_lv_base >
 Csc_core::sc_report_handler
 Csc_core::sc_sensitive
 Csc_core::sc_simcontext
 Csc_core::sc_spawn_options
 Csc_core::sc_time
 Csc_core::sc_time_tuple
 ►Csc_core::sc_trace_file
 Csc_core::sc_trace_params
 Csc_core::sc_user
 ►Csc_dt::sc_value_base
 Csc_core::sc_vector_assembly< T, MT >
 Csc_core::sc_vpool< T >
 Csc_core::sc_vpool< sc_core::sc_int_sigref >
 Csc_core::sc_vpool< sc_core::sc_signed_sigref >
 Csc_core::sc_vpool< sc_core::sc_uint_sigref >
 Csc_core::sc_vpool< sc_core::sc_unsigned_sigref >
 Csc_core::sc_vpool< sc_dt::sc_concat_bool >
 Csc_core::sc_vpool< sc_dt::sc_concatref >
 Csc_core::sc_vpool< sc_dt::sc_int_bitref >
 Csc_core::sc_vpool< sc_dt::sc_int_subref >
 Csc_core::sc_vpool< sc_dt::sc_signed_bitref >
 Csc_core::sc_vpool< sc_dt::sc_signed_subref >
 Csc_core::sc_vpool< sc_dt::sc_uint_bitref >
 Csc_core::sc_vpool< sc_dt::sc_uint_subref >
 Csc_core::sc_vpool< sc_dt::sc_unsigned >
 Csc_core::sc_vpool< sc_dt::sc_unsigned_bitref >
 Csc_core::sc_vpool< sc_dt::sc_unsigned_subref >
 Csc_dt::sc_without_context
 Cgem5::ScalarMemPipeline
 Cgem5::statistics::ScalarProxy< Stat >A proxy class to access the stat at a given index in a VectorBase stat
 ►Csc_gem5::ScEvent
 Csc_dt::scfx_ieee_double
 Csc_dt::scfx_ieee_float
 Csc_dt::scfx_index
 Csc_dt::scfx_mant
 Csc_dt::scfx_mant_ref
 Csc_dt::scfx_params
 Csc_dt::scfx_pow10
 Csc_dt::scfx_rep
 Csc_dt::scfx_rep_node
 Csc_dt::scfx_string
 Csc_gem5::ScHalt
 Cgem5::Scheduler
 Csc_gem5::Scheduler
 Cgem5::ScheduleStage
 ►Cgem5::SchedulingPolicyInterface class for the wave scheduling policy
 Cgem5::Serializable::ScopedCheckpointSection
 Cgem5::EventQueue::ScopedMigration
 Cgem5::EventQueue::ScopedRelease
 Cgem5::o3::ScoreboardImplements a simple scoreboard to track which registers are ready
 Cgem5::ScoreboardCheckStage
 Cgem5::UFSHostDevice::SCSIReplySCSI reply structure
 Cgem5::UFSHostDevice::SCSIResumeInfoAfter a SCSI command has been identified, the SCSI resume function will handle it
 ►Cgem5::branch_prediction::StatisticalCorrector::SCThreadHistory
 ►Cscx_evs_GIC
 ►Cscx_evs_PL330
 Cgem5::fastmodel::ScxEvsCortexA76x1Types
 Cgem5::fastmodel::ScxEvsCortexA76x2Types
 Cgem5::fastmodel::ScxEvsCortexA76x3Types
 Cgem5::fastmodel::ScxEvsCortexA76x4Types
 Cgem5::fastmodel::ScxEvsCortexR52x1Types
 Cgem5::fastmodel::ScxEvsCortexR52x2Types
 Cgem5::fastmodel::ScxEvsCortexR52x3Types
 Cgem5::fastmodel::ScxEvsCortexR52x4Types
 Cgem5::SDMAEngine::SDMAQueue
 Cgem5::IniFile::SectionA section
 Cgem5::CowDiskImage::Sector
 Cgem5::X86ISA::SegDescriptorLimit
 Cgem5::loader::MemoryImage::Segment
 Cgem5::X86ISA::SegRegIndex
 Csc_core::sc_vector_iter< Element, AccessPolicy >::SelectIter< U >
 Csc_core::sc_vector_iter< Element, AccessPolicy >::SelectIter< const U >
 Csc_core::sc_vector_iter< Element, AccessPolicy >::SelectIter< ElementType >
 Cgem5::ArmISA::SelfDebug
 Cgem5::BaseSemihosting::SemiCallBase< Semihosting, Abi32, Abi64 >Semihosting call information structure
 ►Cgem5::Packet::SenderStateA virtual base opaque structure used to hold state associated with the packet (e.g., an MSHR), specific to a SimObject that sees the packet
 Csc_gem5::Port::Sensitivity
 ►Csc_gem5::Sensitivity
 Cgem5::prefetch::STeMS::ActiveGenerationTableEntry::SequenceEntrySequence entry data type
 Cgem5::ruby::SequencerRequest
 ►Cgem5::SerializableBasic support for object serialization
 Cgem5::VncServer::ServerCutText
 Cgem5::VncServer::ServerInitMsg
 Cgem5::ruby::Set
 Cgem5::ShowParam< T, Enabled >
 Cgem5::ShowParam< BitUnionType< T > >
 Cgem5::ShowParam< bool >
 Cgem5::ShowParam< MatStore< X, Y > >
 Cgem5::ShowParam< T, std::enable_if_t< std::is_base_of_v< typename RegisterBankBase::RegisterBaseBase, T > > >
 Cgem5::ShowParam< T, std::enable_if_t< std::is_same_v< char, T >||std::is_same_v< unsigned char, T >||std::is_same_v< signed char, T > > >
 Cgem5::ShowParam< VecPredRegContainer< NumBits, Packed > >
 Cgem5::ShowParam< VecRegContainer< Sz > >
 ►Camba_pv::signal_slave_base
 Cgem5::SignalInterruptDummyProtocolType
 Cgem5::HSAPacketProcessor::SignalState
 Cgem5::bitfield_backend::Signed< Storage, first, last >
 ►Cgem5::compression::DictionaryCompressor< uint32_t >::SignExtendedPattern
 ►CTypes::SimGic
 ►Cgem5::SimObjectResolverBase class to wrap object resolving functionality
 CSimpleAddressMapSimple address map implementation for the generic protocol
 Cgem5::o3::SimpleFreeListFree list for a single class of registers (e.g., integer or floating point)
 Cgem5::o3::SimpleRenameMapRegister rename map for a single class of registers (e.g., integer or floating point)
 Cgem5::SimulatorThreads
 Cgem5::X86ISA::smbios::SMBiosTable::SMBiosHeader
 Cgem5::SMMUAction
 Cgem5::SMMUCommand
 Cgem5::SMMUEvent
 Cgem5::SMMUSemaphore
 Cgem5::SMMUSignal
 Cgem5::SMMUTranslRequest
 ►Cgem5::SMMUv3BaseCache
 Cgem5::SNHash
 Cgem5::SnoopFilter::SnoopItemPer cache line item tracking a bitmask of ResponsePorts who have an outstanding request to this line (requested) or already share a cache line with this address (holder)
 Cgem5::ArmISA::SoftwareStep
 Cgem5::SparcPseudoInstABI
 Cgem5::statistics::SparseHistDataData structure of sparse histogram
 Cgem5::statistics::SparseHistStorTemplatized storage and interface for a sparse histogram stat
 Cgem5::SpatterKernel
 Csc_gem5::special_result
 Cgem5::X86ISA::Src1Op
 Cgem5::X86ISA::Src2Op
 Cgem5::X86ISA::Src3Op
 Cgem5::SSTResponderInterface
 Cstack_el
 Cgem5::StackDistCalcThe stack distance calculator is a passive object that merely observes the addresses pass to it
 Cgem5::o3::Decode::StallsSource of possible stalls
 Cgem5::o3::Fetch::StallsSource of possible stalls
 Cgem5::o3::Rename::StallsSource of possible stalls
 ►Cgem5::Aapcs32::State
 Cgem5::Aapcs64::State
 CTestABI_TcInit::State
 ►Cgem5::BaseSemihosting::AbiBase::StateBase< Arg, BaseSemihostingImpl >
 Cgem5::guest_abi::StateInitializer< ABI, Enabled >
 Cgem5::guest_abi::StateInitializer< ABI, typename std::enable_if_t< std::is_constructible_v< typename ABI::State, const ThreadContext * > > >
 ►CStaticInstFlags
 Cgem5::statistics::StatStorTemplatized storage and interface for a simple scalar stat
 Cgem5::VegaISA::StatusReg
 ►Cgem5::statistics::StorageParams
 Cgem5::o3::StoreSetImplements a store set predictor for determining if memory instructions are dependent upon each other
 Cgem5::ruby::StoreTrace
 ►Cgem5::StreamGen
 Cgem5::StreamTableEntry
 Cgem5::StringWrap
 Cgem5::ruby::SubBlock
 Cgem5::EtherSwitch::SwitchTableEntry
 Cgem5::loader::Symbol
 Cgem5::loader::SymbolTable
 ►Cgem5::X86Linux::SyscallABI
 ►Cgem5::SyscallDescThis class provides the wrapper interface for the system call implementations which are defined in the sim/syscall_emul files and bound to the ISAs in the architecture specific code (i.e
 Cgem5::SyscallDescTable< ABI >
 ►Cgem5::SyscallDescTable< EmuLinux::SyscallABI32 >
 ►Cgem5::SyscallDescTable< EmuLinux::SyscallABI64 >
 Cgem5::SyscallDescTable< gem5::PowerISA::SEWorkload::SyscallABI >
 Cgem5::SyscallDescTable< gem5::RiscvISA::RegABI32 >
 Cgem5::SyscallDescTable< gem5::RiscvISA::RegABI64 >
 Cgem5::SyscallDescTable< gem5::SparcISA::SEWorkload::SyscallABI32 >
 Cgem5::SyscallDescTable< gem5::SparcISA::SEWorkload::SyscallABI64 >
 Cgem5::SyscallDescTable< gem5::X86ISA::EmuLinux::SyscallABI32 >
 Cgem5::SyscallDescTable< gem5::X86ISA::EmuLinux::SyscallABI64 >
 Cgem5::SyscallDescTable< SyscallABI >
 Cgem5::SyscallReturnThis class represents the return value from an emulated system call, including any errno setting
 Cgem5::ruby::FaultModel::system_conf
 ►Cgem5::SystemCounterListenerAbstract class for elements whose events depend on the counting speed of the System Counter
 Cgem5::BitfieldTypeImpl< Base >::TypeDeducer::T< typename >
 Cgem5::BitfieldTypeImpl< Base >::TypeDeducer::T< void(C::*)(Type1 &, Type2)>
 ►Cgem5::branch_prediction::TAGE::TageBranchInfo
 Cgem5::branch_prediction::TAGEBase::TageEntry
 Cgem5::TapListener
 ►Cgem5::QueueEntry::TargetA queue entry is holding packets that will be serviced as soon as resources are available
 Cgem5::trace::TarmacContextThis object type is encapsulating the informations needed by a Tarmac record to generate it's own entries
 Cgem5::UFSHostDevice::taskStartTask start information
 Cgem5::ruby::TBEStorage
 Cgem5::ruby::TBETable< ENTRY >
 ►Cgem5::ruby::TBETable< MiscNode_TBE >
 ►Ctcp_hdr
 ►Ctcp_opt
 Cgem5::networking::TcpPtr
 Cgem5::statistics::TempHelper class to construct formula node trees
 Cgem5::TemperatureThe class stores temperatures in Kelvin and provides helper methods to convert to/from Celsius
 ►CDictionaryCompressor::template DeltaPattern
 ►Ctesting::Test
 CTestABI
 CTestABI_1D
 CTestABI_2D
 CTestABI_Prepare
 CTestABI_TcInit
 CTestProxy
 ►Ctesting::TestWithParam
 Cgem5::X86Linux64::tgt_clone_args
 Cgem5::X86Linux64::tgt_fsid
 Cgem5::RiscvLinux32::tgt_fsid_t
 Cgem5::RiscvLinux64::tgt_fsid_t
 Cgem5::ArmFreebsd32::tgt_iovec
 Cgem5::ArmFreebsd64::tgt_iovec
 Cgem5::ArmLinux32::tgt_iovec
 Cgem5::ArmLinux64::tgt_iovec
 Cgem5::Linux::tgt_iovec
 Cgem5::OperatingSystem::tgt_iovec
 Cgem5::X86Linux64::tgt_iovec
 Cgem5::ArmFreebsd32::tgt_stat
 Cgem5::ArmFreebsd64::tgt_stat
 Cgem5::ArmLinux32::tgt_stat
 Cgem5::ArmLinux64::tgt_stat
 Cgem5::Linux::tgt_statStat buffer
 Cgem5::PowerLinux::tgt_stat
 Cgem5::RiscvLinux32::tgt_stat
 Cgem5::Solaris::tgt_statStat buffer
 Cgem5::SparcLinux::tgt_stat
 Cgem5::ArmFreebsd32::tgt_stat64
 Cgem5::ArmFreebsd64::tgt_stat64
 Cgem5::ArmLinux32::tgt_stat64
 Cgem5::ArmLinux64::tgt_stat64
 Cgem5::Linux::tgt_stat64
 Cgem5::PowerLinux::tgt_stat64
 Cgem5::RiscvLinux64::tgt_stat64
 Cgem5::Solaris::tgt_stat64
 Cgem5::Sparc32Linux::tgt_stat64
 Cgem5::SparcLinux::tgt_stat64
 Cgem5::X86Linux32::tgt_stat64
 Cgem5::X86Linux64::tgt_stat64
 Cgem5::RiscvLinux32::tgt_statfs
 Cgem5::RiscvLinux64::tgt_statfs
 Cgem5::X86Linux64::tgt_statfs
 Cgem5::X86Linux64::tgt_statx
 Cgem5::ArmLinux32::tgt_sysinfo
 Cgem5::ArmLinux64::tgt_sysinfo
 Cgem5::MipsLinux::tgt_sysinfo
 Cgem5::RiscvLinux32::tgt_sysinfo
 Cgem5::RiscvLinux64::tgt_sysinfo
 Cgem5::Sparc32Linux::tgt_sysinfo
 Cgem5::SparcLinux::tgt_sysinfo
 Cgem5::X86Linux32::tgt_sysinfo
 Cgem5::X86Linux64::tgt_sysinfo
 Cgem5::Solaris::tgt_timespec
 ►Cgem5::ThermalEntityAn abstract class that represents any thermal entity which is used in the circuital thermal equivalent model
 Cgem5::System::Threads::Thread
 Cgem5::linux::thread_info
 Cgem5::branch_prediction::MultiperspectivePerceptron::ThreadDataHistory data is kept for each thread
 Cgem5::branch_prediction::TAGEBase::ThreadHistory
 Cgem5::branch_prediction::SimpleIndirectPredictor::ThreadInfoPer thread path and global history registers
 Cgem5::free_bsd::ThreadInfo
 Cgem5::linux::ThreadInfo
 Cgem5::System::Threads
 Cgem5::trace::ArmNativeTrace::ThreadState
 Cgem5::trace::X86NativeTrace::ThreadState
 Cgem5::Tile< ElemType, Container >Provides a view of a matrix that is row-interleaved onto a MatStore
 Cgem5::Time
 Ctlm_utils::time_ordered_list< PAYLOAD >
 Ctlm_utils::time_ordered_list< std::pair >
 Cgem5::TimeBuffer< T >
 Cgem5::TimeBuffer< bool >
 ►Cgem5::TimeBuffer< Data >
 ►Cgem5::TimeBuffer< ElemType >
 ►Cgem5::TimeBuffer< gem5::minor::BranchData >
 ►Cgem5::TimeBuffer< gem5::minor::ForwardInstData >
 ►Cgem5::TimeBuffer< gem5::minor::ForwardLineData >
 Cgem5::TimeBuffer< gem5::o3::DecodeStruct >
 Cgem5::TimeBuffer< gem5::o3::FetchStruct >
 Cgem5::TimeBuffer< gem5::o3::IEWStruct >
 Cgem5::TimeBuffer< gem5::o3::IssueStruct >
 Cgem5::TimeBuffer< gem5::o3::RenameStruct >
 Cgem5::TimeBuffer< gem5::o3::TimeStruct >
 Cgem5::TimedQueue< T >
 Cgem5::TimedQueue< gem5::Packet >
 Cgem5::TimedQueue< gem5::SpatterAccess * >
 Cgem5::ruby::TimerTable
 Cgem5::ArmLinux32::timespec
 Cgem5::ArmLinux64::timespec
 Cgem5::Linux::timespecFor clock_gettime()
 Cgem5::RiscvLinux32::timespec
 Cgem5::RiscvLinux64::timespec
 Cgem5::o3::TimeStructStruct that defines all backwards communication
 Cgem5::ArmFreebsd32::timevalFor gettimeofday()
 Cgem5::ArmFreebsd64::timevalFor gettimeofday()
 Cgem5::ArmLinux32::timevalFor gettimeofday()
 Cgem5::ArmLinux64::timevalFor gettimeofday()
 Cgem5::Linux::timevalFor gettimeofday()
 Cgem5::OperatingSystem::timevalFor gettimeofday()
 Cgem5::TimingExprEvalContextObject to gather the visible context for evaluation
 ►Cgem5::TimingRequestProtocol
 ►Cgem5::TimingResponseProtocol
 Cgem5::MipsISA::TlbEntry
 Cgem5::PowerISA::TlbEntry
 Cgem5::SparcISA::TlbEntry
 ►Cgem5::ArmISA::TLBIOp
 ►Cgem5::ArmISA::TLBIRange
 Cgem5::SparcISA::TlbMap
 Cgem5::SparcISA::TlbRange
 Cgem5::ArmISA::TlbTestInterface
 Ctlm::tlm_analysis_triple< T >
 ►Ctlm::tlm_base_initiator_socket_b< BUSWIDTH, FW_IF, BW_IF >
 ►Ctlm::tlm_base_initiator_socket_b< BUSWIDTH, ClockRateControlFwIf, ClockRateControlBwIf >
 ►Ctlm::tlm_base_initiator_socket_b< BUSWIDTH, SignalInterruptFwIf, SignalInterruptBwIf >
 ►Ctlm::tlm_base_initiator_socket_b< BUSWIDTH, tlm_fw_transport_if< my_extended_payload_types >, tlm_bw_transport_if< my_extended_payload_types > >
 ►Ctlm::tlm_base_initiator_socket_b< BUSWIDTH, tlm_fw_transport_if< tlm::tlm_base_protocol_types >, tlm_bw_transport_if< tlm::tlm_base_protocol_types > >
 ►Ctlm::tlm_base_initiator_socket_b< BUSWIDTH, tlm_fw_transport_if< tlm_base_protocol_types >, tlm_bw_transport_if< tlm_base_protocol_types > >
 ►Ctlm::tlm_base_initiator_socket_b< BUSWIDTH, tlm_fw_transport_if< TYPES >, tlm_bw_transport_if< TYPES > >
 Ctlm::tlm_base_protocol_types
 ►Ctlm::tlm_base_socket_if
 Ctlm::tlm_base_target_socket_b< BUSWIDTH, FW_IF, BW_IF >
 ►Ctlm::tlm_base_target_socket_b< 32, tlm_fw_transport_if<>, tlm_bw_transport_if<> >
 ►Ctlm::tlm_base_target_socket_b< BUSWIDTH, ClockRateControlFwIf, ClockRateControlBwIf >
 ►Ctlm::tlm_base_target_socket_b< BUSWIDTH, SignalInterruptFwIf, SignalInterruptBwIf >
 ►Ctlm::tlm_base_target_socket_b< BUSWIDTH, tlm_fw_transport_if< my_extended_payload_types >, tlm_bw_transport_if< my_extended_payload_types > >
 ►Ctlm::tlm_base_target_socket_b< BUSWIDTH, tlm_fw_transport_if< tlm::tlm_base_protocol_types >, tlm_bw_transport_if< tlm::tlm_base_protocol_types > >
 ►Ctlm::tlm_base_target_socket_b< BUSWIDTH, tlm_fw_transport_if< tlm_base_protocol_types >, tlm_bw_transport_if< tlm_base_protocol_types > >
 ►Ctlm::tlm_base_target_socket_b< BUSWIDTH, tlm_fw_transport_if< TYPES >, tlm_bw_transport_if< TYPES > >
 Ctlm::tlm_bool< D >
 Ctlm::tlm_dmi
 Ctlm::tlm_endian_context_pool
 ►Ctlm::tlm_extension_base
 ►Ctlm::tlm_generic_payload
 Ctlm::tlm_global_quantum
 ►Ctlm::tlm_mm_interface
 Ctlm::tlm_phase
 Ctlm_utils::tlm_quantumkeeper
 Ctlm::tlm_tag< T >
 Cgem5::ArmFreebsd32::tmsFor times()
 Cgem5::ArmFreebsd64::tmsFor times()
 Cgem5::ArmLinux32::tmsFor times()
 Cgem5::ArmLinux64::tmsFor times()
 Cgem5::Linux::tmsFor times()
 Cgem5::PowerLinux::tmsFor times()
 Cgem5::TokenManager
 Cgem5::ruby::Topology
 Cgem5::TraceCPU::FixedRetryGen::TraceElementThis struct stores a line in the trace file
 Cgem5::TraceGen::TraceElementThis struct stores a line in the trace file
 ►Cgem5::trace::TarmacTracerRecordV8::TraceEntryV8General data shared by all v8 entries
 Cgem5::o3::ElasticTrace::TraceInfo
 Cgem5::ruby::TraceRecordClass for recording cache contents
 ►Csc_gem5::TraceValBase
 Cgem5::MemChecker::TransactionCaptures the lifetimes of read and write operations, and the values they consumed or produced respectively
 Cgem5::UFSHostDevice::transferDoneInfoTransfer completion info
 Cgem5::UFSHostDevice::transferInfoDifferent events, and scenarios require different types of information
 Cgem5::UFSHostDevice::transferStartTransfer start information
 Cgem5::TrafficGen::TransitionStruct to represent a probabilistic transition during parsing
 ►Cgem5::BaseMMU::Translation
 Cgem5::VegaISA::GpuTLB::Translation
 Cgem5::X86ISA::GpuTLB::Translation
 ►Cgem5::TranslationGenTranslationGen is a base class for a generator object which returns information about address translations over a range of virtual addresses
 Cgem5::TranslationGenConstIteratorAn iterator for pulling "Range" instances out of a TranslationGen
 Cgem5::SMMUTranslationProcess::TranslContext
 Cgem5::SMMUTranslationProcess::TranslResult
 Cgem5::ruby::AbstractController::TransMapPair
 Cgem5::Trie< Key, Value >A trie is a tree-based data structure used for data retrieval
 Cgem5::Trie< Addr, TlbEntry >
 Cgem5::Trie< Addr, uint32_t >
 Cgem5::ruby::TriggerQueue< T >
 ►Cstd::true_type
 Cgem5::SparcISA::TteTag
 Cgem5::igbreg::TxDesc
 Cgem5::BitfieldTypeImpl< Base >::TypeDeducer
 ►Cudp_hdr
 Cgem5::networking::UdpPtr
 Cgem5::UFSHostDevice::UFSHCDSGEntryStruct UFSHCDSGEntry - UFSHCI PRD Entry baseAddr: Lower 32bit physical address DW-0 upperAddr: Upper 32bit physical address DW-1 reserved: Reserved for future use DW-2 size: size of physical segment DW-3
 Cgem5::Port::UnboundPortException
 Cgem5::ruby::UncoalescedTable
 ►Cgem5::compression::DictionaryCompressor< uint32_t >::UncompressedPattern
 Cgem5::UncontendedMutex
 Cgem5::o3::UnifiedFreeListFreeList class that simply holds the list of free integer and floating point registers
 Cgem5::o3::UnifiedRenameMapUnified register rename map for all classes of registers
 Csc_gem5::UniqueNameGen
 ►Cgem5::ruby::RubyPrefetcher::UnitFilterEntry
 ►Cstd::unordered_map
 ►Cstd::unordered_set
 Cgem5::bitfield_backend::Unsigned< Storage, first, last >
 Cgem5::X86ISA::UpcOp
 Cgem5::UFSHostDevice::UPIUMessageUPIU tranfer message
 Cgem5::UFSHostDevice::UTPTransferCMDDescStruct UTPTransferCMDDesc - UFS Commad Descriptor structure commandUPIU: Command UPIU Frame address responseUPIU: Response UPIU Frame address PRDTable: Physcial Region Descriptor All lengths as defined by JEDEC220
 Cgem5::UFSHostDevice::UTPTransferReqDescStruct UTPTransferReqDesc - UTRD structure header: UTRD header DW-0 to DW-3 commandDescBaseAddrLo: UCD base address low DW-4 commandDescBaseAddrHi: UCD base address high DW-5 responseUPIULength: response UPIU length DW-6 responseUPIUOffset: response UPIU offset DW-6 PRDTableLength: Physical region descriptor length DW-7 PRDTableOffset: Physical region descriptor offset DW-7
 Cgem5::UFSHostDevice::UTPUPIUHeaderAll the data structures are defined in the UFS standard This standard be found at the JEDEC website free of charge (login required): http://www.jedec.org/standards-documents/results/jesd220
 Cgem5::UFSHostDevice::UTPUPIURSPStruct UTPUPIURSP - Response UPIU structure header: UPIU header DW-0 to DW-2 residualTransferCount: Residual transfer count DW-3 reserved: Reserved DW-4 to DW-7 senseDataLen: Sense data length DW-8 U16 senseData: Sense data field DW-8 to DW-12
 Cgem5::UFSHostDevice::UTPUPIUTaskReqStruct UTPUPIUTaskReq - Task request UPIU structure header - UPIU header structure DW0 to DW-2 inputParam1: Input param 1 DW-3 inputParam2: Input param 2 DW-4 inputParam3: Input param 3 DW-5 reserved: Reserver DW-6 to DW-7
 Cgem5::Linux::utsnameInterface struct for uname()
 Cgem5::OperatingSystem::utsnameInterface struct for uname()
 Cgem5::Solaris::utsnameInterface struct for uname()
 Cgem5::ruby::TriggerQueue< T >::ValType
 CValueSamplesA pair of value and its number of samples, used for sampling
 Cgem5::guest_abi::VarArgs< Types >
 Cgem5::guest_abi::VarArgsBase< Types >
 ►Cgem5::guest_abi::VarArgsBase< Types... >
 Cgem5::guest_abi::VarArgsBase<>
 Cgem5::guest_abi::VarArgsImpl< ABI, Base, Types >
 ►Cgem5::guest_abi::VarArgsImpl< ABI, Base, Types... >
 Csc_gem5::VcdTraceScope
 Cgem5::VecPredRegContainer< NumBits, Packed >Generic predicate register container
 Cgem5::VecPredRegContainer< size, T >
 Cgem5::VecPredRegT< VecElem, NumElems, Packed, Const >Predicate register view
 Cgem5::VecRegContainer< SIZE >Vector Register Abstraction This generic class is the model in a particularization of MVC, to vector registers
 Cgem5::VecRegContainer< 16 >
 Cgem5::VecRegContainer< sizeof(DataType) *NumVecElemPerVecReg >
 ►Cstd::vector< T >STL vector class
 Cstd::vector< Access >
 Cstd::vector< AccessMapState >
 Cstd::vector< Action * >
 Cstd::vector< Addr >
 Cstd::vector< ArmISA::VecPredRegContainer >
 Cstd::vector< AtomicStruct * >
 Cstd::vector< Bank >
 Cstd::vector< BankType >
 Cstd::vector< BASER >
 Cstd::vector< bool >
 Cstd::vector< BpId >
 Cstd::vector< bw_interface_type * >
 Cstd::vector< char * >
 Cstd::vector< char >
 Cstd::vector< Chunk >
 Cstd::vector< class gem5::HSAPacketProcessor::RQLEntry * >
 Cstd::vector< ClockRateControlFwIf * >
 Cstd::vector< CompactorEntry >
 Cstd::vector< const char * >
 Cstd::vector< const RegClass * >
 Cstd::vector< const sc_core::sc_event * >
 Cstd::vector< ContextID >
 Cstd::vector< Counter >
 Cstd::vector< DictionaryEntry >
 Cstd::vector< DISPATCH_STATUS >
 Cstd::vector< DmaDoneEvent * >
 Cstd::vector< DmaDoneEvent >
 Cstd::vector< DomainID >
 Cstd::vector< double >
 Cstd::vector< DynamicSensitivity * >
 Cstd::vector< Entry >
 Cstd::vector< Episode * >
 Cstd::vector< Fault >
 Cstd::vector< FW_IF * >
 Cstd::vector< gem5::AddressMonitor >
 Cstd::vector< gem5::AddrRange >
 Cstd::vector< gem5::AMDGPUVM::GEM5_PACKED >
 Cstd::vector< gem5::ArmISA::BrkPoint >
 Cstd::vector< gem5::ArmISA::PMU::CounterState >
 Cstd::vector< gem5::ArmISA::WatchPoint >
 Cstd::vector< gem5::ArmV8KvmCPU::IntRegInfo >
 Cstd::vector< gem5::ArmV8KvmCPU::MiscRegInfo >
 Cstd::vector< gem5::BaseCPU * >
 Cstd::vector< gem5::BaseGlobalEvent::BarrierEvent * >
 Cstd::vector< gem5::BaseInterrupts * >
 Cstd::vector< gem5::BaseISA * >
 Cstd::vector< gem5::BasePixelPump::PixelEvent * >
 Cstd::vector< gem5::bloom_filter::Base * >
 Cstd::vector< gem5::branch_prediction::MultiperspectivePerceptron::FilterEntry >
 Cstd::vector< gem5::branch_prediction::MultiperspectivePerceptron::HistorySpec * >
 Cstd::vector< gem5::branch_prediction::MultiperspectivePerceptron::ThreadData * >
 Cstd::vector< gem5::branch_prediction::ReturnAddrStack::AddrStack >
 Cstd::vector< gem5::branch_prediction::SimpleBTB::BTBEntry >
 Cstd::vector< gem5::branch_prediction::SimpleIndirectPredictor::ThreadInfo >
 Cstd::vector< gem5::branch_prediction::TAGEBase::ThreadHistory >
 Cstd::vector< gem5::CacheBlk >
 Cstd::vector< gem5::Check * >
 Cstd::vector< gem5::Clocked * >
 Cstd::vector< gem5::CoherentXBar::SnoopRespPort * >
 Cstd::vector< gem5::compression::Base * >
 Cstd::vector< gem5::compression::FrequentValues::CompData::CompressedValue >
 Cstd::vector< gem5::compression::FrequentValues::FrequentValuesListener * >
 Cstd::vector< gem5::compression::FrequentValues::VFTEntry >
 Cstd::vector< gem5::CompressionBlk >
 Cstd::vector< gem5::ComputeUnit * >
 Cstd::vector< gem5::ComputeUnit::DataPort >
 Cstd::vector< gem5::ComputeUnit::DTLBPort >
 Cstd::vector< gem5::CopyEngine::CopyEngineChannel * >
 Cstd::vector< gem5::CpuThread * >
 Cstd::vector< gem5::Cycles >
 Cstd::vector< gem5::debug::Flag * >
 Cstd::vector< gem5::DerivedClockDomain * >
 Cstd::vector< gem5::DmaThread * >
 Cstd::vector< gem5::Drainable * >
 Cstd::vector< gem5::Dueler >
 Cstd::vector< gem5::EmulatedDriver * >
 Cstd::vector< gem5::EtherSwitch::Interface * >
 Cstd::vector< gem5::FALRUBlk * >
 Cstd::vector< gem5::fastmodel::CortexA76 * >
 Cstd::vector< gem5::fastmodel::CortexR52 * >
 Cstd::vector< gem5::FetchUnit >
 Cstd::vector< gem5::FetchUnit::FetchBufDesc >
 Cstd::vector< gem5::Fiber * >
 Cstd::vector< gem5::FuncUnit * >
 Cstd::vector< gem5::GenericSatCounter >
 Cstd::vector< gem5::GenericTimerFrame * >
 Cstd::vector< gem5::GicV2::BankedRegs * >
 Cstd::vector< gem5::Gicv2mFrame * >
 Cstd::vector< gem5::Gicv3CPUInterface * >
 Cstd::vector< gem5::Gicv3Redistributor * >
 Cstd::vector< gem5::GpuWavefront * >
 Cstd::vector< gem5::IntSinkPinBase< gem5::RiscvISA::Interrupts > * >
 Cstd::vector< gem5::IntSinkPinBase< gem5::X86ISA::I82094AA > * >
 Cstd::vector< gem5::IntSinkPinBase< gem5::X86ISA::I8259 > * >
 Cstd::vector< gem5::IntSourcePinBase< gem5::X86IdeController > * >
 Cstd::vector< gem5::IntSourcePinBase< gem5::X86ISA::Cmos::X86RTC > * >
 Cstd::vector< gem5::IntSourcePinBase< gem5::X86ISA::I8042 > * >
 Cstd::vector< gem5::IntSourcePinBase< gem5::X86ISA::I8254 > * >
 Cstd::vector< gem5::IntSourcePinBase< gem5::X86ISA::I8259 > * >
 Cstd::vector< gem5::KvmVM::MemorySlot >
 Cstd::vector< gem5::LinearEquation >
 Cstd::vector< gem5::loader::MemoryImage::Segment >
 Cstd::vector< gem5::loader::ObjectFile * >
 Cstd::vector< gem5::LupioTMR::LupioTimer >
 Cstd::vector< gem5::memory::AbstractMemory * >
 Cstd::vector< gem5::memory::BackingStoreEntry >
 Cstd::vector< gem5::memory::DRAMInterface::Command >
 Cstd::vector< gem5::memory::DRAMInterface::Rank * >
 Cstd::vector< gem5::memory::NVMInterface::Rank * >
 Cstd::vector< gem5::MemPool >
 Cstd::vector< gem5::minor::Decode::DecodeThreadInfo >
 Cstd::vector< gem5::minor::Execute::ExecuteThreadInfo >
 Cstd::vector< gem5::minor::Fetch1::Fetch1ThreadInfo >
 Cstd::vector< gem5::minor::Fetch2::Fetch2ThreadInfo >
 Cstd::vector< gem5::minor::FUPipeline * >
 Cstd::vector< gem5::minor::InputBuffer< gem5::minor::ForwardInstData > >
 Cstd::vector< gem5::minor::InputBuffer< gem5::minor::ForwardLineData > >
 Cstd::vector< gem5::minor::Scoreboard >
 Cstd::vector< gem5::MinorFU * >
 Cstd::vector< gem5::MinorFUTiming * >
 Cstd::vector< gem5::MinorOpClass * >
 Cstd::vector< gem5::o3::DependencyEntry >
 Cstd::vector< gem5::o3::ElasticTrace::TraceInfo * >
 Cstd::vector< gem5::o3::LSQUnit >
 Cstd::vector< gem5::o3::ThreadState * >
 Cstd::vector< gem5::OpDesc * >
 Cstd::vector< gem5::OperandInfo >
 Cstd::vector< gem5::Packet * >
 Cstd::vector< gem5::Packet >
 Cstd::vector< gem5::partitioning_policy::BasePartitioningPolicy * >
 Cstd::vector< gem5::PhysRegId >
 Cstd::vector< gem5::Pixel >
 Cstd::vector< gem5::PoolManager * >
 Cstd::vector< gem5::PortTerminator::ReqPort >
 Cstd::vector< gem5::PortTerminator::RespPort >
 Cstd::vector< gem5::PowerModel * >
 Cstd::vector< gem5::PowerModelState * >
 Cstd::vector< gem5::PowerState * >
 Cstd::vector< gem5::prefetch::AccessMapPatternMatching::AccessMapEntry >
 Cstd::vector< gem5::prefetch::Base * >
 Cstd::vector< gem5::prefetch::DeltaCorrelatingPredictionTables::DCPTEntry >
 Cstd::vector< gem5::prefetch::IndirectMemory::IndirectPatternDetectorEntry >
 Cstd::vector< gem5::prefetch::IndirectMemory::PrefetchTableEntry >
 Cstd::vector< gem5::prefetch::IrregularStreamBuffer::AddressMapping >
 Cstd::vector< gem5::prefetch::IrregularStreamBuffer::AddressMappingEntry >
 Cstd::vector< gem5::prefetch::IrregularStreamBuffer::TrainingUnitEntry >
 Cstd::vector< gem5::prefetch::PIF::IndexEntry >
 Cstd::vector< gem5::prefetch::PIF::PrefetchListenerPC * >
 Cstd::vector< gem5::prefetch::SBOOE::Sandbox >
 Cstd::vector< gem5::prefetch::SBOOE::SandboxEntry >
 Cstd::vector< gem5::prefetch::SignaturePath::PatternEntry >
 Cstd::vector< gem5::prefetch::SignaturePath::PatternStrideEntry >
 Cstd::vector< gem5::prefetch::SignaturePath::SignatureEntry >
 Cstd::vector< gem5::prefetch::SignaturePathV2::GlobalHistoryEntry >
 Cstd::vector< gem5::prefetch::STeMS::ActiveGenerationTableEntry >
 Cstd::vector< gem5::prefetch::STeMS::ActiveGenerationTableEntry::SequenceEntry >
 Cstd::vector< gem5::prefetch::STeMS::RegionMissOrderBufferEntry >
 Cstd::vector< gem5::ProbeListener * >
 Cstd::vector< gem5::ProbeListenerArgBase< Arg > * >
 Cstd::vector< gem5::ProbeListenerArgBase< bool > * >
 Cstd::vector< gem5::ProbeListenerArgBase< gem5::CacheAccessProbeArg > * >
 Cstd::vector< gem5::ProbeListenerArgBase< gem5::CacheDataUpdateProbeArg > * >
 Cstd::vector< gem5::ProbeListenerArgBase< gem5::Packet > * >
 Cstd::vector< gem5::ProbeListenerArgBase< gem5::RefCountingPtr > * >
 Cstd::vector< gem5::ProbeListenerArgBase< gem5::Temperature > * >
 Cstd::vector< gem5::ProbeListenerArgBase< RequestPtr > * >
 Cstd::vector< gem5::ProbeListenerArgBase< std::pair > * >
 Cstd::vector< gem5::ProbeListenerArgBase< std::pair< gem5::RefCountingPtr, gem5::Packet > > * >
 Cstd::vector< gem5::ProbeListenerArgBase< std::pair< gem5::SimpleThread *, const gem5::RefCountingPtr > > * >
 Cstd::vector< gem5::ProbePoint * >
 Cstd::vector< gem5::Process * >
 Cstd::vector< gem5::ProtocolTester::GMTokenPort * >
 Cstd::vector< gem5::QueuedResponsePort * >
 Cstd::vector< gem5::RedirectPath * >
 Cstd::vector< gem5::RefCountingPtr >
 Cstd::vector< gem5::RegId >
 Cstd::vector< gem5::RegisterFileCache * >
 Cstd::vector< gem5::RequestorInfo >
 Cstd::vector< gem5::RequestPort * >
 Cstd::vector< gem5::ResponsePort * >
 Cstd::vector< gem5::RiscvISA::PMP::PmpEntry >
 Cstd::vector< gem5::RiscvISA::TlbEntry >
 Cstd::vector< gem5::ruby::AbstractController * >
 Cstd::vector< gem5::ruby::BankedArray::AccessRecord >
 Cstd::vector< gem5::ruby::BasicExtLink * >
 Cstd::vector< gem5::ruby::BasicIntLink * >
 Cstd::vector< gem5::ruby::FaultModel::system_conf >
 Cstd::vector< gem5::ruby::garnet::CreditLink * >
 Cstd::vector< gem5::ruby::garnet::flitBuffer >
 Cstd::vector< gem5::ruby::garnet::NetworkBridge * >
 Cstd::vector< gem5::ruby::garnet::NetworkInterface * >
 Cstd::vector< gem5::ruby::garnet::NetworkInterface::InputPort * >
 Cstd::vector< gem5::ruby::garnet::NetworkInterface::OutputPort * >
 Cstd::vector< gem5::ruby::garnet::NetworkLink * >
 Cstd::vector< gem5::ruby::garnet::OutVcState >
 Cstd::vector< gem5::ruby::garnet::Router * >
 Cstd::vector< gem5::ruby::garnet::VirtualChannel >
 Cstd::vector< gem5::ruby::MessageBuffer * >
 Cstd::vector< gem5::ruby::PerfectSwitch::OutputPort >
 Cstd::vector< gem5::ruby::PrefetchEntry >
 Cstd::vector< gem5::ruby::RubyPort * >
 Cstd::vector< gem5::ruby::RubyPort::MemResponsePort * >
 Cstd::vector< gem5::ruby::RubyPort::PioRequestPort * >
 Cstd::vector< gem5::ruby::RubyPrefetcher::NonUnitFilterEntry >
 Cstd::vector< gem5::ruby::RubyPrefetcher::UnitFilterEntry >
 Cstd::vector< gem5::ruby::Set >
 Cstd::vector< gem5::ruby::TBEStorage * >
 Cstd::vector< gem5::ruby::TraceRecord * >
 Cstd::vector< gem5::ScalarRegisterFile * >
 Cstd::vector< gem5::Scheduler >
 Cstd::vector< gem5::scmi::Communication * >
 Cstd::vector< gem5::SectorBlk >
 Cstd::vector< gem5::SectorSubBlk * >
 Cstd::vector< gem5::SectorSubBlk >
 Cstd::vector< gem5::SimpleCache::CPUSidePort >
 Cstd::vector< gem5::SimpleExecContext * >
 Cstd::vector< gem5::SimpleThread * >
 Cstd::vector< gem5::SMMUv3DeviceInterface * >
 Cstd::vector< gem5::statistics::DistData >
 Cstd::vector< gem5::statistics::Formula * >
 Cstd::vector< gem5::statistics::Group * >
 Cstd::vector< gem5::statistics::Histogram * >
 Cstd::vector< gem5::statistics::Info * >
 Cstd::vector< gem5::statistics::Scalar * >
 Cstd::vector< gem5::SuperBlk >
 Cstd::vector< gem5::System * >
 Cstd::vector< gem5::System::Threads::Thread >
 Cstd::vector< gem5::SystemCounterListener * >
 Cstd::vector< gem5::ThermalCapacitor * >
 Cstd::vector< gem5::ThermalDomain * >
 Cstd::vector< gem5::ThermalEntity * >
 Cstd::vector< gem5::ThermalNode * >
 Cstd::vector< gem5::ThermalReference * >
 Cstd::vector< gem5::ThermalResistor * >
 Cstd::vector< gem5::ThreadContext * >
 Cstd::vector< gem5::TimingExpr * >
 Cstd::vector< gem5::TLBCoalescer::CpuSidePort * >
 Cstd::vector< gem5::TLBCoalescer::MemSidePort * >
 Cstd::vector< gem5::TokenManager * >
 Cstd::vector< gem5::TraceCPU::ElasticDataGen::GraphNode * >
 Cstd::vector< gem5::UFSHostDevice::UFSSCSIDevice * >
 Cstd::vector< gem5::VecRegContainer >
 Cstd::vector< gem5::VectorRegisterFile * >
 Cstd::vector< gem5::VegaISA::GpuTLB * >
 Cstd::vector< gem5::VegaISA::GpuTLB::CpuSidePort * >
 Cstd::vector< gem5::VegaISA::GpuTLB::MemSidePort * >
 Cstd::vector< gem5::VegaTLBCoalescer::CpuSidePort * >
 Cstd::vector< gem5::VegaTLBCoalescer::MemSidePort * >
 Cstd::vector< gem5::VirtDescriptor >
 Cstd::vector< gem5::VirtQueue * >
 Cstd::vector< gem5::WaitClass >
 Cstd::vector< gem5::Wavefront * >
 Cstd::vector< gem5::WFBarrier >
 Cstd::vector< gem5::X86ISA::ACPI::MADT::Record * >
 Cstd::vector< gem5::X86ISA::ACPI::SysDescTable * >
 Cstd::vector< gem5::X86ISA::E820Entry * >
 Cstd::vector< gem5::X86ISA::GpuTLB::CpuSidePort * >
 Cstd::vector< gem5::X86ISA::GpuTLB::MemSidePort * >
 Cstd::vector< gem5::X86ISA::intelmp::BaseConfigEntry * >
 Cstd::vector< gem5::X86ISA::intelmp::ExtConfigEntry * >
 Cstd::vector< gem5::X86ISA::smbios::SMBiosStructure * >
 Cstd::vector< gem5::X86ISA::TlbEntry >
 Cstd::vector< Gicv3::IntTriggerType >
 Cstd::vector< GPUDynInstPtr >
 Cstd::vector< HistoryBuffer::iterator >
 Cstd::vector< hsa_kernel_dispatch_packet_s >
 Cstd::vector< hsa_signal_value_t >
 Cstd::vector< IF * >
 Cstd::vector< Index >
 Cstd::vector< IndexNodeMap >
 Cstd::vector< InstPtr >
 Cstd::vector< InstSeqNum >
 Cstd::vector< int * >
 Cstd::vector< int >
 Cstd::vector< int32_t >
 Cstd::vector< int64_t >
 Cstd::vector< int8_t >
 Cstd::vector< iris::MemorySpaceId >
 Cstd::vector< iris::MemorySpaceInfo >
 Cstd::vector< iris::MemorySupportedAddressTranslationResult >
 Cstd::vector< iris::ResourceId >
 Cstd::vector< IROUTER >
 Cstd::vector< LastWriter * >
 Cstd::vector< Location >
 Cstd::vector< LocProperty >
 Cstd::vector< LQEntry >
 Cstd::vector< MachInst >
 Cstd::vector< MemDepEntryPtr >
 Cstd::vector< MemPtr >
 Cstd::vector< MsgPtr >
 Cstd::vector< MSHR >
 Cstd::vector< MSIXPbaEntry >
 Cstd::vector< MSIXTable >
 Cstd::vector< MultiSocketSimpleSwitchAT::ConnectionInfo * >
 Cstd::vector< PCEvent * >
 Cstd::vector< PhysRegIdPtr >
 Cstd::vector< PollEvent * >
 Cstd::vector< PortID >
 Cstd::vector< PwrStatus >
 Cstd::vector< QueuedResponsePort * >
 Cstd::vector< Range >
 Cstd::vector< Register32 >
 Cstd::vector< Register64 >
 Cstd::vector< RegisterBankTest::Access >
 Cstd::vector< RegisterRaz >
 Cstd::vector< RegPtr >
 Cstd::vector< RegVal >
 Cstd::vector< ReqLayer * >
 Cstd::vector< RequestPtr >
 Cstd::vector< RespLayer * >
 Cstd::vector< Result >
 Cstd::vector< sc_core::sc_attr_base * >
 Cstd::vector< sc_core::sc_event * >
 Cstd::vector< sc_core::sc_event_finder * >
 Cstd::vector< sc_core::sc_export_base * >
 Cstd::vector< sc_core::sc_fifo_in_if< T > * >
 Cstd::vector< sc_core::sc_fifo_out_if< T > * >
 Cstd::vector< sc_core::sc_interface * >
 Cstd::vector< sc_core::sc_join * >
 Cstd::vector< sc_core::sc_object * >
 Cstd::vector< sc_core::sc_port_base * >
 Cstd::vector< sc_core::sc_signal_in_if< bool > * >
 Cstd::vector< sc_core::sc_signal_in_if< sc_dt::sc_logic > * >
 Cstd::vector< sc_core::sc_signal_in_if< sc_dt::sc_lv< W > > * >
 Cstd::vector< sc_core::sc_signal_in_if< T > * >
 Cstd::vector< sc_core::sc_signal_inout_if< bool > * >
 Cstd::vector< sc_core::sc_signal_inout_if< sc_dt::sc_logic > * >
 Cstd::vector< sc_core::sc_signal_inout_if< sc_dt::sc_lv< W > > * >
 Cstd::vector< sc_core::sc_signal_inout_if< T > * >
 Cstd::vector< sc_core::sc_spawn_options::Reset< const sc_core::sc_in< bool > > >
 Cstd::vector< sc_core::sc_spawn_options::Reset< const sc_core::sc_inout< bool > > >
 Cstd::vector< sc_core::sc_spawn_options::Reset< const sc_core::sc_out< bool > > >
 Cstd::vector< sc_core::sc_spawn_options::Reset< const sc_core::sc_signal_in_if< bool > > >
 Cstd::vector< sc_dt::uint64 >
 Cstd::vector< sc_fifo_in_if< T > * >
 Cstd::vector< sc_fifo_out_if< T > * >
 Cstd::vector< sc_gem5::Port::Binding * >
 Cstd::vector< sc_gem5::Port::Sensitivity * >
 Cstd::vector< sc_gem5::Reset * >
 Cstd::vector< sc_gem5::VcdTraceValBase * >
 Cstd::vector< sc_signal_in_if< bool > * >
 Cstd::vector< sc_signal_in_if< sc_dt::sc_bigint< W > > * >
 Cstd::vector< sc_signal_in_if< sc_dt::sc_biguint< W > > * >
 Cstd::vector< sc_signal_in_if< sc_dt::sc_int< W > > * >
 Cstd::vector< sc_signal_in_if< sc_dt::sc_logic > * >
 Cstd::vector< sc_signal_in_if< sc_dt::sc_lv< W > > * >
 Cstd::vector< sc_signal_in_if< sc_dt::sc_uint< W > > * >
 Cstd::vector< sc_signal_in_if< T > * >
 Cstd::vector< sc_signal_inout_if< bool > * >
 Cstd::vector< sc_signal_inout_if< sc_dt::sc_bigint< W > > * >
 Cstd::vector< sc_signal_inout_if< sc_dt::sc_biguint< W > > * >
 Cstd::vector< sc_signal_inout_if< sc_dt::sc_int< W > > * >
 Cstd::vector< sc_signal_inout_if< sc_dt::sc_logic > * >
 Cstd::vector< sc_signal_inout_if< sc_dt::sc_lv< W > > * >
 Cstd::vector< sc_signal_inout_if< sc_dt::sc_uint< W > > * >
 Cstd::vector< sc_signal_inout_if< T > * >
 Cstd::vector< sc_trace_params * >
 Cstd::vector< ScalarRegU32 >
 Cstd::vector< short >
 Cstd::vector< SignalInterruptFwIf * >
 Cstd::vector< size_type >
 Cstd::vector< SnoopRespLayer * >
 Cstd::vector< SQEntry >
 Cstd::vector< SrcClockDomain * >
 Cstd::vector< SSID >
 Cstd::vector< StaticSensitivity * >
 Cstd::vector< statistics::Counter >
 Cstd::vector< std::deque >
 Cstd::vector< std::deque< std::pair< GPUDynInstPtr, SCH_STATUS > > >
 Cstd::vector< std::deque< struct gem5::FlashDevice::CallBackEntry > >
 Cstd::vector< std::deque< tlm::tlm_generic_payload * > >
 Cstd::vector< std::list >
 Cstd::vector< std::list< std::unique_ptr< gem5::MemBackdoor > > >
 Cstd::vector< std::map< uint32_t, gem5::ruby::AbstractController * > >
 Cstd::vector< std::pair >
 Cstd::vector< std::pair< Addr, std::vector< uint8_t > > >
 Cstd::vector< std::pair< gem5::TCPIface::NodeInfo, int > >
 Cstd::vector< std::pair< gem5::Wavefront *, bool > >
 Cstd::vector< std::pair< int, AtomicOpFunctor * > >
 Cstd::vector< std::pair< std::string, sc_gem5::VcdTraceValBase * > >
 Cstd::vector< std::pair< uint32_t, ExceptionCode > >
 Cstd::vector< std::queue< int > >
 Cstd::vector< std::shared_ptr< gem5::ruby::garnet::InputUnit > >
 Cstd::vector< std::shared_ptr< gem5::ruby::garnet::OutputUnit > >
 Cstd::vector< std::string >
 Cstd::vector< std::thread >
 Cstd::vector< std::tuple< void *, uint32_t, Addr > >
 Cstd::vector< std::unique_ptr< gem5::ArmISA::PMU::RegularEvent::RegularProbe > >
 Cstd::vector< std::unique_ptr< gem5::BaseCache::CacheCmdStats > >
 Cstd::vector< std::unique_ptr< gem5::BaseCPU::CommitCPUStats > >
 Cstd::vector< std::unique_ptr< gem5::BaseCPU::ExecuteCPUStats > >
 Cstd::vector< std::unique_ptr< gem5::BaseCPU::FetchCPUStats > >
 Cstd::vector< std::unique_ptr< gem5::BaseMemProbe::PacketListener > >
 Cstd::vector< std::unique_ptr< gem5::BaseSemihosting::FileBase > >
 Cstd::vector< std::unique_ptr< gem5::compression::DictionaryCompressor::Pattern > >
 Cstd::vector< std::unique_ptr< gem5::CpuLocalTimer::Timer > >
 Cstd::vector< std::unique_ptr< gem5::fastmodel::ScxEvsCortexR52::CorePins > >
 Cstd::vector< std::unique_ptr< gem5::fastmodel::SignalReceiver > >
 Cstd::vector< std::unique_ptr< gem5::fastmodel::SignalSender > >
 Cstd::vector< std::unique_ptr< gem5::GenericTimer::CoreTimers > >
 Cstd::vector< std::unique_ptr< gem5::IntSinkPinBase > >
 Cstd::vector< std::unique_ptr< gem5::IntSourcePinBase > >
 Cstd::vector< std::unique_ptr< gem5::IntSourcePinBase< gem5::ArmSigInterruptPinGen > > >
 Cstd::vector< std::unique_ptr< gem5::IntSourcePinBase< gem5::fastmodel::GIC > > >
 Cstd::vector< std::unique_ptr< gem5::loader::ObjectFile > >
 Cstd::vector< std::unique_ptr< gem5::PCStateBase > >
 Cstd::vector< std::unique_ptr< gem5::RegisterBank::RegisterBase > >
 Cstd::vector< std::unique_ptr< gem5::ruby::Network > >
 Cstd::vector< std::unique_ptr< gem5::ruby::WeightBased::LinkInfo > >
 Cstd::vector< std::unique_ptr< gem5::SignalSourcePort< bool > > >
 Cstd::vector< std::unique_ptr< sc_gem5::TlmInitiatorBaseWrapper > >
 Cstd::vector< std::unique_ptr< sc_gem5::TlmTargetBaseWrapper > >
 Cstd::vector< std::unique_ptr< SignalInitiator< uint64_t > > >
 Cstd::vector< std::vector >
 Cstd::vector< std::vector< Addr > >
 Cstd::vector< std::vector< bool > >
 Cstd::vector< std::vector< double > >
 Cstd::vector< std::vector< Entry > >
 Cstd::vector< std::vector< gem5::branch_prediction::SimpleIndirectPredictor::IPredEntry > >
 Cstd::vector< std::vector< gem5::ReplaceableEntry * > >
 Cstd::vector< std::vector< gem5::ruby::AbstractCacheEntry * > >
 Cstd::vector< std::vector< gem5::ruby::MessageBuffer * > >
 Cstd::vector< std::vector< gem5::ruby::NetDest > >
 Cstd::vector< std::vector< gem5::statistics::Histogram * > >
 Cstd::vector< std::vector< gem5::statistics::Scalar * > >
 Cstd::vector< std::vector< gem5::Wavefront * > >
 Cstd::vector< std::vector< int > >
 Cstd::vector< std::vector< Register32 > >
 Cstd::vector< std::vector< RegVal > >
 Cstd::vector< std::vector< ReplData > >
 Cstd::vector< std::vector< short int > >
 Cstd::vector< std::vector< std::array< bool, 2 > > >
 Cstd::vector< std::vector< std::string > >
 Cstd::vector< std::vector< std::vector< Addr > > >
 Cstd::vector< std::vector< std::vector< bool > > >
 Cstd::vector< std::vector< std::vector< gem5::ruby::MessageBuffer * > > >
 Cstd::vector< std::vector< uint32_t > >
 Cstd::vector< std::vector< unsigned int > >
 Cstd::vector< std::vector< unsigned short int > >
 Cstd::vector< Storage * >
 Cstd::vector< struct gem5::FlashDevice::PageMapEntry >
 Cstd::vector< struct vring_used_elem >
 Cstd::vector< Symbol >
 Cstd::vector< T * >
 Cstd::vector< ThreadID >
 Cstd::vector< Tick >
 Cstd::vector< tlm::tlm_bw_transport_if< tlm::tlm_base_protocol_types > * >
 ►Cstd::vector< tlm::tlm_extension_base * >
 Cstd::vector< tlm::tlm_fw_transport_if< tlm::tlm_base_protocol_types > * >
 Cstd::vector< tlm::tlm_generic_payload * >
 Cstd::vector< tlm::tlm_master_if< REQ, RSP > * >
 Cstd::vector< tlm::tlm_slave_if< REQ, RSP > * >
 Cstd::vector< tlm::tlm_transport_if< REQ, RSP > * >
 Cstd::vector< tlm_fw_transport_if< my_extended_payload_types > * >
 Cstd::vector< tlm_fw_transport_if< tlm::tlm_base_protocol_types > * >
 Cstd::vector< tlm_fw_transport_if< tlm_base_protocol_types > * >
 Cstd::vector< tlm_fw_transport_if< TYPES > * >
 Cstd::vector< tlm_nonblocking_get_if< T > * >
 Cstd::vector< tlm_nonblocking_peek_if< T > * >
 Cstd::vector< tlm_nonblocking_put_if< T > * >
 Cstd::vector< tlm_utils::callback_binder_bw< tlm::tlm_base_protocol_types > * >
 Cstd::vector< tlm_utils::callback_binder_fw< tlm::tlm_base_protocol_types > * >
 Cstd::vector< tlm_utils::instance_specific_extensions_per_accessor * >
 ►Cstd::vector< tlm_utils::ispex_base * >
 Cstd::vector< tlm_utils::simple_target_socket_b::fw_process::process_handle_class * >
 Cstd::vector< tlm_utils::simple_target_socket_tagged_b::fw_process::process_handle_class * >
 Cstd::vector< uint32_t >
 Cstd::vector< uint64_t >
 Cstd::vector< uint8_t >
 Cstd::vector< unsigned >
 Cstd::vector< unsigned int >
 Cstd::vector< unsigned int short >
 Cstd::vector< unsigned short int >
 Cstd::vector< value_type >
 Cstd::vector< VecRegContainer >
 Cstd::vector< VegaTlbEntry >
 Cstd::vector< VirtDescriptor::Index >
 Cstd::vector< VirtualReg >
 Cstd::vector< VNET_type >
 Cstd::vector< void * >
 Cstd::vector< WriteQueueEntry >
 Cgem5::statistics::VectorProxy< Stat >
 Cgem5::VerticalSlice< ElemType, Container, FromTile >Provides a view of a vertical slice of either a MatStore or a Tile
 Cgem5::VirtDescriptorVirtIO descriptor (chain) wrapper
 Cgem5::VirtQueue::VirtRing< T >VirtIO ring buffer wrapper
 Cgem5::VirtQueue::VirtRing< struct vring_used_elem >
 Cgem5::VirtQueue::VirtRing< VirtDescriptor::Index >
 Cgem5::ruby::garnet::VirtualChannel
 Cgem5::sinic::Device::VirtualReg
 Cgem5::VMA
 ►Cgem5::VncKeyboardA device that expects to receive input from the vnc server should derrive (through mulitple inheritence if necessary from VncKeyboard or VncMouse and call setKeyboard() or setMouse() respectively on the vnc server
 ►Cgem5::VncMouse
 Cgem5::ArmISA::VReg128-bit NEON vector register
 Cvring
 Cvring_avail
 Cvring_desc
 Cvring_used
 Cvring_used_elem
 Cgem5::X86ISA::I386Process::VSyscallPage
 Cgem5::X86ISA::X86_64Process::VSyscallPage
 Cgem5::WaitClass
 Cgem5::WaiterStateWaiterState defines internal state of a waiter thread
 Cgem5::ArmISA::TableWalker::WalkerState
 Cgem5::RiscvISA::Walker::WalkerState
 Cgem5::VegaISA::Walker::WalkerState
 Cgem5::X86ISA::Walker::WalkerState
 Cgem5::ArmISA::WatchPoint
 Cgem5::WFBarrierWF barrier slots
 Cgem5::WholeTranslationStateThis class captures the state of an address translation
 Cgem5::TimeBuffer< T >::wire
 Csc_dt::word_list
 Csc_dt::word_short
 Csc_gem5::WriteChecker< WRITER_POLICY >
 Csc_gem5::WriteChecker< sc_core::SC_MANY_WRITERS >
 Csc_gem5::WriteChecker< sc_core::SC_ONE_WRITER >
 Cgem5::MemChecker::WriteClusterCaptures sets of writes where all writes are overlapping with at least one other write
 Cgem5::ruby::WriteMask
 Cgem5::UFSHostDevice::writeToDiskBurstDisk transfer burst information
 ►CX
 Cgem5::X86ISA::X86CPUID
 Cgem5::X86PseudoInstABI
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