pagetable.hh File Reference

#include "arch/amdgpu/vega/page_size.hh"
#include "base/bitunion.hh"
#include "base/types.hh"
#include "sim/serialize.hh"

Go to the source code of this file.

Namespaces
namespace	gem5
	Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
namespace	gem5::VegaISA
	classes that represnt vector/scalar operands in VEGA ISA.

Functions
	gem5::VegaISA::BitUnion64 (PageTableEntry) Bitfield< 58
	The page table entry is reverse engineered from the macros here:
	gem5::VegaISA::EndBitUnion (PageTableEntry) BitUnion64(PageDirectoryEntry) Bitfield< 63

Variables
	gem5::VegaISA::m
Bitfield< 56 >	gem5::VegaISA::f
Bitfield< 55 >	gem5::VegaISA::l
Bitfield< 53, 52 >	gem5::VegaISA::sw
Bitfield< 51 >	gem5::VegaISA::t
Bitfield< 47, 12 >	gem5::VegaISA::ppn
Bitfield< 11, 7 >	gem5::VegaISA::fragment
Bitfield< 6 >	gem5::VegaISA::w
Bitfield< 5 >	gem5::VegaISA::r
Bitfield< 4 >	gem5::VegaISA::x
Bitfield< 3 >	gem5::VegaISA::z
Bitfield< 2 >	gem5::VegaISA::c
Bitfield< 1 >	gem5::VegaISA::s
Bitfield< 0 >	gem5::VegaISA::v
	gem5::VegaISA::blockFragmentSize
Bitfield< 54 >	gem5::VegaISA::p
Bitfield< 47, 6 >	gem5::VegaISA::baseAddr