gem5  v22.0.0.2
pagetable.hh
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31 
32 #ifndef __ARCH_AMDGPU_VEGA_PAGETABLE_H__
33 #define __ARCH_AMDGPU_VEGA_PAGETABLE_H__
34 
36 #include "base/bitunion.hh"
37 #include "base/types.hh"
38 #include "sim/serialize.hh"
39 
40 namespace gem5
41 {
42 namespace VegaISA
43 {
44 
51 BitUnion64(PageTableEntry)
52  Bitfield<58,57> m;
53  Bitfield<56> f;
54  Bitfield<55> l;
55  Bitfield<53,52> sw;
56  Bitfield<51> t;
57  Bitfield<47, 12> ppn;
58  Bitfield<11, 7> fragment;
59  Bitfield<6> w;
60  Bitfield<5> r;
61  Bitfield<4> x;
62  Bitfield<3> z;
63  Bitfield<2> c;
64  Bitfield<1> s;
65  Bitfield<0> v;
67 
68 BitUnion64(PageDirectoryEntry)
69  Bitfield<63,59> blockFragmentSize;
70  Bitfield<54> p;
71  Bitfield<47, 6> baseAddr;
72  Bitfield<2> c;
73  Bitfield<1> s;
74  Bitfield<0> v;
75 EndBitUnion(PageDirectoryEntry)
76 
77 struct VegaTlbEntry : public Serializable
78 {
79  uint16_t vmid;
80 
81  // The base of the physical page.
82  Addr paddr;
83 
84  // The beginning of the virtual page this entry maps.
85  Addr vaddr;
86  // The size of the page this represents, in address bits.
87  unsigned logBytes;
88 
89  PageTableEntry pte;
90 
91  // Read permission is always available, assuming it isn't blocked by
92  // other mechanisms.
93  bool writable() { return pte.w; };
94  // Whether the page is cacheable or not.
95  bool uncacheable() { return !pte.c; };
96  // Whether or not memory on this page can be executed.
97  bool noExec() { return !pte.x; };
98 
99  // A sequence number to keep track of LRU.
100  uint64_t lruSeq;
101 
102  VegaTlbEntry()
103  : vmid(0), paddr(0), vaddr(0), logBytes(PageShift), pte(), lruSeq(0)
104  {}
105 
106  VegaTlbEntry(Addr _vmid, Addr _vaddr, Addr _paddr, unsigned _logBytes,
107  PageTableEntry _pte)
108  : vmid(_vmid), paddr(_paddr), vaddr(_vaddr), logBytes(_logBytes),
109  pte(_pte), lruSeq(0)
110  {}
111 
112  // Return the page size in bytes
113  Addr size() const
114  {
115  return (static_cast<Addr>(1) << logBytes);
116  }
117 
118  void serialize(CheckpointOut &cp) const override;
119  void unserialize(CheckpointIn &cp) override;
120 };
121 
122 } // namespace VegaISA
123 } // namespace gem5
124 
125 #endif // __ARCH_AMDGPU_VEGA_PAGETABLE_H__
gem5::VegaISA::s
Bitfield< 1 > s
Definition: pagetable.hh:64
gem5::unserialize
void unserialize(ThreadContext &tc, CheckpointIn &cp)
Definition: thread_context.cc:264
gem5::VegaISA::f
Bitfield< 56 > f
Definition: pagetable.hh:53
gem5::VegaISA::m
m
Definition: pagetable.hh:52
serialize.hh
gem5::VegaISA::PageShift
const Addr PageShift
Definition: page_size.hh:41
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::VegaISA::sw
Bitfield< 53, 52 > sw
Definition: pagetable.hh:55
gem5::VegaISA::w
Bitfield< 6 > w
Definition: pagetable.hh:59
gem5::VegaISA::r
Bitfield< 5 > r
Definition: pagetable.hh:60
gem5::VegaISA::baseAddr
Bitfield< 47, 6 > baseAddr
Definition: pagetable.hh:71
gem5::X86ISA::writable
Bitfield< 12 > writable
Definition: misc.hh:994
page_size.hh
gem5::VegaISA::fragment
Bitfield< 11, 7 > fragment
Definition: pagetable.hh:58
gem5::VegaISA::c
Bitfield< 2 > c
Definition: pagetable.hh:63
gem5::Serializable
Basic support for object serialization.
Definition: serialize.hh:169
gem5::VegaISA::t
Bitfield< 51 > t
Definition: pagetable.hh:56
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::VegaISA::EndBitUnion
EndBitUnion(PageTableEntry) BitUnion64(PageDirectoryEntry) Bitfield< 63
gem5::VegaISA::x
Bitfield< 4 > x
Definition: pagetable.hh:61
bitunion.hh
gem5::VegaISA::blockFragmentSize
blockFragmentSize
Definition: pagetable.hh:69
gem5::SparcISA::PageTableEntry
Definition: pagetable.hh:68
gem5::VegaISA::BitUnion64
BitUnion64(PageTableEntry) Bitfield< 58
The page table entry is reverse engineered from the macros here:
gem5::serialize
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
Definition: thread_context.cc:215
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::VegaISA::v
Bitfield< 0 > v
Definition: pagetable.hh:65
gem5::VegaISA::ppn
Bitfield< 47, 12 > ppn
Definition: pagetable.hh:57
types.hh
gem5::VegaISA::l
Bitfield< 55 > l
Definition: pagetable.hh:54
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::VegaISA::z
Bitfield< 3 > z
Definition: pagetable.hh:62
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37

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